imx31_icu.c revision 1.1.2.4
1 /*- 2 * Copyright (c) 2007 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: imx31_icu.c,v 1.1.2.4 2007/09/12 06:19:45 matt Exp $"); 38 39 #define _INTR_PRIVATE 40 41 #include "locators.h" 42 43 #include <sys/param.h> 44 #include <sys/evcnt.h> 45 #include <sys/device.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <machine/intr.h> 50 51 #include <arm/cpu.h> 52 #include <arm/armreg.h> 53 #include <arm/cpufunc.h> 54 55 #include <machine/autoconf.h> 56 #include <machine/atomic.h> 57 #include <machine/bus.h> 58 59 #include <arm/imx/imx31reg.h> 60 #include <arm/imx/imx31var.h> 61 62 static void avic_unblock_irqs(struct pic_softc *, size_t, uint32_t); 63 static void avic_block_irqs(struct pic_softc *, size_t, uint32_t); 64 static void avic_establish_irq(struct pic_softc *, int, int, int); 65 static void avic_source_name(struct pic_softc *, int, char *, size_t); 66 67 const struct pic_ops avic_pic_ops = { 68 .pic_unblock_irqs = avic_unblock_irqs, 69 .pic_block_irqs = avic_block_irqs, 70 .pic_establish_irq = avic_establish_irq, 71 .pic_source_name = avic_source_name 72 }; 73 74 struct avic_softc { 75 struct device avic_dv; 76 struct pic_softc avic_pic; 77 bus_space_tag_t avic_memt; 78 bus_space_handle_t avic_memh; 79 }; 80 81 extern struct cfdriver avic_cd; 82 83 #define INTC_READ(avic, reg) \ 84 bus_space_read_4((avic)->avic_memt, (avic)->avic_memh, (reg)) 85 #define INTC_WRITE(avic, reg, val) \ 86 bus_space_write_4((avic)->avic_memt, (avic)->avic_memh, (reg), (val)) 87 #define HW_TO_SW_IPL(ipl) ((ipl) + 1) 88 #define SW_TO_HW_IPL(ipl) ((ipl) - 1) 89 90 void 91 avic_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask) 92 { 93 struct avic_softc * const avic = (void *) pic; 94 #if 0 95 if (irq_base == 0) 96 INTC_WRITE(avic, IMX31_INTENABLEL, irq_mask); 97 else 98 INTC_WRITE(avic, IMX31_INTENABLEH, irq_mask); 99 #else 100 uint32_t irq; 101 while ((irq = ffs(irq_mask)) != 0) { 102 irq--; 103 irq_base += irq; 104 irq_mask >>= irq; 105 INTC_WRITE(avic, IMX31_INTENNUM, irq_base); 106 } 107 #endif 108 } 109 110 void 111 avic_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask) 112 { 113 struct avic_softc * const avic = (void *) pic; 114 #if 0 115 if (irq_base == 0) 116 INTC_WRITE(avic, IMX31_INTDISABLEL, irq_mask); 117 else 118 INTC_WRITE(avic, IMX31_INTDISABLEH, irq_mask); 119 #else 120 uint32_t irq; 121 while ((irq = ffs(irq_mask)) != 0) { 122 irq--; 123 irq_base += irq; 124 irq_mask >>= irq; 125 INTC_WRITE(avic, IMX31_INTDISNUM, irq_base); 126 } 127 #endif 128 } 129 130 void 131 avic_establish_irq(struct pic_softc *pic, int irq, int ipl, int type) 132 { 133 struct avic_softc * const avic = (void *) pic; 134 bus_addr_t priority_reg; 135 int priority_shift; 136 uint32_t v; 137 138 KASSERT(irq < 64); 139 KASSERT(ipl < 16); 140 141 priority_reg = IMX31_NIPRIORITY0 - (irq >> 3); 142 priority_shift = (irq & 7) * 4; 143 v = INTC_READ(avic, priority_reg); 144 v &= ~(0x0f << priority_shift); 145 v |= SW_TO_HW_IPL(ipl) << priority_shift; 146 INTC_WRITE(avic, priority_reg, v); 147 148 KASSERT(type == IST_LEVEL); 149 } 150 151 static const char * const avic_intr_source_names[] = AVIC_INTR_SOURCE_NAMES; 152 153 void 154 avic_source_name(struct pic_softc *pic, int irq, char *buf, size_t len) 155 { 156 strlcpy(buf, avic_intr_source_names[irq], len); 157 } 158 159 void 160 imx31_irq_handler(void *frame) 161 { 162 struct avic_softc * const avic = avic_cd.cd_devs[0]; 163 struct pic_softc * const pic = &avic->avic_pic; 164 int32_t saved_nimask; 165 int32_t irq; 166 int ipl, newipl, oldipl; 167 168 saved_nimask = INTC_READ(avic, IMX31_NIMASK); 169 for (;;) { 170 irq = INTC_READ(avic, IMX31_NIVECSR); 171 if (irq < 0) 172 break; 173 ipl = (int16_t) irq; 174 KASSERT(ipl >= 0); 175 irq >>= 16; 176 KASSERT(irq < 64); 177 KASSERT(pic->pic_sources[irq] != NULL); 178 179 /* 180 * If this interrupt is not above the current spl, 181 * mark it as pending and try again. 182 */ 183 newipl = HW_TO_SW_IPL(ipl); 184 if (newipl <= curcpu()->ci_cpl) { 185 pic_mark_pending(pic, irq); 186 continue; 187 } 188 189 /* 190 * Before enabling interrupts, mask out lower priority 191 * interrupts and raise SPL to its equivalent. 192 */ 193 194 INTC_WRITE(avic, IMX31_NIMASK, ipl); 195 oldipl = _splraise(newipl); 196 cpsie(I32_bit); 197 198 pic_dispatch(pic->pic_sources[irq], frame); 199 200 /* 201 * Disable interrupts again. Drop SPL. Restore saved 202 * HW interrupt level. 203 */ 204 cpsid(I32_bit); 205 splx(oldipl); 206 INTC_WRITE(avic, IMX31_NIMASK, saved_nimask); 207 } 208 } 209 210 static int avic_match(device_t, cfdata_t, void *); 211 static void avic_attach(device_t, device_t, void *); 212 213 CFATTACH_DECL(avic, 214 sizeof(struct avic_softc), 215 avic_match, avic_attach, 216 NULL, NULL); 217 218 int 219 avic_match(device_t parent, cfdata_t self, void *aux) 220 { 221 struct ahb_attach_args * const ahba = aux; 222 223 if (ahba->ahba_addr != INTC_BASE) 224 return 0; 225 226 return 1; 227 } 228 229 void 230 avic_attach(device_t parent, device_t self, void *aux) 231 { 232 struct avic_softc * const avic = (void *) self; 233 struct ahb_attach_args * const ahba = aux; 234 int error; 235 236 KASSERT(ahba->ahba_irqbase != AHBCF_IRQBASE_DEFAULT); 237 KASSERT(self->dv_unit == 0); 238 239 if (ahba->ahba_size == AHBCF_SIZE_DEFAULT) 240 ahba->ahba_size = INTC_SIZE; 241 242 avic->avic_memt = ahba->ahba_memt; 243 error = bus_space_map(avic->avic_memt, ahba->ahba_addr, ahba->ahba_size, 244 0, &avic->avic_memh); 245 if (error) 246 panic("avic_attach: failed to map register %#lx-%#lx: %d", 247 ahba->ahba_addr, ahba->ahba_addr + ahba->ahba_size - 1, 248 error); 249 250 avic->avic_pic.pic_ops = &avic_pic_ops; 251 avic->avic_pic.pic_maxsources = 64; 252 strlcpy(avic->avic_pic.pic_name, self->dv_xname, 253 sizeof(avic->avic_pic.pic_name)); 254 255 pic_add(&avic->avic_pic, ahba->ahba_irqbase); 256 aprint_normal(": interrupts %d..%d\n", 257 ahba->ahba_irqbase, ahba->ahba_irqbase + 63); 258 #if 0 259 softintr_init(); 260 #endif 261 } 262
Indexes created Wed Oct 01 19:09:53 GMT 2025