imx31_icu.c revision 1.2
1 /* $NetBSD: imx31_icu.c,v 1.2 2008/04/27 18:58:44 matt Exp $ */ 2 /*- 3 * Copyright (c) 2007 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of The NetBSD Foundation nor the names of its 22 * contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: imx31_icu.c,v 1.2 2008/04/27 18:58:44 matt Exp $"); 39 40 #define _INTR_PRIVATE 41 42 #include "locators.h" 43 44 #include <sys/param.h> 45 #include <sys/evcnt.h> 46 #include <sys/device.h> 47 48 #include <uvm/uvm_extern.h> 49 50 #include <machine/intr.h> 51 52 #include <arm/cpu.h> 53 #include <arm/armreg.h> 54 #include <arm/cpufunc.h> 55 56 #include <machine/autoconf.h> 57 #include <machine/atomic.h> 58 #include <machine/bus.h> 59 60 #include <arm/imx/imx31reg.h> 61 #include <arm/imx/imx31var.h> 62 63 static void avic_unblock_irqs(struct pic_softc *, size_t, uint32_t); 64 static void avic_block_irqs(struct pic_softc *, size_t, uint32_t); 65 static void avic_establish_irq(struct pic_softc *, struct intrsource *); 66 static void avic_source_name(struct pic_softc *, int, char *, size_t); 67 68 const struct pic_ops avic_pic_ops = { 69 .pic_unblock_irqs = avic_unblock_irqs, 70 .pic_block_irqs = avic_block_irqs, 71 .pic_establish_irq = avic_establish_irq, 72 .pic_source_name = avic_source_name 73 }; 74 75 struct avic_softc { 76 struct device avic_dv; 77 struct pic_softc avic_pic; 78 bus_space_tag_t avic_memt; 79 bus_space_handle_t avic_memh; 80 }; 81 82 extern struct cfdriver avic_cd; 83 84 #define INTC_READ(avic, reg) \ 85 bus_space_read_4((avic)->avic_memt, (avic)->avic_memh, (reg)) 86 #define INTC_WRITE(avic, reg, val) \ 87 bus_space_write_4((avic)->avic_memt, (avic)->avic_memh, (reg), (val)) 88 #define HW_TO_SW_IPL(ipl) ((ipl) + 1) 89 #define SW_TO_HW_IPL(ipl) ((ipl) - 1) 90 91 void 92 avic_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask) 93 { 94 struct avic_softc * const avic = (void *) pic; 95 #if 0 96 if (irq_base == 0) 97 INTC_WRITE(avic, IMX31_INTENABLEL, irq_mask); 98 else 99 INTC_WRITE(avic, IMX31_INTENABLEH, irq_mask); 100 #else 101 uint32_t irq; 102 while ((irq = ffs(irq_mask)) != 0) { 103 irq--; 104 irq_base += irq; 105 irq_mask >>= irq; 106 INTC_WRITE(avic, IMX31_INTENNUM, irq_base); 107 } 108 #endif 109 } 110 111 void 112 avic_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask) 113 { 114 struct avic_softc * const avic = (void *) pic; 115 #if 0 116 if (irq_base == 0) 117 INTC_WRITE(avic, IMX31_INTDISABLEL, irq_mask); 118 else 119 INTC_WRITE(avic, IMX31_INTDISABLEH, irq_mask); 120 #else 121 uint32_t irq; 122 while ((irq = ffs(irq_mask)) != 0) { 123 irq--; 124 irq_base += irq; 125 irq_mask >>= irq; 126 INTC_WRITE(avic, IMX31_INTDISNUM, irq_base); 127 } 128 #endif 129 } 130 131 void 132 avic_establish_irq(struct pic_softc *pic, struct intrsource *is) 133 { 134 struct avic_softc * const avic = (void *) pic; 135 bus_addr_t priority_reg; 136 int priority_shift; 137 uint32_t v; 138 139 KASSERT(is->is_irq < 64); 140 KASSERT(is->is_ipl < 16); 141 142 priority_reg = IMX31_NIPRIORITY0 - (is->is_irq >> 3); 143 priority_shift = (is->is_irq & 7) * 4; 144 v = INTC_READ(avic, priority_reg); 145 v &= ~(0x0f << priority_shift); 146 v |= SW_TO_HW_IPL(is->is_ipl) << priority_shift; 147 INTC_WRITE(avic, priority_reg, v); 148 149 KASSERT(is->is_type == IST_LEVEL); 150 } 151 152 static const char * const avic_intr_source_names[] = AVIC_INTR_SOURCE_NAMES; 153 154 void 155 avic_source_name(struct pic_softc *pic, int irq, char *buf, size_t len) 156 { 157 strlcpy(buf, avic_intr_source_names[irq], len); 158 } 159 160 void 161 imx31_irq_handler(void *frame) 162 { 163 struct avic_softc * const avic = avic_cd.cd_devs[0]; 164 struct pic_softc * const pic = &avic->avic_pic; 165 int32_t saved_nimask; 166 int32_t irq; 167 int ipl, newipl, oldipl; 168 169 saved_nimask = INTC_READ(avic, IMX31_NIMASK); 170 for (;;) { 171 irq = INTC_READ(avic, IMX31_NIVECSR); 172 if (irq < 0) 173 break; 174 ipl = (int16_t) irq; 175 KASSERT(ipl >= 0); 176 irq >>= 16; 177 KASSERT(irq < 64); 178 KASSERT(pic->pic_sources[irq] != NULL); 179 180 /* 181 * If this interrupt is not above the current spl, 182 * mark it as pending and try again. 183 */ 184 newipl = HW_TO_SW_IPL(ipl); 185 if (newipl <= curcpu()->ci_cpl) { 186 pic_mark_pending(pic, irq); 187 continue; 188 } 189 190 /* 191 * Before enabling interrupts, mask out lower priority 192 * interrupts and raise SPL to its equivalent. 193 */ 194 195 INTC_WRITE(avic, IMX31_NIMASK, ipl); 196 oldipl = _splraise(newipl); 197 cpsie(I32_bit); 198 199 pic_dispatch(pic->pic_sources[irq], frame); 200 201 /* 202 * Disable interrupts again. Drop SPL. Restore saved 203 * HW interrupt level. 204 */ 205 cpsid(I32_bit); 206 splx(oldipl); 207 INTC_WRITE(avic, IMX31_NIMASK, saved_nimask); 208 } 209 } 210 211 static int avic_match(device_t, cfdata_t, void *); 212 static void avic_attach(device_t, device_t, void *); 213 214 CFATTACH_DECL(avic, 215 sizeof(struct avic_softc), 216 avic_match, avic_attach, 217 NULL, NULL); 218 219 int 220 avic_match(device_t parent, cfdata_t self, void *aux) 221 { 222 struct ahb_attach_args * const ahba = aux; 223 224 if (ahba->ahba_addr != INTC_BASE) 225 return 0; 226 227 return 1; 228 } 229 230 void 231 avic_attach(device_t parent, device_t self, void *aux) 232 { 233 struct avic_softc * const avic = (void *) self; 234 struct ahb_attach_args * const ahba = aux; 235 int error; 236 237 KASSERT(ahba->ahba_irqbase != AHBCF_IRQBASE_DEFAULT); 238 KASSERT(self->dv_unit == 0); 239 240 if (ahba->ahba_size == AHBCF_SIZE_DEFAULT) 241 ahba->ahba_size = INTC_SIZE; 242 243 avic->avic_memt = ahba->ahba_memt; 244 error = bus_space_map(avic->avic_memt, ahba->ahba_addr, ahba->ahba_size, 245 0, &avic->avic_memh); 246 if (error) 247 panic("avic_attach: failed to map register %#lx-%#lx: %d", 248 ahba->ahba_addr, ahba->ahba_addr + ahba->ahba_size - 1, 249 error); 250 251 avic->avic_pic.pic_ops = &avic_pic_ops; 252 avic->avic_pic.pic_maxsources = 64; 253 strlcpy(avic->avic_pic.pic_name, self->dv_xname, 254 sizeof(avic->avic_pic.pic_name)); 255 256 pic_add(&avic->avic_pic, ahba->ahba_irqbase); 257 aprint_normal(": interrupts %d..%d\n", 258 ahba->ahba_irqbase, ahba->ahba_irqbase + 63); 259 #if 0 260 softintr_init(); 261 #endif 262 } 263
Indexes created Tue Sep 30 20:09:53 GMT 2025