imx50_iomuxreg.h revision 1.1.2.2
1 /* $NetBSD: imx50_iomuxreg.h,v 1.1.2.2 2014/08/10 06:53:51 tls Exp $ */ 2 3 /* 4 * Copyright (c) 2012 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * This file was generated automatically from PDF file by mkiomuxreg_imx50.rb 31 */ 32 33 #ifndef _ARM_IMX_IMX50_IOMUXREG_H 34 #define _ARM_IMX_IMX50_IOMUXREG_H 35 36 /* register offset address */ 37 38 #define IOMUXC_GPR0 0x0000 39 #define IOMUXC_GPR1 0x0004 40 #define IOMUXC_GPR2 0x0008 41 #define IOMUXC_OBSERVE_MUX_0 0x000C 42 #define IOMUXC_OBSERVE_MUX_1 0x0010 43 #define IOMUXC_OBSERVE_MUX_2 0x0014 44 #define IOMUXC_OBSERVE_MUX_3 0x0018 45 #define IOMUXC_OBSERVE_MUX_4 0x001C 46 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 0x0020 47 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 0x0024 48 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 0x0028 49 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 0x002C 50 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 0x0030 51 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 0x0034 52 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 0x0038 53 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 0x003C 54 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL 0x0040 55 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA 0x0044 56 #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL 0x0048 57 #define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA 0x004C 58 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL 0x0050 59 #define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA 0x0054 60 #define IOMUXC_SW_MUX_CTL_PAD_PWM1 0x0058 61 #define IOMUXC_SW_MUX_CTL_PAD_PWM2 0x005C 62 #define IOMUXC_SW_MUX_CTL_PAD_OWIRE 0x0060 63 #define IOMUXC_SW_MUX_CTL_PAD_EPITO 0x0064 64 #define IOMUXC_SW_MUX_CTL_PAD_WDOG 0x0068 65 #define IOMUXC_SW_MUX_CTL_PAD_SSI_TXFS 0x006C 66 #define IOMUXC_SW_MUX_CTL_PAD_SSI_TXC 0x0070 67 #define IOMUXC_SW_MUX_CTL_PAD_SSI_TXD 0x0074 68 #define IOMUXC_SW_MUX_CTL_PAD_SSI_RXD 0x0078 69 #define IOMUXC_SW_MUX_CTL_PAD_SSI_RXF 0x007C 70 #define IOMUXC_SW_MUX_CTL_PAD_SSI_RXC 0x0080 71 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TXD 0x0084 72 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RXD 0x0088 73 #define IOMUXC_SW_MUX_CTL_PAD_UART1_CTS 0x008C 74 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RTS 0x0090 75 #define IOMUXC_SW_MUX_CTL_PAD_UART2_TXD 0x0094 76 #define IOMUXC_SW_MUX_CTL_PAD_UART2_RXD 0x0098 77 #define IOMUXC_SW_MUX_CTL_PAD_UART2_CTS 0x009C 78 #define IOMUXC_SW_MUX_CTL_PAD_UART2_RTS 0x00A0 79 #define IOMUXC_SW_MUX_CTL_PAD_UART3_TXD 0x00A4 80 #define IOMUXC_SW_MUX_CTL_PAD_UART3_RXD 0x00A8 81 #define IOMUXC_SW_MUX_CTL_PAD_UART4_TXD 0x00AC 82 #define IOMUXC_SW_MUX_CTL_PAD_UART4_RXD 0x00B0 83 #define IOMUXC_SW_MUX_CTL_PAD_CSPI_SCLK 0x00B4 84 #define IOMUXC_SW_MUX_CTL_PAD_CSPI_MOSI 0x00B8 85 #define IOMUXC_SW_MUX_CTL_PAD_CSPI_MISO 0x00BC 86 #define IOMUXC_SW_MUX_CTL_PAD_CSPI_SS0 0x00C0 87 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK 0x00C4 88 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI 0x00C8 89 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO 0x00CC 90 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0 0x00D0 91 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK 0x00D4 92 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI 0x00D8 93 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO 0x00DC 94 #define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0 0x00E0 95 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK 0x00E4 96 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD 0x00E8 97 #define IOMUXC_SW_MUX_CTL_PAD_SD1_D0 0x00EC 98 #define IOMUXC_SW_MUX_CTL_PAD_SD1_D1 0x00F0 99 #define IOMUXC_SW_MUX_CTL_PAD_SD1_D2 0x00F4 100 #define IOMUXC_SW_MUX_CTL_PAD_SD1_D3 0x00F8 101 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK 0x00FC 102 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD 0x0100 103 #define IOMUXC_SW_MUX_CTL_PAD_SD2_D0 0x0104 104 #define IOMUXC_SW_MUX_CTL_PAD_SD2_D1 0x0108 105 #define IOMUXC_SW_MUX_CTL_PAD_SD2_D2 0x010C 106 #define IOMUXC_SW_MUX_CTL_PAD_SD2_D3 0x0110 107 #define IOMUXC_SW_MUX_CTL_PAD_SD2_D4 0x0114 108 #define IOMUXC_SW_MUX_CTL_PAD_SD2_D5 0x0118 109 #define IOMUXC_SW_MUX_CTL_PAD_SD2_D6 0x011C 110 #define IOMUXC_SW_MUX_CTL_PAD_SD2_D7 0x0120 111 #define IOMUXC_SW_MUX_CTL_PAD_SD2_WP 0x0124 112 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CD 0x0128 113 #define IOMUXC_SW_MUX_CTL_PAD_DISP_D0 0x012C 114 #define IOMUXC_SW_MUX_CTL_PAD_DISP_D1 0x0130 115 #define IOMUXC_SW_MUX_CTL_PAD_DISP_D2 0x0134 116 #define IOMUXC_SW_MUX_CTL_PAD_DISP_D3 0x0138 117 #define IOMUXC_SW_MUX_CTL_PAD_DISP_D4 0x013C 118 #define IOMUXC_SW_MUX_CTL_PAD_DISP_D5 0x0140 119 #define IOMUXC_SW_MUX_CTL_PAD_DISP_D6 0x0144 120 #define IOMUXC_SW_MUX_CTL_PAD_DISP_D7 0x0148 121 #define IOMUXC_SW_MUX_CTL_PAD_DISP_WR 0x014C 122 #define IOMUXC_SW_MUX_CTL_PAD_DISP_RD 0x0150 123 #define IOMUXC_SW_MUX_CTL_PAD_DISP_RS 0x0154 124 #define IOMUXC_SW_MUX_CTL_PAD_DISP_CS 0x0158 125 #define IOMUXC_SW_MUX_CTL_PAD_DISP_BUSY 0x015C 126 #define IOMUXC_SW_MUX_CTL_PAD_DISP_RESET 0x0160 127 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD 0x0164 128 #define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK 0x0168 129 #define IOMUXC_SW_MUX_CTL_PAD_SD3_D0 0x016C 130 #define IOMUXC_SW_MUX_CTL_PAD_SD3_D1 0x0170 131 #define IOMUXC_SW_MUX_CTL_PAD_SD3_D2 0x0174 132 #define IOMUXC_SW_MUX_CTL_PAD_SD3_D3 0x0178 133 #define IOMUXC_SW_MUX_CTL_PAD_SD3_D4 0x017C 134 #define IOMUXC_SW_MUX_CTL_PAD_SD3_D5 0x0180 135 #define IOMUXC_SW_MUX_CTL_PAD_SD3_D6 0x0184 136 #define IOMUXC_SW_MUX_CTL_PAD_SD3_D7 0x0188 137 #define IOMUXC_SW_MUX_CTL_PAD_SD3_WP 0x018C 138 #define IOMUXC_SW_MUX_CTL_PAD_DISP_D8 0x0190 139 #define IOMUXC_SW_MUX_CTL_PAD_DISP_D9 0x0194 140 #define IOMUXC_SW_MUX_CTL_PAD_DISP_D10 0x0198 141 #define IOMUXC_SW_MUX_CTL_PAD_DISP_D11 0x019C 142 #define IOMUXC_SW_MUX_CTL_PAD_DISP_D12 0x01A0 143 #define IOMUXC_SW_MUX_CTL_PAD_DISP_D13 0x01A4 144 #define IOMUXC_SW_MUX_CTL_PAD_DISP_D14 0x01A8 145 #define IOMUXC_SW_MUX_CTL_PAD_DISP_D15 0x01AC 146 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_D0 0x01B0 147 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_D1 0x01B4 148 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_D2 0x01B8 149 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_D3 0x01BC 150 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_D4 0x01C0 151 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_D5 0x01C4 152 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_D6 0x01C8 153 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_D7 0x01CC 154 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_D8 0x01D0 155 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_D9 0x01D4 156 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_D10 0x01D8 157 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_D11 0x01DC 158 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_D12 0x01E0 159 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_D13 0x01E4 160 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_D14 0x01E8 161 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_D15 0x01EC 162 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK 0x01F0 163 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP 0x01F4 164 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE 0x01F8 165 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL 0x01FC 166 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK 0x0200 167 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOEZ 0x0204 168 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOED 0x0208 169 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE 0x020C 170 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE 0x0210 171 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLKN 0x0214 172 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR 0x0218 173 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWRCOM 0x021C 174 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWRSTAT 0x0220 175 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWRCTRL0 0x0224 176 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWRCTRL1 0x0228 177 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWRCTRL2 0x022C 178 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWRCTRL3 0x0230 179 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_VCOM0 0x0234 180 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_VCOM1 0x0238 181 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0 0x023C 182 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1 0x0240 183 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0 0x0244 184 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1 0x0248 185 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2 0x024C 186 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3 0x0250 187 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE4 0x0254 188 #define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE5 0x0258 189 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA0 0x025C 190 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA1 0x0260 191 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA2 0x0264 192 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA3 0x0268 193 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA4 0x026C 194 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA5 0x0270 195 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA6 0x0274 196 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA7 0x0278 197 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA8 0x027C 198 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA9 0x0280 199 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA10 0x0284 200 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA11 0x0288 201 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA12 0x028C 202 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA13 0x0290 203 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA14 0x0294 204 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA15 0x0298 205 #define IOMUXC_SW_MUX_CTL_PAD_EIM_CS2 0x029C 206 #define IOMUXC_SW_MUX_CTL_PAD_EIM_CS1 0x02A0 207 #define IOMUXC_SW_MUX_CTL_PAD_EIM_CS0 0x02A4 208 #define IOMUXC_SW_MUX_CTL_PAD_EIM_EB0 0x02A8 209 #define IOMUXC_SW_MUX_CTL_PAD_EIM_EB1 0x02AC 210 #define IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT 0x02B0 211 #define IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK 0x02B4 212 #define IOMUXC_SW_MUX_CTL_PAD_EIM_RDY 0x02B8 213 #define IOMUXC_SW_MUX_CTL_PAD_EIM_OE 0x02BC 214 #define IOMUXC_SW_MUX_CTL_PAD_EIM_RW 0x02C0 215 #define IOMUXC_SW_MUX_CTL_PAD_EIM_LBA 0x02C4 216 #define IOMUXC_SW_MUX_CTL_PAD_EIM_CRE 0x02C8 217 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 0x02CC 218 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 0x02D0 219 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 0x02D4 220 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 0x02D8 221 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 0x02DC 222 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 0x02E0 223 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 0x02E4 224 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 0x02E8 225 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL 0x02EC 226 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA 0x02F0 227 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL 0x02F4 228 #define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA 0x02F8 229 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL 0x02FC 230 #define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA 0x0300 231 #define IOMUXC_SW_PAD_CTL_PAD_PWM1 0x0304 232 #define IOMUXC_SW_PAD_CTL_PAD_PWM2 0x0308 233 #define IOMUXC_SW_PAD_CTL_PAD_OWIRE 0x030C 234 #define IOMUXC_SW_PAD_CTL_PAD_EPITO 0x0310 235 #define IOMUXC_SW_PAD_CTL_PAD_WDOG 0x0314 236 #define IOMUXC_SW_PAD_CTL_PAD_SSI_TXFS 0x0318 237 #define IOMUXC_SW_PAD_CTL_PAD_SSI_TXC 0x031C 238 #define IOMUXC_SW_PAD_CTL_PAD_SSI_TXD 0x0320 239 #define IOMUXC_SW_PAD_CTL_PAD_SSI_RXD 0x0324 240 #define IOMUXC_SW_PAD_CTL_PAD_SSI_RXFS 0x0328 241 #define IOMUXC_SW_PAD_CTL_PAD_SSI_RXC 0x032C 242 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TXD 0x0330 243 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RXD 0x0334 244 #define IOMUXC_SW_PAD_CTL_PAD_UART1_CTS 0x0338 245 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RTS 0x033C 246 #define IOMUXC_SW_PAD_CTL_PAD_UART2_TXD 0x0340 247 #define IOMUXC_SW_PAD_CTL_PAD_UART2_RXD 0x0344 248 #define IOMUXC_SW_PAD_CTL_PAD_UART2_CTS 0x0348 249 #define IOMUXC_SW_PAD_CTL_PAD_UART2_RTS 0x034C 250 #define IOMUXC_SW_PAD_CTL_PAD_UART3_TXD 0x0350 251 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RXD 0x0354 252 #define IOMUXC_SW_PAD_CTL_PAD_UART4_TXD 0x0358 253 #define IOMUXC_SW_PAD_CTL_PAD_UART4_RXD 0x035C 254 #define IOMUXC_SW_PAD_CTL_PAD_CSPI_SCLK 0x0360 255 #define IOMUXC_SW_PAD_CTL_PAD_CSPI_MOSI 0x0364 256 #define IOMUXC_SW_PAD_CTL_PAD_CSPI_MISO 0x0368 257 #define IOMUXC_SW_PAD_CTL_PAD_CSPI_SS0 0x036C 258 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK 0x0370 259 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI 0x0374 260 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO 0x0378 261 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0 0x037C 262 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK 0x0380 263 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI 0x0384 264 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO 0x0388 265 #define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0 0x038C 266 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK 0x0390 267 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD 0x0394 268 #define IOMUXC_SW_PAD_CTL_PAD_SD1_D0 0x0398 269 #define IOMUXC_SW_PAD_CTL_PAD_SD1_D1 0x039C 270 #define IOMUXC_SW_PAD_CTL_PAD_SD1_D2 0x03A0 271 #define IOMUXC_SW_PAD_CTL_PAD_SD1_D3 0x03A4 272 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK 0x03A8 273 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD 0x03AC 274 #define IOMUXC_SW_PAD_CTL_PAD_SD2_D0 0x03B0 275 #define IOMUXC_SW_PAD_CTL_PAD_SD2_D1 0x03B4 276 #define IOMUXC_SW_PAD_CTL_PAD_SD2_D2 0x03B8 277 #define IOMUXC_SW_PAD_CTL_PAD_SD2_D3 0x03BC 278 #define IOMUXC_SW_PAD_CTL_PAD_SD2_D4 0x03C0 279 #define IOMUXC_SW_PAD_CTL_PAD_SD2_D5 0x03C4 280 #define IOMUXC_SW_PAD_CTL_PAD_SD2_D6 0x03C8 281 #define IOMUXC_SW_PAD_CTL_PAD_SD2_D7 0x03CC 282 #define IOMUXC_SW_PAD_CTL_PAD_SD2_WP 0x03D0 283 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CD 0x03D4 284 #define IOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ 0x03D8 285 #define IOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ 0x03DC 286 #define IOMUXC_SW_PAD_CTL_PAD_POR_B 0x03E0 287 #define IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1 0x03E4 288 #define IOMUXC_SW_PAD_CTL_PAD_RESET_IN_B 0x03E8 289 #define IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0 0x03EC 290 #define IOMUXC_SW_PAD_CTL_PAD_TEST_MODE 0x03F0 291 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS 0x03F4 292 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD 0x03F8 293 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB 0x03FC 294 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI 0x0400 295 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK 0x0404 296 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO 0x0408 297 #define IOMUXC_SW_PAD_CTL_PAD_DISP_D0 0x040C 298 #define IOMUXC_SW_PAD_CTL_PAD_DISP_D1 0x0410 299 #define IOMUXC_SW_PAD_CTL_PAD_DISP_D2 0x0414 300 #define IOMUXC_SW_PAD_CTL_PAD_DISP_D3 0x0418 301 #define IOMUXC_SW_PAD_CTL_PAD_DISP_D4 0x041C 302 #define IOMUXC_SW_PAD_CTL_PAD_DISP_D5 0x0420 303 #define IOMUXC_SW_PAD_CTL_PAD_DISP_D6 0x0424 304 #define IOMUXC_SW_PAD_CTL_PAD_DISP_D7 0x0428 305 #define IOMUXC_SW_PAD_CTL_PAD_DISP_WR 0x042C 306 #define IOMUXC_SW_PAD_CTL_PAD_DISP_RD 0x0430 307 #define IOMUXC_SW_PAD_CTL_PAD_DISP_RS 0x0434 308 #define IOMUXC_SW_PAD_CTL_PAD_DISP_CS 0x0438 309 #define IOMUXC_SW_PAD_CTL_PAD_DISP_BUSY 0x043C 310 #define IOMUXC_SW_PAD_CTL_PAD_DISP_RESET 0x0440 311 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD 0x0444 312 #define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK 0x0448 313 #define IOMUXC_SW_PAD_CTL_PAD_SD3_D0 0x044C 314 #define IOMUXC_SW_PAD_CTL_PAD_SD3_D1 0x0450 315 #define IOMUXC_SW_PAD_CTL_PAD_SD3_D2 0x0454 316 #define IOMUXC_SW_PAD_CTL_PAD_SD3_D3 0x0458 317 #define IOMUXC_SW_PAD_CTL_PAD_SD3_D4 0x045C 318 #define IOMUXC_SW_PAD_CTL_PAD_SD3_D5 0x0460 319 #define IOMUXC_SW_PAD_CTL_PAD_SD3_D6 0x0464 320 #define IOMUXC_SW_PAD_CTL_PAD_SD3_D7 0x0468 321 #define IOMUXC_SW_PAD_CTL_PAD_SD3_WP 0x046C 322 #define IOMUXC_SW_PAD_CTL_PAD_DISP_D8 0x0470 323 #define IOMUXC_SW_PAD_CTL_PAD_DISP_D9 0x0474 324 #define IOMUXC_SW_PAD_CTL_PAD_DISP_D10 0x0478 325 #define IOMUXC_SW_PAD_CTL_PAD_DISP_D11 0x047C 326 #define IOMUXC_SW_PAD_CTL_PAD_DISP_D12 0x0480 327 #define IOMUXC_SW_PAD_CTL_PAD_DISP_D13 0x0484 328 #define IOMUXC_SW_PAD_CTL_PAD_DISP_D14 0x0488 329 #define IOMUXC_SW_PAD_CTL_PAD_DISP_D15 0x048C 330 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_OPEN 0x0490 331 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_OPENFB 0x0494 332 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 0x0498 333 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 0x049C 334 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE 0x04A0 335 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 0x04A4 336 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D16 0x04A8 337 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D17 0x04AC 338 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D18 0x04B0 339 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D19 0x04B4 340 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D20 0x04B8 341 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D21 0x04BC 342 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D22 0x04C0 343 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D23 0x04C4 344 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x04C8 345 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 0x04CC 346 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D0 0x04D0 347 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D1 0x04D4 348 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D2 0x04D8 349 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D3 0x04DC 350 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D4 0x04E0 351 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D5 0x04E4 352 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D6 0x04E8 353 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D7 0x04EC 354 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x04F0 355 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 0x04F4 356 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 0x04F8 357 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 0x04FC 358 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x0500 359 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D8 0x0504 360 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D9 0x0508 361 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D10 0x050C 362 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D11 0x0510 363 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D12 0x0514 364 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D13 0x0518 365 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D14 0x051C 366 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D15 0x0520 367 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 0x0524 368 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x0528 369 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D24 0x052C 370 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D25 0x0530 371 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D26 0x0534 372 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D27 0x0538 373 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D28 0x053C 374 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D29 0x0540 375 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D30 0x0544 376 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_D31 0x0548 377 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_D0 0x054C 378 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_D1 0x0550 379 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_D2 0x0554 380 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_D3 0x0558 381 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_D4 0x055C 382 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_D5 0x0560 383 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_D6 0x0564 384 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_D7 0x0568 385 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_D8 0x056C 386 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_D9 0x0570 387 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_D10 0x0574 388 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_D11 0x0578 389 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_D12 0x057C 390 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_D13 0x0580 391 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_D14 0x0584 392 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_D15 0x0588 393 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK 0x058C 394 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP 0x0590 395 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE 0x0594 396 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL 0x0598 397 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK 0x059C 398 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOEZ 0x05A0 399 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOED 0x05A4 400 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE 0x05A8 401 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE 0x05AC 402 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLKN 0x05B0 403 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR 0x05B4 404 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWRCOM 0x05B8 405 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWRSTAT 0x05BC 406 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWRCTRL0 0x05C0 407 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWRCTRL1 0x05C4 408 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWRCTRL2 0x05C8 409 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWRCTRL3 0x05CC 410 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_VCOM0 0x05D0 411 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_VCOM1 0x05D4 412 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0 0x05D8 413 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1 0x05DC 414 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0 0x05E0 415 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1 0x05E4 416 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2 0x05E8 417 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3 0x05EC 418 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE4 0x05F0 419 #define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE5 0x05F4 420 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DA0 0x05F8 421 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DA1 0x05FC 422 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DA2 0x0600 423 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DA3 0x0604 424 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DA4 0x0608 425 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DA5 0x060C 426 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DA6 0x0610 427 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DA7 0x0614 428 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DA8 0x0618 429 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DA9 0x061C 430 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DA10 0x0620 431 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DA11 0x0624 432 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DA12 0x0628 433 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DA13 0x062C 434 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DA14 0x0630 435 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DA15 0x0634 436 #define IOMUXC_SW_PAD_CTL_PAD_EIM_CS2 0x0638 437 #define IOMUXC_SW_PAD_CTL_PAD_EIM_CS1 0x063C 438 #define IOMUXC_SW_PAD_CTL_PAD_EIM_CS0 0x0640 439 #define IOMUXC_SW_PAD_CTL_PAD_EIM_EB0 0x0644 440 #define IOMUXC_SW_PAD_CTL_PAD_EIM_EB1 0x0648 441 #define IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT 0x064C 442 #define IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK 0x0650 443 #define IOMUXC_SW_PAD_CTL_PAD_EIM_RDY 0x0654 444 #define IOMUXC_SW_PAD_CTL_PAD_EIM_OE 0x0658 445 #define IOMUXC_SW_PAD_CTL_PAD_EIM_RW 0x065C 446 #define IOMUXC_SW_PAD_CTL_PAD_EIM_LBA 0x0660 447 #define IOMUXC_SW_PAD_CTL_PAD_EIM_CRE 0x0664 448 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x0668 449 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x066C 450 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x0670 451 #define IOMUXC_SW_PAD_CTL_GRP_EIM 0x0674 452 #define IOMUXC_SW_PAD_CTL_GRP_EPDC 0x0678 453 #define IOMUXC_SW_PAD_CTL_GRP_UART 0x067C 454 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x0680 455 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x0684 456 #define IOMUXC_SW_PAD_CTL_GRP_KEYPAD 0x0688 457 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x068C 458 #define IOMUXC_SW_PAD_CTL_GRP_SSI 0x0690 459 #define IOMUXC_SW_PAD_CTL_GRP_SD1 0x0694 460 #define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x0698 461 #define IOMUXC_SW_PAD_CTL_GRP_SD2 0x069C 462 #define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x06A0 463 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x06A4 464 #define IOMUXC_SW_PAD_CTL_GRP_B2DS 0x06A8 465 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x06AC 466 #define IOMUXC_SW_PAD_CTL_GRP_LCD 0x06B0 467 #define IOMUXC_SW_PAD_CTL_GRP_B3DS 0x06B4 468 #define IOMUXC_SW_PAD_CTL_GRP_MISC 0x06B8 469 #define IOMUXC_SW_PAD_CTL_GRP_SPI 0x06BC 470 #define IOMUXC_SW_PAD_CTL_GRP_NANDF 0x06C0 471 #define IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT 0x06C4 472 #define IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT 0x06C8 473 #define IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT 0x06CC 474 #define IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT 0x06D0 475 #define IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT 0x06D4 476 #define IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT 0x06D8 477 #define IOMUXC_CCM_PLL1_BYPASS_CLK_SELECT_INPUT 0x06DC 478 #define IOMUXC_CCM_PLL2_BYPASS_CLK_SELECT_INPUT 0x06E0 479 #define IOMUXC_CCM_PLL3_BYPASS_CLK_SELECT_INPUT 0x06E4 480 #define IOMUXC_CSPI_IPP_IND_DATAREADY_B_SELECT_INPUT 0x06E8 481 #define IOMUXC_CSPI_IPP_IND_SS1_B_SELECT_INPUT 0x06EC 482 #define IOMUXC_CSPI_IPP_IND_SS2_B_SELECT_INPUT 0x06F0 483 #define IOMUXC_CSPI_IPP_IND_SS3_B_SELECT_INPUT 0x06F4 484 #define IOMUXC_ELCDIF_LCDIF_BUSY_SELECT_INPUT 0x06F8 485 #define IOMUXC_ELCDIF_LCDIF_RXDATA_0_SELECT_INPUT 0x06FC 486 #define IOMUXC_ELCDIF_LCDIF_RXDATA_1_SELECT_INPUT 0x0700 487 #define IOMUXC_ELCDIF_LCDIF_RXDATA_2_SELECT_INPUT 0x0704 488 #define IOMUXC_ELCDIF_LCDIF_RXDATA_3_SELECT_INPUT 0x0708 489 #define IOMUXC_ELCDIF_LCDIF_RXDATA_4_SELECT_INPUT 0x070C 490 #define IOMUXC_ELCDIF_LCDIF_RXDATA_5_SELECT_INPUT 0x0710 491 #define IOMUXC_ELCDIF_LCDIF_RXDATA_6_SELECT_INPUT 0x0714 492 #define IOMUXC_ELCDIF_LCDIF_RXDATA_7_SELECT_INPUT 0x0718 493 #define IOMUXC_ELCDIF_LCDIF_RXDATA_8_SELECT_INPUT 0x071C 494 #define IOMUXC_C_ELCDIF_LCDIF_RXDATA_9_SELECT_INPUT 0x0720 495 #define IOMUXC_ELCDIF_LCDIF_RXDATA_10_SELECT_INPUT 0x0724 496 #define IOMUXC_ELCDIF_LCDIF_RXDATA_11_SELECT_INPUT 0x0728 497 #define IOMUXC_ELCDIF_LCDIF_RXDATA_12_SELECT_INPUT 0x072C 498 #define IOMUXC_ELCDIF_LCDIF_RXDATA_13_SELECT_INPUT 0x0730 499 #define IOMUXC_ELCDIF_LCDIF_RXDATA_14_SELECT_INPUT 0x0734 500 #define IOMUXC_ELCDIF_LCDIF_RXDATA_15_SELECT_INPUT 0x0738 501 #define IOMUXC_ELCDIF_VSYNC_I_SELECT_INPUT 0x073C 502 #define IOMUXC_ESDHC2_IPP_CARD_DET_SELECT_INPUT 0x0740 503 #define IOMUXC_ESDHC2_IPP_WP_ON_SELECT_INPUT 0x0744 504 #define IOMUXC_ESDHC4_IPP_CARD_CLK_IN_SELECT_INPUT 0x0748 505 #define IOMUXC_ESDHC4_IPP_CMD_IN_SELECT_INPUT 0x074C 506 #define IOMUXC_ESDHC4_IPP_DAT0_IN_SELECT_INPUT 0x0750 507 #define IOMUXC_XC_ESDHC4_IPP_DAT1_IN_SELECT_INPUT 0x0754 508 #define IOMUXC_ESDHC4_IPP_DAT2_IN_SELECT_INPUT 0x0758 509 #define IOMUXC_ESDHC4_IPP_DAT3_IN_SELECT_INPUT 0x075C 510 #define IOMUXC_ESDHC4_IPP_DAT4_IN_SELECT_INPUT 0x0760 511 #define IOMUXC_ESDHC4_IPP_DAT5_IN_SELECT_INPUT 0x0764 512 #define IOMUXC_ESDHC4_IPP_DAT6_IN_SELECT_INPUT 0x0768 513 #define IOMUXC_ESDHC4_IPP_DAT7_IN_SELECT_INPUT 0x076C 514 #define IOMUXC_FEC_FEC_COL_SELECT_INPUT 0x0770 515 #define IOMUXC_FEC_FEC_MDI_SELECT_INPUT 0x0774 516 #define IOMUXC_FEC_FEC_RDATA_0_SELECT_INPUT 0x0778 517 #define IOMUXC_FEC_FEC_RDATA_1_SELECT_INPUT 0x077C 518 #define IOMUXC_FEC_FEC_RX_CLK_SELECT_INPUT 0x0780 519 #define IOMUXC_FEC_FEC_RX_DV_SELECT_INPUT 0x0784 520 #define IOMUXC_FEC_FEC_RX_ER_SELECT_INPUT 0x0788 521 #define IOMUXC_FEC_FEC_TX_CLK_SELECT_INPUT 0x078C 522 #define IOMUXC_KPP_IPP_IND_COL_4_SELECT_INPUT 0x0790 523 #define IOMUXC_KPP_IPP_IND_COL_5_SELECT_INPUT 0x0794 524 #define IOMUXC_KPP_IPP_IND_COL_6_SELECT_INPUT 0x0798 525 #define IOMUXC_KPP_IPP_IND_COL_7_SELECT_INPUT 0x079C 526 #define IOMUXC_KPP_IPP_IND_ROW_4_SELECT_INPUT 0x07A0 527 #define IOMUXC_KPP_IPP_IND_ROW_5_SELECT_INPUT 0x07A4 528 #define IOMUXC_KPP_IPP_IND_ROW_6_SELECT_INPUT 0x07A8 529 #define IOMUXC_KPP_IPP_IND_ROW_7_SELECT_INPUT 0x07AC 530 #define IOMUXC_RAWNAND_U_GPMI_INPUT_GPMI_DQS_IN_SELECT_INPUT 0x07B0 531 #define IOMUXC_RAWNAND_U_GPMI_INPUT_GPMI_RDY0_SELECT_INPUT 0x07B4 532 #define IOMUXC_SDMA_EVENTS_14_SELECT_INPUT 0x07B8 533 #define IOMUXC_SDMA_EVENTS_15_SELECT_INPUT 0x07BC 534 #define IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT 0x07C0 535 #define IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT 0x07C4 536 #define IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT 0x07C8 537 #define IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT 0x07CC 538 #define IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT 0x07D0 539 #define IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT 0x07D4 540 #define IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT 0x07D8 541 #define IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT 0x07DC 542 #define IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT 0x07E0 543 #define IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT 0x07E4 544 #define IOMUXC_USBOH1_IPP_IND_OTG_OC_SELECT_INPUT 0x07E8 545 #define IOMUXC_WEIMV2_IPP_IND_READ_DATA_0_SELECT_INPUT 0x07EC 546 #define IOMUXC_WEIMV2_IPP_IND_READ_DATA_1_SELECT_INPUT 0x07F0 547 #define IOMUXC_WEIMV2_IPP_IND_READ_DATA_2_SELECT_INPUT 0x07F4 548 #define IOMUXC_WEIMV2_IPP_IND_READ_DATA_3_SELECT_INPUT 0x07F8 549 #define IOMUXC_WEIMV2_IPP_IND_READ_DATA_4_SELECT_INPUT 0x07FC 550 #define IOMUXC_WEIMV2_IPP_IND_READ_DATA_5_SELECT_INPUT 0x0800 551 #define IOMUXC_WEIMV2_IPP_IND_READ_DATA_6_SELECT_INPUT 0x0804 552 #define IOMUXC_WEIMV2_IPP_IND_READ_DATA_7_SELECT_INPUT 0x0808 553 #define IOMUXC_WEIMV2_IPP_IND_READ_DATA_8_SELECT_INPUT 0x080C 554 #define IOMUXC_WEIMV2_IPP_IND_READ_DATA_9_SELECT_INPUT 0x0810 555 #define IOMUXC_WEIMV2_IPP_IND_READ_DATA_10_SELECT_INPUT 0x0814 556 #define IOMUXC_WEIMV2_IPP_IND_READ_DATA_11_SELECT_INPUT 0x0818 557 #define IOMUXC_WEIMV2_IPP_IND_READ_DATA_12_SELECT_INPUT 0x081C 558 #define IOMUXC_WEIMV2_IPP_IND_READ_DATA_13_SELECT_INPUT 0x0820 559 #define IOMUXC_WEIMV2_IPP_IND_READ_DATA_14_SELECT_INPUT 0x0824 560 #define IOMUXC_WEIMV2_IPP_IND_READ_DATA_15_SELECT_INPUT 0x0828 561 562 #endif /* _ARM_IMX_IMX50_IOMUXREG_H */ 563 564
Indexes created Sat Oct 11 19:10:01 GMT 2025