imx51_ccm.c revision 1.1
1 /* $NetBSD: imx51_ccm.c,v 1.1 2012/04/17 09:33:31 bsh Exp $ */ 2 /* 3 * Copyright (c) 2010, 2011, 2012 Genetec Corporation. All rights reserved. 4 * Written by Hashimoto Kenichi for Genetec Corporation. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * Clock Controller Module (CCM) 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: imx51_ccm.c,v 1.1 2012/04/17 09:33:31 bsh Exp $"); 34 35 #include <sys/types.h> 36 #include <sys/time.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/param.h> 40 41 #include <machine/cpu.h> 42 43 #include <arm/imx/imx51_ccmvar.h> 44 #include <arm/imx/imx51_ccmreg.h> 45 #include <arm/imx/imx51_dpllreg.h> 46 47 #include <arm/imx/imx51var.h> 48 #include <arm/imx/imx51reg.h> 49 50 #include "opt_imx51clk.h" 51 #include "locators.h" 52 53 //#define IMXCCMDEBUG 54 55 #ifndef IMX51_OSC_FREQ 56 #define IMX51_OSC_FREQ (24 * 1000 * 1000) /* 24MHz */ 57 #endif 58 59 struct imxccm_softc { 60 device_t sc_dev; 61 bus_space_tag_t sc_iot; 62 bus_space_handle_t sc_ioh; 63 64 struct { 65 bus_space_handle_t pll_ioh; 66 u_int pll_freq; 67 } sc_pll[IMX51_N_DPLLS]; 68 }; 69 70 struct imxccm_softc *ccm_softc; 71 72 static uint64_t imx51_get_pll_freq(u_int); 73 74 static int imxccm_match(device_t, cfdata_t, void *); 75 static void imxccm_attach(device_t, device_t, void *); 76 77 CFATTACH_DECL_NEW(imxccm, sizeof(struct imxccm_softc), 78 imxccm_match, imxccm_attach, NULL, NULL); 79 80 static int 81 imxccm_match(device_t parent, cfdata_t cfdata, void *aux) 82 { 83 struct axi_attach_args *aa = aux; 84 85 if (aa->aa_addr == CCMC_BASE) 86 return 1; 87 88 return 0; 89 } 90 91 static void 92 imxccm_attach(device_t parent, device_t self, void *aux) 93 { 94 struct axi_attach_args *aa = aux; 95 bus_space_tag_t iot = aa->aa_iot; 96 int i; 97 98 ccm_softc = device_private(self); 99 ccm_softc->sc_dev = self; 100 ccm_softc->sc_iot = iot; 101 102 if (bus_space_map(iot, aa->aa_addr, CCMC_SIZE, 0, 103 &ccm_softc->sc_ioh)) { 104 aprint_error(": can't map\n"); 105 return; 106 } 107 108 for (i=1; i <= IMX51_N_DPLLS; ++i) { 109 if (bus_space_map(iot, DPLL_BASE(i), DPLL_SIZE, 0, 110 &ccm_softc->sc_pll[i-1].pll_ioh)) { 111 aprint_error(": can't map\n"); 112 return; 113 } 114 } 115 116 aprint_normal(": Clock control module\n"); 117 aprint_naive("\n"); 118 119 imx51_get_pll_freq(1); 120 imx51_get_pll_freq(2); 121 imx51_get_pll_freq(3); 122 123 124 aprint_verbose_dev(self, "CPU clock=%d, UART clock=%d\n", 125 imx51_get_clock(IMX51CLK_ARM_ROOT), 126 imx51_get_clock(IMX51CLK_UART_CLK_ROOT)); 127 aprint_verbose_dev(self, 128 "mainbus clock=%d, ahb clock=%d ipg clock=%d perclk=%d\n", 129 imx51_get_clock(IMX51CLK_MAIN_BUS_CLK), 130 imx51_get_clock(IMX51CLK_AHB_CLK_ROOT), 131 imx51_get_clock(IMX51CLK_IPG_CLK_ROOT), 132 imx51_get_clock(IMX51CLK_PERCLK_ROOT)); 133 } 134 135 136 u_int 137 imx51_get_clock(enum imx51_clock clk) 138 { 139 bus_space_tag_t iot = ccm_softc->sc_iot; 140 bus_space_handle_t ioh = ccm_softc->sc_ioh; 141 142 u_int freq; 143 u_int sel; 144 uint32_t cacrr; /* ARM clock root register */ 145 uint32_t ccsr; 146 uint32_t cscdr1; 147 uint32_t cscmr1; 148 uint32_t cbcdr; 149 uint32_t cbcmr; 150 uint32_t cdcr; 151 152 switch (clk) { 153 case IMX51CLK_PLL1: 154 case IMX51CLK_PLL2: 155 case IMX51CLK_PLL3: 156 return ccm_softc->sc_pll[clk-IMX51CLK_PLL1].pll_freq; 157 case IMX51CLK_PLL1SW: 158 ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR); 159 if ((ccsr & CCSR_PLL1_SW_CLK_SEL) == 0) 160 return ccm_softc->sc_pll[1-1].pll_freq; 161 /* step clock */ 162 /* FALLTHROUGH */ 163 case IMX51CLK_PLL1STEP: 164 ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR); 165 switch ((ccsr & CCSR_STEP_SEL_MASK) >> CCSR_STEP_SEL_SHIFT) { 166 case 0: 167 return imx51_get_clock(IMX51CLK_LP_APM); 168 case 1: 169 return 0; /* XXX PLL bypass clock */ 170 case 2: 171 return ccm_softc->sc_pll[2-1].pll_freq / 172 (1 + ((ccsr & CCSR_PLL2_DIV_PODF_MASK) >> 173 CCSR_PLL2_DIV_PODF_SHIFT)); 174 case 3: 175 return ccm_softc->sc_pll[3-1].pll_freq / 176 (1 + ((ccsr & CCSR_PLL3_DIV_PODF_MASK) >> 177 CCSR_PLL3_DIV_PODF_SHIFT)); 178 } 179 /*NOTREACHED*/ 180 case IMX51CLK_PLL2SW: 181 ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR); 182 if ((ccsr & CCSR_PLL2_SW_CLK_SEL) == 0) 183 return imx51_get_clock(IMX51CLK_PLL2); 184 return 0; /* XXX PLL2 bypass clk */ 185 case IMX51CLK_PLL3SW: 186 ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR); 187 if ((ccsr & CCSR_PLL3_SW_CLK_SEL) == 0) 188 return imx51_get_clock(IMX51CLK_PLL3); 189 return 0; /* XXX PLL3 bypass clk */ 190 191 case IMX51CLK_LP_APM: 192 ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR); 193 return (ccsr & CCSR_LP_APM) ? 194 imx51_get_clock(IMX51CLK_FPM) : IMX51_OSC_FREQ; 195 196 case IMX51CLK_ARM_ROOT: 197 freq = imx51_get_clock(IMX51CLK_PLL1SW); 198 cacrr = bus_space_read_4(iot, ioh, CCMC_CACRR); 199 return freq / (cacrr + 1); 200 201 /* ... */ 202 case IMX51CLK_MAIN_BUS_CLK_SRC: 203 cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR); 204 if ((cbcdr & CBCDR_PERIPH_CLK_SEL) == 0) 205 freq = imx51_get_clock(IMX51CLK_PLL2SW); 206 else { 207 freq = 0; 208 cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR); 209 switch ((cbcmr & CBCMR_PERIPH_APM_SEL_MASK) >> 210 CBCMR_PERIPH_APM_SEL_SHIFT) { 211 case 0: 212 freq = imx51_get_clock(IMX51CLK_PLL1SW); 213 break; 214 case 1: 215 freq = imx51_get_clock(IMX51CLK_PLL3SW); 216 break; 217 case 2: 218 freq = imx51_get_clock(IMX51CLK_LP_APM); 219 break; 220 case 3: 221 /* XXX: error */ 222 break; 223 } 224 } 225 return freq; 226 case IMX51CLK_MAIN_BUS_CLK: 227 freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC); 228 cdcr = bus_space_read_4(iot, ioh, CCMC_CDCR); 229 return freq / (cdcr & CDCR_PERIPH_CLK_DVFS_PODF_MASK) >> 230 CDCR_PERIPH_CLK_DVFS_PODF_SHIFT; 231 case IMX51CLK_AHB_CLK_ROOT: 232 freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK); 233 cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR); 234 return freq / (1 + ((cbcdr & CBCDR_AHB_PODF_MASK) >> 235 CBCDR_AHB_PODF_SHIFT)); 236 case IMX51CLK_IPG_CLK_ROOT: 237 freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT); 238 cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR); 239 return freq / (1 + ((cbcdr & CBCDR_IPG_PODF_MASK) >> 240 CBCDR_IPG_PODF_SHIFT)); 241 242 case IMX51CLK_PERCLK_ROOT: 243 cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR); 244 if (cbcmr & CBCMR_PERCLK_IPG_SEL) 245 return imx51_get_clock(IMX51CLK_IPG_CLK_ROOT); 246 if (cbcmr & CBCMR_PERCLK_LP_APM_SEL) 247 freq = imx51_get_clock(IMX51CLK_LP_APM); 248 else 249 freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC); 250 cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR); 251 252 #ifdef IMXCCMDEBUG 253 printf("cbcmr=%x cbcdr=%x\n", cbcmr, cbcdr); 254 #endif 255 256 freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED1_MASK) >> 257 CBCDR_PERCLK_PRED1_SHIFT); 258 freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED2_MASK) >> 259 CBCDR_PERCLK_PRED2_SHIFT); 260 freq /= 1 + ((cbcdr & CBCDR_PERCLK_PODF_MASK) >> 261 CBCDR_PERCLK_PODF_SHIFT); 262 return freq; 263 case IMX51CLK_UART_CLK_ROOT: 264 cscdr1 = bus_space_read_4(iot, ioh, CCMC_CSCDR1); 265 cscmr1 = bus_space_read_4(iot, ioh, CCMC_CSCMR1); 266 267 #ifdef IMXCCMDEBUG 268 printf("cscdr1=%x cscmr1=%x\n", cscdr1, cscmr1); 269 #endif 270 271 sel = (cscmr1 & CSCMR1_UART_CLK_SEL_MASK) >> 272 CSCMR1_UART_CLK_SEL_SHIFT; 273 274 freq = 0; /* shut up GCC */ 275 switch (sel) { 276 case 0: 277 case 1: 278 case 2: 279 freq = imx51_get_clock(IMX51CLK_PLL1SW + sel); 280 break; 281 case 3: 282 freq = imx51_get_clock(IMX51CLK_LP_APM); 283 break; 284 } 285 286 return freq / (1 + ((cscdr1 & CSCDR1_UART_CLK_PRED_MASK) >> 287 CSCDR1_UART_CLK_PRED_SHIFT)) / 288 (1 + ((cscdr1 & CSCDR1_UART_CLK_PODF_MASK) >> 289 CSCDR1_UART_CLK_PODF_SHIFT)); 290 case IMX51CLK_IPU_HSP_CLK_ROOT: 291 freq = 0; 292 cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR); 293 switch ((cbcmr & CBCMR_IPU_HSP_CLK_SEL_MASK) >> 294 CBCMR_IPU_HSP_CLK_SEL_SHIFT) { 295 case 0: 296 freq = imx51_get_clock(IMX51CLK_ARM_AXI_A_CLK); 297 break; 298 case 1: 299 freq = imx51_get_clock(IMX51CLK_ARM_AXI_B_CLK); 300 break; 301 case 2: 302 freq = imx51_get_clock( 303 IMX51CLK_EMI_SLOW_CLK_ROOT); 304 break; 305 case 3: 306 freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT); 307 break; 308 } 309 return freq; 310 default: 311 aprint_error_dev(ccm_softc->sc_dev, 312 "clock %d: not supported yet\n", clk); 313 return 0; 314 } 315 } 316 317 318 static uint64_t 319 imx51_get_pll_freq(u_int pll_no) 320 { 321 uint32_t dp_ctrl; 322 uint32_t dp_op; 323 uint32_t dp_mfd; 324 uint32_t dp_mfn; 325 uint32_t mfi; 326 int32_t mfn; 327 uint32_t mfd; 328 uint32_t pdf; 329 uint32_t ccr; 330 uint64_t freq = 0; 331 u_int ref = 0; 332 bus_space_tag_t iot = ccm_softc->sc_iot; 333 bus_space_handle_t ioh = ccm_softc->sc_pll[pll_no-1].pll_ioh; 334 335 KASSERT(1 <= pll_no && pll_no <= IMX51_N_DPLLS); 336 337 dp_ctrl = bus_space_read_4(iot, ioh, DPLL_DP_CTL); 338 339 if (dp_ctrl & DP_CTL_HFSM) { 340 dp_op = bus_space_read_4(iot, ioh, DPLL_DP_HFS_OP); 341 dp_mfd = bus_space_read_4(iot, ioh, DPLL_DP_HFS_MFD); 342 dp_mfn = bus_space_read_4(iot, ioh, DPLL_DP_HFS_MFN); 343 } else { 344 dp_op = bus_space_read_4(iot, ioh, DPLL_DP_OP); 345 dp_mfd = bus_space_read_4(iot, ioh, DPLL_DP_MFD); 346 dp_mfn = bus_space_read_4(iot, ioh, DPLL_DP_MFN); 347 } 348 349 pdf = dp_op & DP_OP_PDF_MASK; 350 mfi = max(5, (dp_op & DP_OP_MFI_MASK) >> DP_OP_MFI_SHIFT); 351 mfd = dp_mfd; 352 if (dp_mfn & __BIT(26)) 353 /* 27bit signed value */ 354 mfn = (int32_t)(__BITS(31,27) | dp_mfn); 355 else 356 mfn = dp_mfn; 357 358 switch (dp_ctrl & DP_CTL_REF_CLK_SEL_MASK) { 359 case DP_CTL_REF_CLK_SEL_COSC: 360 /* Internal Oscillator */ 361 ref = IMX51_OSC_FREQ; 362 break; 363 case DP_CTL_REF_CLK_SEL_FPM: 364 ccr = bus_space_read_4(iot, ccm_softc->sc_ioh, CCMC_CCR); 365 if (ccr & CCR_FPM_MULT) 366 ref = IMX51_CKIL_FREQ * 1024; 367 else 368 ref = IMX51_CKIL_FREQ * 512; 369 break; 370 default: 371 ref = 0; 372 } 373 374 375 if (dp_ctrl & DP_CTL_REF_CLK_DIV) 376 ref /= 2; 377 378 #if 0 379 if (dp_ctrl & DP_CTL_DPDCK0_2_EN) 380 ref *= 2; 381 382 ref /= (pdf + 1); 383 freq = ref * mfn; 384 freq /= (mfd + 1); 385 freq = (ref * mfi) + freq; 386 #endif 387 388 ref *= 4; 389 freq = (int64_t)ref * mfi + (int64_t)ref * mfn / (mfd + 1); 390 freq /= pdf + 1; 391 392 if (!(dp_ctrl & DP_CTL_DPDCK0_2_EN)) 393 freq /= 2; 394 395 396 #ifdef IMXCCMDEBUG 397 printf("dp_ctl: %08x ", dp_ctrl); 398 printf("pdf: %3d ", pdf); 399 printf("mfi: %3d ", mfi); 400 printf("mfd: %3d ", mfd); 401 printf("mfn: %3d ", mfn); 402 printf("pll: %lld\n", freq); 403 #endif 404 405 ccm_softc->sc_pll[pll_no-1].pll_freq = freq; 406 407 return freq; 408 } 409 410 void 411 imx51_clk_gating(int clk_src, int mode) 412 { 413 bus_space_tag_t iot = ccm_softc->sc_iot; 414 bus_space_handle_t ioh = ccm_softc->sc_ioh; 415 uint32_t group = CCMR_CCGR_MODULE(clk_src); 416 uint32_t field = clk_src % CCMR_CCGR_NSOURCE; 417 uint32_t reg; 418 uint32_t bit; 419 420 bit = (mode << field * 2); 421 reg = bus_space_read_4(iot, ioh, CCMC_CCGR(group)); 422 reg &= ~(0x03 << field * 2); 423 reg |= bit; 424 bus_space_write_4(iot, ioh, CCMC_CCGR(group), reg); 425 } 426
Indexes created Wed Oct 15 16:09:53 GMT 2025