imx51_ccm.c revision 1.1.4.3
1 /* $NetBSD: imx51_ccm.c,v 1.1.4.3 2012/10/30 17:19:03 yamt Exp $ */ 2 /* 3 * Copyright (c) 2010, 2011, 2012 Genetec Corporation. All rights reserved. 4 * Written by Hashimoto Kenichi for Genetec Corporation. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * Clock Controller Module (CCM) 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: imx51_ccm.c,v 1.1.4.3 2012/10/30 17:19:03 yamt Exp $"); 34 35 #include <sys/types.h> 36 #include <sys/time.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/param.h> 40 41 #include <machine/cpu.h> 42 43 #include <arm/imx/imx51_ccmvar.h> 44 #include <arm/imx/imx51_ccmreg.h> 45 #include <arm/imx/imx51_dpllreg.h> 46 47 #include <arm/imx/imx51var.h> 48 #include <arm/imx/imx51reg.h> 49 50 #include "opt_imx51clk.h" 51 #include "locators.h" 52 53 //#define IMXCCMDEBUG 54 55 #ifndef IMX51_OSC_FREQ 56 #define IMX51_OSC_FREQ (24 * 1000 * 1000) /* 24MHz */ 57 #endif 58 59 struct imxccm_softc { 60 device_t sc_dev; 61 bus_space_tag_t sc_iot; 62 bus_space_handle_t sc_ioh; 63 64 struct { 65 bus_space_handle_t pll_ioh; 66 u_int pll_freq; 67 } sc_pll[IMX51_N_DPLLS]; 68 }; 69 70 struct imxccm_softc *ccm_softc; 71 72 static uint64_t imx51_get_pll_freq(u_int); 73 74 static int imxccm_match(device_t, cfdata_t, void *); 75 static void imxccm_attach(device_t, device_t, void *); 76 77 CFATTACH_DECL_NEW(imxccm, sizeof(struct imxccm_softc), 78 imxccm_match, imxccm_attach, NULL, NULL); 79 80 static int 81 imxccm_match(device_t parent, cfdata_t cfdata, void *aux) 82 { 83 struct axi_attach_args *aa = aux; 84 85 if (ccm_softc != NULL) 86 return 0; 87 88 if (aa->aa_addr == CCMC_BASE) 89 return 1; 90 91 return 0; 92 } 93 94 static void 95 imxccm_attach(device_t parent, device_t self, void *aux) 96 { 97 struct imxccm_softc * const sc = device_private(self); 98 struct axi_attach_args *aa = aux; 99 bus_space_tag_t iot = aa->aa_iot; 100 101 ccm_softc = sc; 102 sc->sc_dev = self; 103 sc->sc_iot = iot; 104 105 if (bus_space_map(iot, aa->aa_addr, CCMC_SIZE, 0, &sc->sc_ioh)) { 106 aprint_error(": can't map registers\n"); 107 return; 108 } 109 110 for (u_int i=1; i <= IMX51_N_DPLLS; ++i) { 111 if (bus_space_map(iot, DPLL_BASE(i), DPLL_SIZE, 0, 112 &sc->sc_pll[i-1].pll_ioh)) { 113 aprint_error(": can't map pll registers\n"); 114 return; 115 } 116 } 117 118 aprint_normal(": Clock control module\n"); 119 aprint_naive("\n"); 120 121 imx51_get_pll_freq(1); 122 imx51_get_pll_freq(2); 123 imx51_get_pll_freq(3); 124 125 126 aprint_verbose_dev(self, "CPU clock=%d, UART clock=%d\n", 127 imx51_get_clock(IMX51CLK_ARM_ROOT), 128 imx51_get_clock(IMX51CLK_UART_CLK_ROOT)); 129 aprint_verbose_dev(self, 130 "mainbus clock=%d, ahb clock=%d ipg clock=%d perclk=%d\n", 131 imx51_get_clock(IMX51CLK_MAIN_BUS_CLK), 132 imx51_get_clock(IMX51CLK_AHB_CLK_ROOT), 133 imx51_get_clock(IMX51CLK_IPG_CLK_ROOT), 134 imx51_get_clock(IMX51CLK_PERCLK_ROOT)); 135 } 136 137 138 u_int 139 imx51_get_clock(enum imx51_clock clk) 140 { 141 bus_space_tag_t iot = ccm_softc->sc_iot; 142 bus_space_handle_t ioh = ccm_softc->sc_ioh; 143 144 u_int freq = 0; 145 u_int sel; 146 uint32_t cacrr; /* ARM clock root register */ 147 uint32_t ccsr; 148 uint32_t cscdr1; 149 uint32_t cscmr1; 150 uint32_t cbcdr; 151 uint32_t cbcmr; 152 uint32_t cdcr; 153 154 switch (clk) { 155 case IMX51CLK_PLL1: 156 case IMX51CLK_PLL2: 157 case IMX51CLK_PLL3: 158 return ccm_softc->sc_pll[clk - IMX51CLK_PLL1].pll_freq; 159 case IMX51CLK_PLL1SW: 160 ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR); 161 if ((ccsr & CCSR_PLL1_SW_CLK_SEL) == 0) 162 return ccm_softc->sc_pll[1-1].pll_freq; 163 /* step clock */ 164 /* FALLTHROUGH */ 165 case IMX51CLK_PLL1STEP: 166 ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR); 167 switch (__SHIFTOUT(ccsr, CCSR_STEP_SEL_MASK)) { 168 case 0: 169 return imx51_get_clock(IMX51CLK_LP_APM); 170 case 1: 171 return 0; /* XXX PLL bypass clock */ 172 case 2: 173 return ccm_softc->sc_pll[2-1].pll_freq / 174 (1 + __SHIFTOUT(ccsr, CCSR_PLL2_DIV_PODF_MASK)); 175 case 3: 176 return ccm_softc->sc_pll[3-1].pll_freq / 177 (1 + __SHIFTOUT(ccsr, CCSR_PLL3_DIV_PODF_MASK)); 178 } 179 /*NOTREACHED*/ 180 case IMX51CLK_PLL2SW: 181 ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR); 182 if ((ccsr & CCSR_PLL2_SW_CLK_SEL) == 0) 183 return imx51_get_clock(IMX51CLK_PLL2); 184 return 0; /* XXX PLL2 bypass clk */ 185 case IMX51CLK_PLL3SW: 186 ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR); 187 if ((ccsr & CCSR_PLL3_SW_CLK_SEL) == 0) 188 return imx51_get_clock(IMX51CLK_PLL3); 189 return 0; /* XXX PLL3 bypass clk */ 190 191 case IMX51CLK_LP_APM: 192 ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR); 193 return (ccsr & CCSR_LP_APM) ? 194 imx51_get_clock(IMX51CLK_FPM) : IMX51_OSC_FREQ; 195 196 case IMX51CLK_ARM_ROOT: 197 freq = imx51_get_clock(IMX51CLK_PLL1SW); 198 cacrr = bus_space_read_4(iot, ioh, CCMC_CACRR); 199 return freq / (cacrr + 1); 200 201 /* ... */ 202 case IMX51CLK_MAIN_BUS_CLK_SRC: 203 cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR); 204 if ((cbcdr & CBCDR_PERIPH_CLK_SEL) == 0) 205 freq = imx51_get_clock(IMX51CLK_PLL2SW); 206 else { 207 cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR); 208 switch (__SHIFTOUT(cbcmr, CBCMR_PERIPH_APM_SEL_MASK)) { 209 case 0: 210 freq = imx51_get_clock(IMX51CLK_PLL1SW); 211 break; 212 case 1: 213 freq = imx51_get_clock(IMX51CLK_PLL3SW); 214 break; 215 case 2: 216 freq = imx51_get_clock(IMX51CLK_LP_APM); 217 break; 218 case 3: 219 /* XXX: error */ 220 break; 221 } 222 } 223 return freq; 224 case IMX51CLK_MAIN_BUS_CLK: 225 freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC); 226 cdcr = bus_space_read_4(iot, ioh, CCMC_CDCR); 227 return freq / __SHIFTOUT(cdcr, CDCR_PERIPH_CLK_DVFS_PODF_MASK); 228 case IMX51CLK_AHB_CLK_ROOT: 229 freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK); 230 cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR); 231 return freq / (1 + __SHIFTOUT(cbcdr, CBCDR_AHB_PODF_MASK)); 232 case IMX51CLK_IPG_CLK_ROOT: 233 freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT); 234 cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR); 235 return freq / (1 + __SHIFTOUT(cbcdr, CBCDR_IPG_PODF_MASK)); 236 case IMX51CLK_PERCLK_ROOT: 237 cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR); 238 if (cbcmr & CBCMR_PERCLK_IPG_SEL) 239 return imx51_get_clock(IMX51CLK_IPG_CLK_ROOT); 240 if (cbcmr & CBCMR_PERCLK_LP_APM_SEL) 241 freq = imx51_get_clock(IMX51CLK_LP_APM); 242 else 243 freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC); 244 245 cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR); 246 247 #ifdef IMXCCMDEBUG 248 printf("cbcmr=%x cbcdr=%x\n", cbcmr, cbcdr); 249 #endif 250 251 freq /= 1 + __SHIFTOUT(cbcdr, CBCDR_PERCLK_PRED1_MASK); 252 freq /= 1 + __SHIFTOUT(cbcdr, CBCDR_PERCLK_PRED2_MASK); 253 freq /= 1 + __SHIFTOUT(cbcdr, CBCDR_PERCLK_PODF_MASK); 254 return freq; 255 case IMX51CLK_UART_CLK_ROOT: 256 cscdr1 = bus_space_read_4(iot, ioh, CCMC_CSCDR1); 257 cscmr1 = bus_space_read_4(iot, ioh, CCMC_CSCMR1); 258 259 #ifdef IMXCCMDEBUG 260 printf("cscdr1=%x cscmr1=%x\n", cscdr1, cscmr1); 261 #endif 262 263 sel = __SHIFTOUT(cscmr1, CSCMR1_UART_CLK_SEL_MASK); 264 265 switch (sel) { 266 case 0: 267 case 1: 268 case 2: 269 freq = imx51_get_clock(IMX51CLK_PLL1SW + sel); 270 break; 271 case 3: 272 freq = imx51_get_clock(IMX51CLK_LP_APM); 273 break; 274 } 275 276 return freq / (1 + __SHIFTOUT(cscdr1, CSCDR1_UART_CLK_PRED_MASK)) / 277 (1 + __SHIFTOUT(cscdr1, CSCDR1_UART_CLK_PODF_MASK)); 278 case IMX51CLK_IPU_HSP_CLK_ROOT: 279 cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR); 280 switch (__SHIFTOUT(cbcmr, CBCMR_IPU_HSP_CLK_SEL_MASK)) { 281 case 0: 282 freq = imx51_get_clock(IMX51CLK_ARM_AXI_A_CLK); 283 break; 284 case 1: 285 freq = imx51_get_clock(IMX51CLK_ARM_AXI_B_CLK); 286 break; 287 case 2: 288 freq = imx51_get_clock( 289 IMX51CLK_EMI_SLOW_CLK_ROOT); 290 break; 291 case 3: 292 freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT); 293 break; 294 } 295 return freq; 296 default: 297 aprint_error_dev(ccm_softc->sc_dev, 298 "clock %d: not supported yet\n", clk); 299 return 0; 300 } 301 } 302 303 304 static uint64_t 305 imx51_get_pll_freq(u_int pll_no) 306 { 307 uint32_t dp_ctrl; 308 uint32_t dp_op; 309 uint32_t dp_mfd; 310 uint32_t dp_mfn; 311 uint32_t mfi; 312 int32_t mfn; 313 uint32_t mfd; 314 uint32_t pdf; 315 uint32_t ccr; 316 uint64_t freq = 0; 317 u_int ref = 0; 318 bus_space_tag_t iot = ccm_softc->sc_iot; 319 bus_space_handle_t ioh = ccm_softc->sc_pll[pll_no-1].pll_ioh; 320 321 KASSERT(1 <= pll_no && pll_no <= IMX51_N_DPLLS); 322 323 dp_ctrl = bus_space_read_4(iot, ioh, DPLL_DP_CTL); 324 325 if (dp_ctrl & DP_CTL_HFSM) { 326 dp_op = bus_space_read_4(iot, ioh, DPLL_DP_HFS_OP); 327 dp_mfd = bus_space_read_4(iot, ioh, DPLL_DP_HFS_MFD); 328 dp_mfn = bus_space_read_4(iot, ioh, DPLL_DP_HFS_MFN); 329 } else { 330 dp_op = bus_space_read_4(iot, ioh, DPLL_DP_OP); 331 dp_mfd = bus_space_read_4(iot, ioh, DPLL_DP_MFD); 332 dp_mfn = bus_space_read_4(iot, ioh, DPLL_DP_MFN); 333 } 334 335 pdf = dp_op & DP_OP_PDF_MASK; 336 mfi = max(5, __SHIFTOUT(dp_op, DP_OP_MFI_MASK)); 337 mfd = dp_mfd; 338 if (dp_mfn & __BIT(26)) 339 /* 27bit signed value */ 340 mfn = (int32_t)(__BITS(31,27) | dp_mfn); 341 else 342 mfn = dp_mfn; 343 344 switch (dp_ctrl & DP_CTL_REF_CLK_SEL_MASK) { 345 case DP_CTL_REF_CLK_SEL_COSC: 346 /* Internal Oscillator */ 347 ref = IMX51_OSC_FREQ; 348 break; 349 case DP_CTL_REF_CLK_SEL_FPM: 350 ccr = bus_space_read_4(iot, ccm_softc->sc_ioh, CCMC_CCR); 351 if (ccr & CCR_FPM_MULT) 352 ref = IMX51_CKIL_FREQ * 1024; 353 else 354 ref = IMX51_CKIL_FREQ * 512; 355 break; 356 default: 357 ref = 0; 358 } 359 360 361 if (dp_ctrl & DP_CTL_REF_CLK_DIV) 362 ref /= 2; 363 364 #if 0 365 if (dp_ctrl & DP_CTL_DPDCK0_2_EN) 366 ref *= 2; 367 368 ref /= (pdf + 1); 369 freq = ref * mfn; 370 freq /= (mfd + 1); 371 freq = (ref * mfi) + freq; 372 #endif 373 374 ref *= 4; 375 freq = (int64_t)ref * mfi + (int64_t)ref * mfn / (mfd + 1); 376 freq /= pdf + 1; 377 378 if (!(dp_ctrl & DP_CTL_DPDCK0_2_EN)) 379 freq /= 2; 380 381 382 #ifdef IMXCCMDEBUG 383 printf("dp_ctl: %08x ", dp_ctrl); 384 printf("pdf: %3d ", pdf); 385 printf("mfi: %3d ", mfi); 386 printf("mfd: %3d ", mfd); 387 printf("mfn: %3d ", mfn); 388 printf("pll: %lld\n", freq); 389 #endif 390 391 ccm_softc->sc_pll[pll_no-1].pll_freq = freq; 392 393 return freq; 394 } 395 396 void 397 imx51_clk_gating(int clk_src, int mode) 398 { 399 bus_space_tag_t iot = ccm_softc->sc_iot; 400 bus_space_handle_t ioh = ccm_softc->sc_ioh; 401 uint32_t group = CCMR_CCGR_MODULE(clk_src); 402 uint32_t field = clk_src % CCMR_CCGR_NSOURCE; 403 uint32_t reg; 404 uint32_t bit; 405 406 bit = (mode << field * 2); 407 reg = bus_space_read_4(iot, ioh, CCMC_CCGR(group)); 408 reg &= ~(0x03 << field * 2); 409 reg |= bit; 410 bus_space_write_4(iot, ioh, CCMC_CCGR(group), reg); 411 } 412
Indexes created Wed Oct 15 16:09:53 GMT 2025