imx51_ccm.c revision 1.3.2.1
1 /* $NetBSD: imx51_ccm.c,v 1.3.2.1 2014/05/18 17:44:58 rmind Exp $ */ 2 /* 3 * Copyright (c) 2010, 2011, 2012 Genetec Corporation. All rights reserved. 4 * Written by Hashimoto Kenichi for Genetec Corporation. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * Clock Controller Module (CCM) 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: imx51_ccm.c,v 1.3.2.1 2014/05/18 17:44:58 rmind Exp $"); 34 35 #include <sys/types.h> 36 #include <sys/time.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/param.h> 40 41 #include <machine/cpu.h> 42 43 #include <arm/imx/imx51_ccmvar.h> 44 #include <arm/imx/imx51_ccmreg.h> 45 #include <arm/imx/imx51_dpllreg.h> 46 47 #include <arm/imx/imx51var.h> 48 #include <arm/imx/imx51reg.h> 49 50 #include "opt_imx51clk.h" 51 #include "locators.h" 52 53 //#define IMXCCMDEBUG 54 55 #ifndef IMX51_OSC_FREQ 56 #define IMX51_OSC_FREQ (24 * 1000 * 1000) /* 24MHz */ 57 #endif 58 59 struct imxccm_softc { 60 device_t sc_dev; 61 bus_space_tag_t sc_iot; 62 bus_space_handle_t sc_ioh; 63 64 struct { 65 bus_space_handle_t pll_ioh; 66 u_int pll_freq; 67 } sc_pll[IMX51_N_DPLLS]; 68 }; 69 70 struct imxccm_softc *ccm_softc; 71 72 static uint64_t imx51_get_pll_freq(u_int); 73 74 static int imxccm_match(device_t, cfdata_t, void *); 75 static void imxccm_attach(device_t, device_t, void *); 76 77 CFATTACH_DECL_NEW(imxccm, sizeof(struct imxccm_softc), 78 imxccm_match, imxccm_attach, NULL, NULL); 79 80 static int 81 imxccm_match(device_t parent, cfdata_t cfdata, void *aux) 82 { 83 struct axi_attach_args *aa = aux; 84 85 if (ccm_softc != NULL) 86 return 0; 87 88 if (aa->aa_addr == CCMC_BASE) 89 return 1; 90 91 return 0; 92 } 93 94 static void 95 imxccm_attach(device_t parent, device_t self, void *aux) 96 { 97 struct imxccm_softc * const sc = device_private(self); 98 struct axi_attach_args *aa = aux; 99 bus_space_tag_t iot = aa->aa_iot; 100 101 ccm_softc = sc; 102 sc->sc_dev = self; 103 sc->sc_iot = iot; 104 105 if (bus_space_map(iot, aa->aa_addr, CCMC_SIZE, 0, &sc->sc_ioh)) { 106 aprint_error(": can't map registers\n"); 107 return; 108 } 109 110 for (u_int i=1; i <= IMX51_N_DPLLS; ++i) { 111 if (bus_space_map(iot, DPLL_BASE(i), DPLL_SIZE, 0, 112 &sc->sc_pll[i-1].pll_ioh)) { 113 aprint_error(": can't map pll registers\n"); 114 return; 115 } 116 } 117 118 aprint_normal(": Clock control module\n"); 119 aprint_naive("\n"); 120 121 imx51_get_pll_freq(1); 122 imx51_get_pll_freq(2); 123 imx51_get_pll_freq(3); 124 125 126 aprint_verbose_dev(self, "CPU clock=%d, UART clock=%d\n", 127 imx51_get_clock(IMX51CLK_ARM_ROOT), 128 imx51_get_clock(IMX51CLK_UART_CLK_ROOT)); 129 aprint_verbose_dev(self, 130 "mainbus clock=%d, ahb clock=%d ipg clock=%d perclk=%d\n", 131 imx51_get_clock(IMX51CLK_MAIN_BUS_CLK), 132 imx51_get_clock(IMX51CLK_AHB_CLK_ROOT), 133 imx51_get_clock(IMX51CLK_IPG_CLK_ROOT), 134 imx51_get_clock(IMX51CLK_PERCLK_ROOT)); 135 } 136 137 138 u_int 139 imx51_get_clock(enum imx51_clock clk) 140 { 141 bus_space_tag_t iot = ccm_softc->sc_iot; 142 bus_space_handle_t ioh = ccm_softc->sc_ioh; 143 144 u_int freq = 0; 145 u_int sel; 146 uint32_t cacrr; /* ARM clock root register */ 147 uint32_t ccsr; 148 uint32_t cscdr1; 149 uint32_t cscdr2; 150 uint32_t cscmr1; 151 uint32_t cbcdr; 152 uint32_t cbcmr; 153 uint32_t cdcr; 154 155 switch (clk) { 156 case IMX51CLK_PLL1: 157 case IMX51CLK_PLL2: 158 case IMX51CLK_PLL3: 159 return ccm_softc->sc_pll[clk - IMX51CLK_PLL1].pll_freq; 160 case IMX51CLK_PLL1SW: 161 ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR); 162 if ((ccsr & CCSR_PLL1_SW_CLK_SEL) == 0) 163 return ccm_softc->sc_pll[1-1].pll_freq; 164 /* step clock */ 165 /* FALLTHROUGH */ 166 case IMX51CLK_PLL1STEP: 167 ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR); 168 switch (__SHIFTOUT(ccsr, CCSR_STEP_SEL_MASK)) { 169 case 0: 170 return imx51_get_clock(IMX51CLK_LP_APM); 171 case 1: 172 return 0; /* XXX PLL bypass clock */ 173 case 2: 174 return ccm_softc->sc_pll[2-1].pll_freq / 175 (1 + __SHIFTOUT(ccsr, CCSR_PLL2_DIV_PODF_MASK)); 176 case 3: 177 return ccm_softc->sc_pll[3-1].pll_freq / 178 (1 + __SHIFTOUT(ccsr, CCSR_PLL3_DIV_PODF_MASK)); 179 } 180 /*NOTREACHED*/ 181 case IMX51CLK_PLL2SW: 182 ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR); 183 if ((ccsr & CCSR_PLL2_SW_CLK_SEL) == 0) 184 return imx51_get_clock(IMX51CLK_PLL2); 185 return 0; /* XXX PLL2 bypass clk */ 186 case IMX51CLK_PLL3SW: 187 ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR); 188 if ((ccsr & CCSR_PLL3_SW_CLK_SEL) == 0) 189 return imx51_get_clock(IMX51CLK_PLL3); 190 return 0; /* XXX PLL3 bypass clk */ 191 192 case IMX51CLK_LP_APM: 193 ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR); 194 return (ccsr & CCSR_LP_APM) ? 195 imx51_get_clock(IMX51CLK_FPM) : IMX51_OSC_FREQ; 196 197 case IMX51CLK_ARM_ROOT: 198 freq = imx51_get_clock(IMX51CLK_PLL1SW); 199 cacrr = bus_space_read_4(iot, ioh, CCMC_CACRR); 200 return freq / (cacrr + 1); 201 202 /* ... */ 203 case IMX51CLK_MAIN_BUS_CLK_SRC: 204 cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR); 205 if ((cbcdr & CBCDR_PERIPH_CLK_SEL) == 0) 206 freq = imx51_get_clock(IMX51CLK_PLL2SW); 207 else { 208 cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR); 209 switch (__SHIFTOUT(cbcmr, CBCMR_PERIPH_APM_SEL_MASK)) { 210 case 0: 211 freq = imx51_get_clock(IMX51CLK_PLL1SW); 212 break; 213 case 1: 214 freq = imx51_get_clock(IMX51CLK_PLL3SW); 215 break; 216 case 2: 217 freq = imx51_get_clock(IMX51CLK_LP_APM); 218 break; 219 case 3: 220 /* XXX: error */ 221 break; 222 } 223 } 224 return freq; 225 case IMX51CLK_MAIN_BUS_CLK: 226 freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC); 227 cdcr = bus_space_read_4(iot, ioh, CCMC_CDCR); 228 return freq / __SHIFTOUT(cdcr, CDCR_PERIPH_CLK_DVFS_PODF_MASK); 229 case IMX51CLK_AHB_CLK_ROOT: 230 freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK); 231 cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR); 232 return freq / (1 + __SHIFTOUT(cbcdr, CBCDR_AHB_PODF_MASK)); 233 case IMX51CLK_IPG_CLK_ROOT: 234 freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT); 235 cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR); 236 return freq / (1 + __SHIFTOUT(cbcdr, CBCDR_IPG_PODF_MASK)); 237 case IMX51CLK_PERCLK_ROOT: 238 cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR); 239 if (cbcmr & CBCMR_PERCLK_IPG_SEL) 240 return imx51_get_clock(IMX51CLK_IPG_CLK_ROOT); 241 if (cbcmr & CBCMR_PERCLK_LP_APM_SEL) 242 freq = imx51_get_clock(IMX51CLK_LP_APM); 243 else 244 freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC); 245 246 cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR); 247 248 #ifdef IMXCCMDEBUG 249 printf("cbcmr=%x cbcdr=%x\n", cbcmr, cbcdr); 250 #endif 251 252 freq /= 1 + __SHIFTOUT(cbcdr, CBCDR_PERCLK_PRED1_MASK); 253 freq /= 1 + __SHIFTOUT(cbcdr, CBCDR_PERCLK_PRED2_MASK); 254 freq /= 1 + __SHIFTOUT(cbcdr, CBCDR_PERCLK_PODF_MASK); 255 return freq; 256 case IMX51CLK_UART_CLK_ROOT: 257 cscdr1 = bus_space_read_4(iot, ioh, CCMC_CSCDR1); 258 cscmr1 = bus_space_read_4(iot, ioh, CCMC_CSCMR1); 259 260 #ifdef IMXCCMDEBUG 261 printf("cscdr1=%x cscmr1=%x\n", cscdr1, cscmr1); 262 #endif 263 264 sel = __SHIFTOUT(cscmr1, CSCMR1_UART_CLK_SEL_MASK); 265 266 switch (sel) { 267 case 0: 268 case 1: 269 case 2: 270 freq = imx51_get_clock(IMX51CLK_PLL1SW + sel); 271 break; 272 case 3: 273 freq = imx51_get_clock(IMX51CLK_LP_APM); 274 break; 275 } 276 277 return freq / (1 + __SHIFTOUT(cscdr1, CSCDR1_UART_CLK_PRED_MASK)) / 278 (1 + __SHIFTOUT(cscdr1, CSCDR1_UART_CLK_PODF_MASK)); 279 case IMX51CLK_IPU_HSP_CLK_ROOT: 280 cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR); 281 switch (__SHIFTOUT(cbcmr, CBCMR_IPU_HSP_CLK_SEL_MASK)) { 282 case 0: 283 freq = imx51_get_clock(IMX51CLK_ARM_AXI_A_CLK); 284 break; 285 case 1: 286 freq = imx51_get_clock(IMX51CLK_ARM_AXI_B_CLK); 287 break; 288 case 2: 289 freq = imx51_get_clock( 290 IMX51CLK_EMI_SLOW_CLK_ROOT); 291 break; 292 case 3: 293 freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT); 294 break; 295 } 296 return freq; 297 case IMX51CLK_ESDHC2_CLK_ROOT: 298 case IMX51CLK_ESDHC4_CLK_ROOT: 299 cscmr1 = bus_space_read_4(iot, ioh, CCMC_CSCMR1); 300 301 sel = 0; 302 if (clk == IMX51CLK_ESDHC2_CLK_ROOT) 303 sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC2_CLK_SEL); 304 else if (clk == IMX51CLK_ESDHC4_CLK_ROOT) 305 sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC4_CLK_SEL); 306 307 if (sel == 0) 308 freq = imx51_get_clock(IMX51CLK_ESDHC1_CLK_ROOT); 309 else 310 freq = imx51_get_clock(IMX51CLK_ESDHC3_CLK_ROOT); 311 312 return freq; 313 case IMX51CLK_ESDHC1_CLK_ROOT: 314 case IMX51CLK_ESDHC3_CLK_ROOT: 315 316 cscdr1 = bus_space_read_4(iot, ioh, CCMC_CSCDR1); 317 cscmr1 = bus_space_read_4(iot, ioh, CCMC_CSCMR1); 318 319 sel = 0; 320 if (clk == IMX51CLK_ESDHC1_CLK_ROOT) 321 sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC1_CLK_SEL); 322 else if (clk == IMX51CLK_ESDHC3_CLK_ROOT) 323 sel = __SHIFTOUT(cscmr1, CSCMR1_ESDHC3_CLK_SEL); 324 325 switch (sel) { 326 case 0: 327 case 1: 328 case 2: 329 freq = imx51_get_clock(IMX51CLK_PLL1SW + sel); 330 break; 331 case 3: 332 freq = imx51_get_clock(IMX51CLK_LP_APM); 333 break; 334 } 335 336 if (clk == IMX51CLK_ESDHC1_CLK_ROOT) 337 freq = freq / (1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC1_CLK_PRED)) / 338 (1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC1_CLK_PODF)); 339 else if (clk == IMX51CLK_ESDHC3_CLK_ROOT) 340 freq = freq / (1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC3_CLK_PRED)) / 341 (1 + __SHIFTOUT(cscdr1, CSCDR1_ESDHC3_CLK_PODF)); 342 return freq; 343 case IMX51CLK_CSPI_CLK_ROOT: 344 cscmr1 = bus_space_read_4(iot, ioh, CCMC_CSCMR1); 345 cscdr2 = bus_space_read_4(iot, ioh, CCMC_CSCDR2); 346 347 sel = __SHIFTOUT(cscmr1, CSCMR1_CSPI_CLK_SEL); 348 switch (sel) { 349 case 0: 350 case 1: 351 case 2: 352 freq = imx51_get_clock(IMX51CLK_PLL1SW + sel); 353 break; 354 case 3: 355 freq = imx51_get_clock(IMX51CLK_LP_APM); 356 break; 357 } 358 359 freq = freq / (1 + __SHIFTOUT(cscdr2, CSCDR2_ECSPI_CLK_PRED)) / 360 (1 + __SHIFTOUT(cscdr2, CSCDR2_ECSPI_CLK_PODF)); 361 362 return freq; 363 default: 364 aprint_error_dev(ccm_softc->sc_dev, 365 "clock %d: not supported yet\n", clk); 366 return 0; 367 } 368 } 369 370 371 static uint64_t 372 imx51_get_pll_freq(u_int pll_no) 373 { 374 uint32_t dp_ctrl; 375 uint32_t dp_op; 376 uint32_t dp_mfd; 377 uint32_t dp_mfn; 378 uint32_t mfi; 379 int32_t mfn; 380 uint32_t mfd; 381 uint32_t pdf; 382 uint32_t ccr; 383 uint64_t freq = 0; 384 u_int ref = 0; 385 bus_space_tag_t iot = ccm_softc->sc_iot; 386 bus_space_handle_t ioh = ccm_softc->sc_pll[pll_no-1].pll_ioh; 387 388 KASSERT(1 <= pll_no && pll_no <= IMX51_N_DPLLS); 389 390 dp_ctrl = bus_space_read_4(iot, ioh, DPLL_DP_CTL); 391 392 if (dp_ctrl & DP_CTL_HFSM) { 393 dp_op = bus_space_read_4(iot, ioh, DPLL_DP_HFS_OP); 394 dp_mfd = bus_space_read_4(iot, ioh, DPLL_DP_HFS_MFD); 395 dp_mfn = bus_space_read_4(iot, ioh, DPLL_DP_HFS_MFN); 396 } else { 397 dp_op = bus_space_read_4(iot, ioh, DPLL_DP_OP); 398 dp_mfd = bus_space_read_4(iot, ioh, DPLL_DP_MFD); 399 dp_mfn = bus_space_read_4(iot, ioh, DPLL_DP_MFN); 400 } 401 402 pdf = dp_op & DP_OP_PDF_MASK; 403 mfi = max(5, __SHIFTOUT(dp_op, DP_OP_MFI_MASK)); 404 mfd = dp_mfd; 405 if (dp_mfn & __BIT(26)) 406 /* 27bit signed value */ 407 mfn = (int32_t)(__BITS(31,27) | dp_mfn); 408 else 409 mfn = dp_mfn; 410 411 switch (dp_ctrl & DP_CTL_REF_CLK_SEL_MASK) { 412 case DP_CTL_REF_CLK_SEL_COSC: 413 /* Internal Oscillator */ 414 ref = IMX51_OSC_FREQ; 415 break; 416 case DP_CTL_REF_CLK_SEL_FPM: 417 ccr = bus_space_read_4(iot, ccm_softc->sc_ioh, CCMC_CCR); 418 if (ccr & CCR_FPM_MULT) 419 ref = IMX51_CKIL_FREQ * 1024; 420 else 421 ref = IMX51_CKIL_FREQ * 512; 422 break; 423 default: 424 ref = 0; 425 } 426 427 428 if (dp_ctrl & DP_CTL_REF_CLK_DIV) 429 ref /= 2; 430 431 #if 0 432 if (dp_ctrl & DP_CTL_DPDCK0_2_EN) 433 ref *= 2; 434 435 ref /= (pdf + 1); 436 freq = ref * mfn; 437 freq /= (mfd + 1); 438 freq = (ref * mfi) + freq; 439 #endif 440 441 ref *= 4; 442 freq = (int64_t)ref * mfi + (int64_t)ref * mfn / (mfd + 1); 443 freq /= pdf + 1; 444 445 if (!(dp_ctrl & DP_CTL_DPDCK0_2_EN)) 446 freq /= 2; 447 448 449 #ifdef IMXCCMDEBUG 450 printf("dp_ctl: %08x ", dp_ctrl); 451 printf("pdf: %3d ", pdf); 452 printf("mfi: %3d ", mfi); 453 printf("mfd: %3d ", mfd); 454 printf("mfn: %3d ", mfn); 455 printf("pll: %lld\n", freq); 456 #endif 457 458 ccm_softc->sc_pll[pll_no-1].pll_freq = freq; 459 460 return freq; 461 } 462 463 void 464 imx51_clk_gating(int clk_src, int mode) 465 { 466 bus_space_tag_t iot = ccm_softc->sc_iot; 467 bus_space_handle_t ioh = ccm_softc->sc_ioh; 468 uint32_t group = CCMR_CCGR_MODULE(clk_src); 469 uint32_t field = clk_src % CCMR_CCGR_NSOURCE; 470 uint32_t reg; 471 uint32_t bit; 472 473 bit = (mode << field * 2); 474 reg = bus_space_read_4(iot, ioh, CCMC_CCGR(group)); 475 reg &= ~(0x03 << field * 2); 476 reg |= bit; 477 bus_space_write_4(iot, ioh, CCMC_CCGR(group), reg); 478 } 479
Indexes created Wed Oct 15 16:09:53 GMT 2025