imx51_esdhc.c revision 1.1.6.2 1 1.1 bsh /* $NetBSD: imx51_esdhc.c,v 1.1.6.2 2017/12/03 11:35:53 jdolecek Exp $ */
2 1.1 bsh
3 1.1 bsh /*-
4 1.1 bsh * Copyright (c) 2012 Genetec Corporation. All rights reserved.
5 1.1 bsh * Written by Hiroyuki Bessho for Genetec Corporation.
6 1.1 bsh *
7 1.1 bsh * Redistribution and use in source and binary forms, with or without
8 1.1 bsh * modification, are permitted provided that the following conditions
9 1.1 bsh * are met:
10 1.1 bsh * 1. Redistributions of source code must retain the above copyright
11 1.1 bsh * notice, this list of conditions and the following disclaimer.
12 1.1 bsh * 2. Redistributions in binary form must reproduce the above
13 1.1 bsh * copyright notice, this list of conditions and the following
14 1.1 bsh * disclaimer in the documentation and/or other materials provided
15 1.1 bsh * with the distribution.
16 1.1 bsh *
17 1.1 bsh * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS''
18 1.1 bsh * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
19 1.1 bsh * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
20 1.1 bsh * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS
21 1.1 bsh * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 1.1 bsh * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 1.1 bsh * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 1.1 bsh * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
25 1.1 bsh * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 1.1 bsh * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
27 1.1 bsh * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 1.1 bsh * SUCH DAMAGE.
29 1.1 bsh */
30 1.1 bsh
31 1.1 bsh
32 1.1 bsh #include <sys/cdefs.h>
33 1.1 bsh __KERNEL_RCSID(0, "$NetBSD: imx51_esdhc.c,v 1.1.6.2 2017/12/03 11:35:53 jdolecek Exp $");
34 1.1 bsh
35 1.1.6.1 tls #include "opt_imx.h"
36 1.1.6.1 tls
37 1.1 bsh #include <sys/param.h>
38 1.1 bsh #include <sys/device.h>
39 1.1 bsh #include <sys/systm.h>
40 1.1 bsh #include <sys/bus.h>
41 1.1 bsh #include <sys/pmf.h>
42 1.1 bsh
43 1.1 bsh #include <machine/intr.h>
44 1.1 bsh
45 1.1 bsh #include <dev/sdmmc/sdhcvar.h>
46 1.1 bsh #include <dev/sdmmc/sdmmcvar.h>
47 1.1 bsh
48 1.1 bsh #include <arm/imx/imx51reg.h>
49 1.1 bsh #include <arm/imx/imx51var.h>
50 1.1 bsh #include <arm/imx/imx51_ccmvar.h>
51 1.1 bsh
52 1.1 bsh struct sdhc_axi_softc {
53 1.1 bsh struct sdhc_softc sc_sdhc;
54 1.1 bsh /* we have only one slot */
55 1.1 bsh struct sdhc_host *sc_hosts[1];
56 1.1 bsh
57 1.1 bsh void *sc_ih;
58 1.1 bsh };
59 1.1 bsh
60 1.1 bsh static int sdhc_match(device_t, cfdata_t, void *);
61 1.1 bsh static void sdhc_attach(device_t, device_t, void *);
62 1.1 bsh
63 1.1 bsh CFATTACH_DECL_NEW(sdhc_axi, sizeof(struct sdhc_axi_softc),
64 1.1 bsh sdhc_match, sdhc_attach, NULL, NULL);
65 1.1 bsh
66 1.1 bsh static int
67 1.1 bsh sdhc_match(device_t parent, cfdata_t cf, void *aux)
68 1.1 bsh {
69 1.1 bsh
70 1.1 bsh struct axi_attach_args *aa = aux;
71 1.1 bsh
72 1.1 bsh switch (aa->aa_addr) {
73 1.1 bsh case ESDHC1_BASE:
74 1.1 bsh case ESDHC2_BASE:
75 1.1.6.1 tls case ESDHC3_BASE:
76 1.1.6.1 tls case ESDHC4_BASE:
77 1.1 bsh return 1;
78 1.1 bsh }
79 1.1 bsh
80 1.1 bsh return 0;
81 1.1 bsh }
82 1.1 bsh
83 1.1 bsh static void
84 1.1 bsh sdhc_attach(device_t parent, device_t self, void *aux)
85 1.1 bsh {
86 1.1 bsh struct sdhc_axi_softc *sc = device_private(self);
87 1.1 bsh struct axi_attach_args *aa = aux;
88 1.1 bsh bus_space_tag_t iot = aa->aa_iot;
89 1.1 bsh bus_space_handle_t ioh;
90 1.1.6.1 tls u_int perclk = 0;
91 1.1 bsh
92 1.1 bsh sc->sc_sdhc.sc_dev = self;
93 1.1 bsh
94 1.1 bsh sc->sc_sdhc.sc_dmat = aa->aa_dmat;
95 1.1 bsh
96 1.1 bsh if (bus_space_map(iot, aa->aa_addr, ESDHC_SIZE, 0, &ioh)) {
97 1.1 bsh aprint_error_dev(self, "can't map\n");
98 1.1 bsh return;
99 1.1 bsh }
100 1.1 bsh
101 1.1 bsh aprint_normal(": SD/MMC host controller\n");
102 1.1 bsh aprint_naive("\n");
103 1.1 bsh sc->sc_sdhc.sc_host = sc->sc_hosts;
104 1.1 bsh /* base clock frequency in kHz */
105 1.1.6.1 tls switch (aa->aa_addr) {
106 1.1.6.1 tls case ESDHC1_BASE:
107 1.1.6.1 tls perclk = imx51_get_clock(IMX51CLK_ESDHC1_CLK_ROOT);
108 1.1.6.1 tls break;;
109 1.1.6.1 tls case ESDHC2_BASE:
110 1.1.6.1 tls perclk = imx51_get_clock(IMX51CLK_ESDHC2_CLK_ROOT);
111 1.1.6.1 tls break;;
112 1.1.6.1 tls case ESDHC3_BASE:
113 1.1.6.1 tls perclk = imx51_get_clock(IMX51CLK_ESDHC3_CLK_ROOT);
114 1.1.6.1 tls break;;
115 1.1.6.1 tls case ESDHC4_BASE:
116 1.1.6.1 tls perclk = imx51_get_clock(IMX51CLK_ESDHC4_CLK_ROOT);
117 1.1.6.1 tls break;;
118 1.1.6.1 tls }
119 1.1 bsh sc->sc_sdhc.sc_clkbase = perclk / 1000;
120 1.1.6.2 jdolecek sc->sc_sdhc.sc_flags |= SDHC_FLAG_USE_DMA;
121 1.1 bsh sc->sc_sdhc.sc_flags |= SDHC_FLAG_HAVE_DVS |
122 1.1 bsh SDHC_FLAG_NO_PWR0 |
123 1.1 bsh SDHC_FLAG_32BIT_ACCESS |
124 1.1 bsh SDHC_FLAG_ENHANCED;
125 1.1 bsh
126 1.1 bsh sc->sc_ih = intr_establish(aa->aa_irq, IPL_SDMMC, IST_LEVEL,
127 1.1 bsh sdhc_intr, &sc->sc_sdhc);
128 1.1 bsh
129 1.1 bsh if (sc->sc_ih == NULL) {
130 1.1 bsh aprint_error_dev(self, "can't establish interrupt\n");
131 1.1 bsh return;
132 1.1 bsh }
133 1.1 bsh
134 1.1 bsh if (sdhc_host_found(&sc->sc_sdhc, iot, ioh, ESDHC_SIZE)) {
135 1.1 bsh aprint_error_dev(self, "can't initialize host\n");
136 1.1 bsh return;
137 1.1 bsh }
138 1.1 bsh
139 1.1 bsh if (!pmf_device_register1(self, sdhc_suspend, sdhc_resume,
140 1.1 bsh sdhc_shutdown)) {
141 1.1 bsh aprint_error_dev(self,
142 1.1 bsh "can't establish power hook\n");
143 1.1 bsh }
144 1.1 bsh }
145