imx51_iomuxreg.h revision 1.1.2.2
1 /* 2 * This file was generated automatically from PDF file by mkiomuxreg_imx51.rb 3 * 4 */ 5 #ifndef _IMX51_IOMUXREG_H 6 #define _IMX51_IOMUXREG_H 7 8 /* register offset address */ 9 10 #define IOMUXC_GPR0 0x0000 11 #define IOMUXC_GPR1 0x0004 12 #define IOMUXC_OBSERVE_MUX_0 0x0008 13 #define IOMUXC_OBSERVE_MUX_1 0x000c 14 #define IOMUXC_OBSERVE_MUX_2 0x0010 15 #define IOMUXC_OBSERVE_MUX_3 0x0014 16 #define IOMUXC_OBSERVE_MUX_4 0x0018 17 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA0 0x001c 18 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA1 0x0020 19 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA2 0x0024 20 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA3 0x0028 21 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA4 0x002c 22 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA5 0x0030 23 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA6 0x0034 24 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA7 0x0038 25 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA8 0x003c 26 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA9 0x0040 27 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA10 0x0044 28 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA11 0x0048 29 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA12 0x004c 30 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA13 0x0050 31 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA14 0x0054 32 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DA15 0x0058 33 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D16 0x005c 34 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D17 0x0060 35 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D18 0x0064 36 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D19 0x0068 37 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D20 0x006c 38 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D21 0x0070 39 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D22 0x0074 40 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D23 0x0078 41 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D24 0x007c 42 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D25 0x0080 43 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D26 0x0084 44 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D27 0x0088 45 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D28 0x008c 46 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D29 0x0090 47 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D30 0x0094 48 #define IOMUXC_SW_MUX_CTL_PAD_EIM_D31 0x0098 49 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A16 0x009c 50 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A17 0x00a0 51 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A18 0x00a4 52 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A19 0x00a8 53 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A20 0x00ac 54 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A21 0x00b0 55 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A22 0x00b4 56 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A23 0x00b8 57 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A24 0x00bc 58 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A25 0x00c0 59 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A26 0x00c4 60 #define IOMUXC_SW_MUX_CTL_PAD_EIM_A27 0x00c8 61 #define IOMUXC_SW_MUX_CTL_PAD_EIM_EB0 0x00cc 62 #define IOMUXC_SW_MUX_CTL_PAD_EIM_EB1 0x00d0 63 #define IOMUXC_SW_MUX_CTL_PAD_EIM_EB2 0x00d4 64 #define IOMUXC_SW_MUX_CTL_PAD_EIM_EB3 0x00d8 65 #define IOMUXC_SW_MUX_CTL_PAD_EIM_OE 0x00dc 66 #define IOMUXC_SW_MUX_CTL_PAD_EIM_CS0 0x00e0 67 #define IOMUXC_SW_MUX_CTL_PAD_EIM_CS1 0x00e4 68 #define IOMUXC_SW_MUX_CTL_PAD_EIM_CS2 0x00e8 69 #define IOMUXC_SW_MUX_CTL_PAD_EIM_CS3 0x00ec 70 #define IOMUXC_SW_MUX_CTL_PAD_EIM_CS4 0x00f0 71 #define IOMUXC_SW_MUX_CTL_PAD_EIM_CS5 0x00f4 72 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DTACK 0x00f8 73 #define IOMUXC_SW_MUX_CTL_PAD_EIM_LBA 0x00fc 74 #define IOMUXC_SW_MUX_CTL_PAD_EIM_CRE 0x0100 75 #define IOMUXC_SW_MUX_CTL_PAD_DRAM_CS1 0x0104 76 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_WE_B 0x0108 77 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_RE_B 0x010c 78 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE 0x0110 79 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE 0x0114 80 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B 0x0118 81 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0 0x011c 82 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB1 0x0120 83 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB2 0x0124 84 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_RB3 0x0128 85 #define IOMUXC_SW_MUX_CTL_PAD_GPIO_NAND 0x012c 86 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS0 0x0130 87 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS1 0x0134 88 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2 0x0138 89 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3 0x013c 90 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4 0x0140 91 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5 0x0144 92 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6 0x0148 93 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_CS7 0x014c 94 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_RDY_INT 0x0150 95 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D15 0x0154 96 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D14 0x0158 97 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D13 0x015c 98 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D12 0x0160 99 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D11 0x0164 100 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D10 0x0168 101 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D9 0x016c 102 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D8 0x0170 103 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D7 0x0174 104 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D6 0x0178 105 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D5 0x017c 106 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D4 0x0180 107 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D3 0x0184 108 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D2 0x0188 109 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D1 0x018c 110 #define IOMUXC_SW_MUX_CTL_PAD_NANDF_D0 0x0190 111 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D8 0x0194 112 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D9 0x0198 113 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D10 0x019c 114 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D11 0x01a0 115 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D12 0x01a4 116 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D13 0x01a8 117 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D14 0x01ac 118 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D15 0x01b0 119 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D16 0x01b4 120 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D17 0x01b8 121 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D18 0x01bc 122 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_D19 0x01c0 123 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_VSYNC 0x01c4 124 #define IOMUXC_SW_MUX_CTL_PAD_CSI1_HSYNC 0x01c8 125 #define IOMUXC_SW_MUX_CTL_PAD_CSI2_D12 0x01cc 126 #define IOMUXC_SW_MUX_CTL_PAD_CSI2_D13 0x01d0 127 #define IOMUXC_SW_MUX_CTL_PAD_CSI2_D14 0x01d4 128 #define IOMUXC_SW_MUX_CTL_PAD_CSI2_D15 0x01d8 129 #define IOMUXC_SW_MUX_CTL_PAD_CSI2_D16 0x01dc 130 #define IOMUXC_SW_MUX_CTL_PAD_CSI2_D17 0x01e0 131 #define IOMUXC_SW_MUX_CTL_PAD_CSI2_D18 0x01e4 132 #define IOMUXC_SW_MUX_CTL_PAD_CSI2_D19 0x01e8 133 #define IOMUXC_SW_MUX_CTL_PAD_CSI2_VSYNC 0x01ec 134 #define IOMUXC_SW_MUX_CTL_PAD_CSI2_HSYNC 0x01f0 135 #define IOMUXC_SW_MUX_CTL_PAD_CSI2_PIXCLK 0x01f4 136 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_CLK 0x01f8 137 #define IOMUXC_SW_MUX_CTL_PAD_I2C1_DAT 0x01fc 138 #define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_TXD 0x0200 139 #define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_RXD 0x0204 140 #define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_CK 0x0208 141 #define IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_FS 0x020c 142 #define IOMUXC_SW_MUX_CTL_PAD_CSPI1_MOSI 0x0210 143 #define IOMUXC_SW_MUX_CTL_PAD_CSPI1_MISO 0x0214 144 #define IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS0 0x0218 145 #define IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS1 0x021c 146 #define IOMUXC_SW_MUX_CTL_PAD_CSPI1_RDY 0x0220 147 #define IOMUXC_SW_MUX_CTL_PAD_CSPI1_SCLK 0x0224 148 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RXD 0x0228 149 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TXD 0x022c 150 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RTS 0x0230 151 #define IOMUXC_SW_MUX_CTL_PAD_UART1_CTS 0x0234 152 #define IOMUXC_SW_MUX_CTL_PAD_UART2_RXD 0x0238 153 #define IOMUXC_SW_MUX_CTL_PAD_UART2_TXD 0x023c 154 #define IOMUXC_SW_MUX_CTL_PAD_UART3_RXD 0x0240 155 #define IOMUXC_SW_MUX_CTL_PAD_UART3_TXD 0x0244 156 #define IOMUXC_SW_MUX_CTL_PAD_OWIRE_LINE 0x0248 157 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 0x024c 158 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 0x0250 159 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 0x0254 160 #define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 0x0258 161 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 0x025c 162 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 0x0260 163 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 0x0264 164 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 0x0268 165 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 0x026c 166 #define IOMUXC_SW_MUX_CTL_PAD_KEY_COL5 0x0270 167 #define IOMUXC_SW_MUX_CTL_PAD_JTAG_DE_B 0x0274 168 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_CLK 0x0278 169 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_DIR 0x027c 170 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_STP 0x0280 171 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_NXT 0x0284 172 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA0 0x0288 173 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA1 0x028c 174 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA2 0x0290 175 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA3 0x0294 176 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA4 0x0298 177 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA5 0x029c 178 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA6 0x02a0 179 #define IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA7 0x02a4 180 #define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN11 0x02a8 181 #define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN12 0x02ac 182 #define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN13 0x02b0 183 #define IOMUXC_SW_MUX_CTL_PAD_DI1_D0_CS 0x02b4 184 #define IOMUXC_SW_MUX_CTL_PAD_DI1_D1_CS 0x02b8 185 #define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_DIN 0x02bc 186 #define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_DIO 0x02c0 187 #define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_CLK 0x02c4 188 #define IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_RS 0x02c8 189 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT0 0x02cc 190 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT1 0x02d0 191 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT2 0x02d4 192 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT3 0x02d8 193 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT4 0x02dc 194 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT5 0x02e0 195 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT6 0x02e4 196 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT7 0x02e8 197 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT8 0x02ec 198 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT9 0x02f0 199 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT10 0x02f4 200 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT11 0x02f8 201 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT12 0x02fc 202 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT13 0x0300 203 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT14 0x0304 204 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT15 0x0308 205 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT16 0x030c 206 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT17 0x0310 207 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT18 0x0314 208 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT19 0x0318 209 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT20 0x031c 210 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT21 0x0320 211 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT22 0x0324 212 #define IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT23 0x0328 213 #define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN3 0x032c 214 #define IOMUXC_SW_MUX_CTL_PAD_DI1_PIN2 0x0330 215 #define IOMUXC_SW_MUX_CTL_PAD_DI_GP1 0x0334 216 #define IOMUXC_SW_MUX_CTL_PAD_DI_GP2 0x0338 217 #define IOMUXC_SW_MUX_CTL_PAD_DI_GP3 0x033c 218 #define IOMUXC_SW_MUX_CTL_PAD_DI2_PIN4 0x0340 219 #define IOMUXC_SW_MUX_CTL_PAD_DI2_PIN2 0x0344 220 #define IOMUXC_SW_MUX_CTL_PAD_DI2_PIN3 0x0348 221 #define IOMUXC_SW_MUX_CTL_PAD_DI2_DISP_CLK 0x034c 222 #define IOMUXC_SW_MUX_CTL_PAD_DI_GP4 0x0350 223 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT0 0x0354 224 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT1 0x0358 225 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT2 0x035c 226 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT3 0x0360 227 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT4 0x0364 228 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT5 0x0368 229 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT6 0x036c 230 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT7 0x0370 231 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT8 0x0374 232 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT9 0x0378 233 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT10 0x037c 234 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT11 0x0380 235 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT12 0x0384 236 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT13 0x0388 237 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT14 0x038c 238 #define IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT15 0x0390 239 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD 0x0394 240 #define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK 0x0398 241 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 0x039c 242 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 0x03a0 243 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 0x03a4 244 #define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 0x03a8 245 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_0 0x03ac 246 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_1 0x03b0 247 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD 0x03b4 248 #define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK 0x03b8 249 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 0x03bc 250 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 0x03c0 251 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 0x03c4 252 #define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 0x03c8 253 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_2 0x03cc 254 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_3 0x03d0 255 #define IOMUXC_SW_MUX_CTL_PAD_PMIC_INT_REQ 0x03d4 256 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_4 0x03d8 257 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_5 0x03dc 258 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_6 0x03e0 259 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_7 0x03e4 260 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_8 0x03e8 261 #define IOMUXC_SW_MUX_CTL_PAD_GPIO1_9 0x03ec 262 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D16 0x03f0 263 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D17 0x03f4 264 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D18 0x03f8 265 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D19 0x03fc 266 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D20 0x0400 267 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D21 0x0404 268 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D22 0x0408 269 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D23 0x040c 270 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D24 0x0410 271 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D25 0x0414 272 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D26 0x0418 273 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D27 0x041c 274 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D28 0x0420 275 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D29 0x0424 276 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D30 0x0428 277 #define IOMUXC_SW_PAD_CTL_PAD_EIM_D31 0x042c 278 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A16 0x0430 279 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A17 0x0434 280 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A18 0x0438 281 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A19 0x043c 282 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A20 0x0440 283 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A21 0x0444 284 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A22 0x0448 285 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A23 0x044c 286 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A24 0x0450 287 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A25 0x0454 288 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A26 0x0458 289 #define IOMUXC_SW_PAD_CTL_PAD_EIM_A27 0x045c 290 #define IOMUXC_SW_PAD_CTL_PAD_EIM_EB0 0x0460 291 #define IOMUXC_SW_PAD_CTL_PAD_EIM_EB1 0x0464 292 #define IOMUXC_SW_PAD_CTL_PAD_EIM_EB2 0x0468 293 #define IOMUXC_SW_PAD_CTL_PAD_EIM_EB3 0x046c 294 #define IOMUXC_SW_PAD_CTL_PAD_EIM_OE 0x0470 295 #define IOMUXC_SW_PAD_CTL_PAD_EIM_CS0 0x0474 296 #define IOMUXC_SW_PAD_CTL_PAD_EIM_CS1 0x0478 297 #define IOMUXC_SW_PAD_CTL_PAD_EIM_CS2 0x047c 298 #define IOMUXC_SW_PAD_CTL_PAD_EIM_CS3 0x0480 299 #define IOMUXC_SW_PAD_CTL_PAD_EIM_CS4 0x0484 300 #define IOMUXC_SW_PAD_CTL_PAD_EIM_CS5 0x0488 301 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DTACK 0x048c 302 #define IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT 0x0490 303 #define IOMUXC_SW_PAD_CTL_PAD_EIM_LBA 0x0494 304 #define IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK 0x0498 305 #define IOMUXC_SW_PAD_CTL_PAD_EIM_RW 0x049c 306 #define IOMUXC_SW_PAD_CTL_PAD_EIM_CRE 0x04a0 307 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x04a4 308 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x04a8 309 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE 0x04ac 310 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x04b0 311 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x04b4 312 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK 0x04b8 313 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 0x04bc 314 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 0x04c0 315 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 0x04c4 316 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 0x04c8 317 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0 0x04cc 318 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1 0x04d0 319 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x04d4 320 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x04d8 321 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x04dc 322 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x04e0 323 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B 0x04e4 324 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B 0x04e8 325 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_ALE 0x04ec 326 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE 0x04f0 327 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B 0x04f4 328 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0 0x04f8 329 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB1 0x04fc 330 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB2 0x0500 331 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_RB3 0x0504 332 #define IOMUXC_SW_PAD_CTL_PAD_EIM_SDBA2 0x0508 333 #define IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT1 0x050c 334 #define IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT0 0x0510 335 #define IOMUXC_SW_PAD_CTL_PAD_GPIO_NAND 0x0514 336 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS0 0x0518 337 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS1 0x051c 338 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2 0x0520 339 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3 0x0524 340 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS4 0x0528 341 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS5 0x052c 342 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS6 0x0530 343 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_CS7 0x0534 344 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_RDY_INT 0x0538 345 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D15 0x053c 346 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D14 0x0540 347 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D13 0x0544 348 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D12 0x0548 349 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D11 0x054c 350 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D10 0x0550 351 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D9 0x0554 352 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D8 0x0558 353 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D7 0x055c 354 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D6 0x0560 355 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D5 0x0564 356 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D4 0x0568 357 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D3 0x056c 358 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D2 0x0570 359 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D1 0x0574 360 #define IOMUXC_SW_PAD_CTL_PAD_NANDF_D0 0x0578 361 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D8 0x057c 362 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D9 0x0580 363 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D10 0x0584 364 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D11 0x0588 365 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D12 0x058c 366 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D13 0x0590 367 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D14 0x0594 368 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D15 0x0598 369 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D16 0x059c 370 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D17 0x05a0 371 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D18 0x05a4 372 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_D19 0x05a8 373 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_VSYNC 0x05ac 374 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_HSYNC 0x05b0 375 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_PIXCLK 0x05b4 376 #define IOMUXC_SW_PAD_CTL_PAD_CSI1_MCLK 0x05b8 377 #define IOMUXC_SW_PAD_CTL_PAD_CSI2_D12 0x05bc 378 #define IOMUXC_SW_PAD_CTL_PAD_CSI2_D13 0x05c0 379 #define IOMUXC_SW_PAD_CTL_PAD_CSI2_D14 0x05c4 380 #define IOMUXC_SW_PAD_CTL_PAD_CSI2_D15 0x05c8 381 #define IOMUXC_SW_PAD_CTL_PAD_CSI2_D16 0x05cc 382 #define IOMUXC_SW_PAD_CTL_PAD_CSI2_D17 0x05d0 383 #define IOMUXC_SW_PAD_CTL_PAD_CSI2_D18 0x05d4 384 #define IOMUXC_SW_PAD_CTL_PAD_CSI2_D19 0x05d8 385 #define IOMUXC_SW_PAD_CTL_PAD_CSI2_VSYNC 0x05dc 386 #define IOMUXC_SW_PAD_CTL_PAD_CSI2_HSYNC 0x05e0 387 #define IOMUXC_SW_PAD_CTL_PAD_CSI2_PIXCLK 0x05e4 388 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_CLK 0x05e8 389 #define IOMUXC_SW_PAD_CTL_PAD_I2C1_DAT 0x05ec 390 #define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_TXD 0x05f0 391 #define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_RXD 0x05f4 392 #define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_CK 0x05f8 393 #define IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_FS 0x05fc 394 #define IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI 0x0600 395 #define IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO 0x0604 396 #define IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 0x0608 397 #define IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 0x060c 398 #define IOMUXC_SW_PAD_CTL_PAD_CSPI1_RDY 0x0610 399 #define IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK 0x0614 400 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RXD 0x0618 401 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TXD 0x061c 402 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RTS 0x0620 403 #define IOMUXC_SW_PAD_CTL_PAD_UART1_CTS 0x0624 404 #define IOMUXC_SW_PAD_CTL_PAD_UART2_RXD 0x0628 405 #define IOMUXC_SW_PAD_CTL_PAD_UART2_TXD 0x062c 406 #define IOMUXC_SW_PAD_CTL_PAD_UART3_RXD 0x0630 407 #define IOMUXC_SW_PAD_CTL_PAD_UART3_TXD 0x0634 408 #define IOMUXC_SW_PAD_CTL_PAD_OWIRE_LINE 0x0638 409 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 0x063c 410 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 0x0640 411 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 0x0644 412 #define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 0x0648 413 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 0x064c 414 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 0x0650 415 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 0x0654 416 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 0x0658 417 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 0x065c 418 #define IOMUXC_SW_PAD_CTL_PAD_KEY_COL5 0x0660 419 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK 0x0664 420 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS 0x0668 421 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI 0x066c 422 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB 0x0670 423 #define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD 0x0674 424 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_CLK 0x0678 425 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_DIR 0x067c 426 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_STP 0x0680 427 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_NXT 0x0684 428 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA0 0x0688 429 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA1 0x068c 430 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA2 0x0690 431 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA3 0x0694 432 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA4 0x0698 433 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA5 0x069c 434 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA6 0x06a0 435 #define IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA7 0x06a4 436 #define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 0x06a8 437 #define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN12 0x06ac 438 #define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN13 0x06b0 439 #define IOMUXC_SW_PAD_CTL_PAD_DI1_D0_CS 0x06b4 440 #define IOMUXC_SW_PAD_CTL_PAD_DI1_D1_CS 0x06b8 441 #define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_DIN 0x06bc 442 #define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_DIO 0x06c0 443 #define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_CLK 0x06c4 444 #define IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_RS 0x06c8 445 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT0 0x06cc 446 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT1 0x06d0 447 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT2 0x06d4 448 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT3 0x06d8 449 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT4 0x06dc 450 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT5 0x06e0 451 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT6 0x06e4 452 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT7 0x06e8 453 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT8 0x06ec 454 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT9 0x06f0 455 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT10 0x06f4 456 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT11 0x06f8 457 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT12 0x06fc 458 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT13 0x0700 459 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT14 0x0704 460 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT15 0x0708 461 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT16 0x070c 462 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT17 0x0710 463 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT18 0x0714 464 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT19 0x0718 465 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT20 0x071c 466 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT21 0x0720 467 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT22 0x0724 468 #define IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT23 0x0728 469 #define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN3 0x072c 470 #define IOMUXC_SW_PAD_CTL_PAD_DI1_DISP_CLK 0x0730 471 #define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN2 0x0734 472 #define IOMUXC_SW_PAD_CTL_PAD_DI1_PIN15 0x0738 473 #define IOMUXC_SW_PAD_CTL_PAD_DI_GP1 0x073c 474 #define IOMUXC_SW_PAD_CTL_PAD_DI_GP2 0x0740 475 #define IOMUXC_SW_PAD_CTL_PAD_DI_GP3 0x0744 476 #define IOMUXC_SW_PAD_CTL_PAD_DI2_PIN4 0x0748 477 #define IOMUXC_SW_PAD_CTL_PAD_DI2_PIN2 0x074c 478 #define IOMUXC_SW_PAD_CTL_PAD_DI2_PIN3 0x0750 479 #define IOMUXC_SW_PAD_CTL_PAD_DI2_DISP_CLK 0x0754 480 #define IOMUXC_SW_PAD_CTL_PAD_DI_GP4 0x0758 481 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT0 0x075c 482 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT1 0x0760 483 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT2 0x0764 484 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT3 0x0768 485 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT4 0x076c 486 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT5 0x0770 487 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT6 0x0774 488 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT7 0x0778 489 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT8 0x077c 490 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT9 0x0780 491 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT10 0x0784 492 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT11 0x0788 493 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT12 0x078c 494 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT13 0x0790 495 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT14 0x0794 496 #define IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT15 0x0798 497 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD 0x079c 498 #define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK 0x07a0 499 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 0x07a4 500 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 0x07a8 501 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 0x07ac 502 #define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 0x07b0 503 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_0 0x07b4 504 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_1 0x07b8 505 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD 0x07bc 506 #define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK 0x07c0 507 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 0x07c4 508 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 0x07c8 509 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 0x07cc 510 #define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 0x07d0 511 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_2 0x07d4 512 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_3 0x07d8 513 #define IOMUXC_SW_PAD_CTL_PAD_RESET_IN_B 0x07dc 514 #define IOMUXC_SW_PAD_CTL_PAD_POR_B 0x07e0 515 #define IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1 0x07e4 516 #define IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0 0x07e8 517 #define IOMUXC_SW_PAD_CTL_PAD_PMIC_RDY 0x07ec 518 #define IOMUXC_SW_PAD_CTL_PAD_CKIL 0x07f0 519 #define IOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ 0x07f4 520 #define IOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ 0x07f8 521 #define IOMUXC_SW_PAD_CTL_PAD_PMIC_INT_REQ 0x07fc 522 #define IOMUXC_SW_PAD_CTL_PAD_CLK_SS 0x0800 523 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_4 0x0804 524 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_5 0x0808 525 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_6 0x080c 526 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_7 0x0810 527 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_8 0x0814 528 #define IOMUXC_SW_PAD_CTL_PAD_GPIO1_9 0x0818 529 #define IOMUXC_SW_PAD_CTL_GRP_CSI2_PKE0 0x081c 530 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKS 0x0820 531 #define IOMUXC_SW_PAD_CTL_GRP_EIM_SR1 0x0824 532 #define IOMUXC_SW_PAD_CTL_GRP_DISP2_PKE0 0x0828 533 #define IOMUXC_SW_PAD_CTL_GRP_DRAM_B4 0x082c 534 #define IOMUXC_SW_PAD_CTL_GRP_INDDR 0x0830 535 #define IOMUXC_SW_PAD_CTL_GRP_EIM_SR2 0x0834 536 #define IOMUXC_SW_PAD_CTL_GRP_PKEDDR 0x0838 537 #define IOMUXC_SW_PAD_CTL_GRP_DDR_A0 0x083c 538 #define IOMUXC_SW_PAD_CTL_GRP_EMI_PKE0 0x0840 539 #define IOMUXC_SW_PAD_CTL_GRP_EIM_SR3 0x0844 540 #define IOMUXC_SW_PAD_CTL_GRP_DDR_A1 0x0848 541 #define IOMUXC_SW_PAD_CTL_GRP_DDRAPUS 0x084c 542 #define IOMUXC_SW_PAD_CTL_GRP_EIM_SR4 0x0850 543 #define IOMUXC_SW_PAD_CTL_GRP_EMI_SR5 0x0854 544 #define IOMUXC_SW_PAD_CTL_GRP_EMI_SR6 0x0858 545 #define IOMUXC_SW_PAD_CTL_GRP_HYSDDR0 0x085c 546 #define IOMUXC_SW_PAD_CTL_GRP_CSI1_PKE0 0x0860 547 #define IOMUXC_SW_PAD_CTL_GRP_HYSDDR1 0x0864 548 #define IOMUXC_SW_PAD_CTL_GRP_DISP1_PKE0 0x0868 549 #define IOMUXC_SW_PAD_CTL_GRP_HYSDDR2 0x086c 550 #define IOMUXC_SW_PAD_CTL_GRP_HVDDR 0x0870 551 #define IOMUXC_SW_PAD_CTL_GRP_HYSDDR3 0x0874 552 #define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B0 0x0878 553 #define IOMUXC_SW_PAD_CTL_GRP_DDRAPKS 0x087c 554 #define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B1 0x0880 555 #define IOMUXC_SW_PAD_CTL_GRP_DDRPUS 0x0884 556 #define IOMUXC_SW_PAD_CTL_GRP_EIM_DS1 0x0888 557 #define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B2 0x088c 558 #define IOMUXC_SW_PAD_CTL_GRP_PKEADDR 0x0890 559 #define IOMUXC_SW_PAD_CTL_GRP_EIM_DS2 0x0894 560 #define IOMUXC_SW_PAD_CTL_GRP_EIM_DS3 0x0898 561 #define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B4 0x089c 562 #define IOMUXC_SW_PAD_CTL_GRP_INMODE1 0x08a0 563 #define IOMUXC_SW_PAD_CTL_GRP_DRAM_B0 0x08a4 564 #define IOMUXC_SW_PAD_CTL_GRP_EIM_DS4 0x08a8 565 #define IOMUXC_SW_PAD_CTL_GRP_DRAM_B1 0x08ac 566 #define IOMUXC_SW_PAD_CTL_GRP_DDR_SR_A0 0x08b0 567 #define IOMUXC_SW_PAD_CTL_GRP_EMI_DS5 0x08b4 568 #define IOMUXC_SW_PAD_CTL_GRP_DRAM_B2 0x08b8 569 #define IOMUXC_SW_PAD_CTL_GRP_DDR_SR_A1 0x08bc 570 #define IOMUXC_SW_PAD_CTL_GRP_EMI_DS6 0x08c0 571 #define IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT 0x08c4 572 #define IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT 0x08c8 573 #define IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT 0x08cc 574 #define IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT 0x08d0 575 #define IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT 0x08d4 576 #define IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT 0x08d8 577 #define IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT 0x08dc 578 #define IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT 0x08e0 579 #define IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT 0x08e4 580 #define IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT 0x08e8 581 #define IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT 0x08ec 582 #define IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT 0x08f0 583 #define IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT 0x08f4 584 #define IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT 0x08f8 585 #define IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT 0x08fc 586 #define IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT 0x0900 587 #define IOMUXC_CCM_IPP_DI0_CLK_SELECT_INPUT 0x0904 588 #define IOMUXC_CCM_IPP_DI1_CLK_SELECT_INPUT 0x0908 589 #define IOMUXC_CCM_PLL1_BYPASS_CLK_SELECT_INPUT 0x090c 590 #define IOMUXC_CCM_PLL2_BYPASS_CLK_SELECT_INPUT 0x0910 591 #define IOMUXC_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT 0x0914 592 #define IOMUXC_CSPI_IPP_IND_MISO_SELECT_INPUT 0x0918 593 #define IOMUXC_CSPI_IPP_IND_MOSI_SELECT_INPUT 0x091c 594 #define IOMUXC_CSPI_IPP_IND_SS1_B_SELECT_INPUT 0x0920 595 #define IOMUXC_CSPI_IPP_IND_SS2_B_SELECT_INPUT 0x0924 596 #define IOMUXC_CSPI_IPP_IND_SS3_B_SELECT_INPUT 0x0928 597 #define IOMUXC_DPLLIP1_L1T_TOG_EN_SELECT_INPUT 0x092c 598 #define IOMUXC_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT 0x0930 599 #define IOMUXC_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT 0x0934 600 #define IOMUXC_EMI_IPP_IND_RDY_INT_SELECT_INPUT 0x0938 601 #define IOMUXC_ESDHC3_IPP_DAT0_IN_SELECT_INPUT 0x093c 602 #define IOMUXC_ESDHC3_IPP_DAT1_IN_SELECT_INPUT 0x0940 603 #define IOMUXC_ESDHC3_IPP_DAT2_IN_SELECT_INPUT 0x0944 604 #define IOMUXC_ESDHC3_IPP_DAT3_IN_SELECT_INPUT 0x0948 605 #define IOMUXC_FEC_FEC_COL_SELECT_INPUT 0x094c 606 #define IOMUXC_FEC_FEC_CRS_SELECT_INPUT 0x0950 607 #define IOMUXC_FEC_FEC_MDI_SELECT_INPUT 0x0954 608 #define IOMUXC_FEC_FEC_RDATA_0_SELECT_INPUT 0x0958 609 #define IOMUXC_FEC_FEC_RDATA_1_SELECT_INPUT 0x095c 610 #define IOMUXC_FEC_FEC_RDATA_2_SELECT_INPUT 0x0960 611 #define IOMUXC_FEC_FEC_RDATA_3_SELECT_INPUT 0x0964 612 #define IOMUXC_FEC_FEC_RX_CLK_SELECT_INPUT 0x0968 613 #define IOMUXC_FEC_FEC_RX_DV_SELECT_INPUT 0x096c 614 #define IOMUXC_FEC_FEC_RX_ER_SELECT_INPUT 0x0970 615 #define IOMUXC_FEC_FEC_TX_CLK_SELECT_INPUT 0x0974 616 #define IOMUXC_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT 0x0978 617 #define IOMUXC_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT 0x097c 618 #define IOMUXC_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT 0x0980 619 #define IOMUXC_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT 0x0984 620 #define IOMUXC_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT 0x0988 621 #define IOMUXC_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT 0x098c 622 #define IOMUXC_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT 0x0990 623 #define IOMUXC_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT 0x0994 624 #define IOMUXC_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT 0x0998 625 #define IOMUXC_HSC_MIPI_MIX_PAR0_VSYNC_SELECT_INPUT 0x09a4 626 #define IOMUXC_HSC_MIPI_MIX_PAR1_DI_WAIT_SELECT_INPUT 0x09a8 627 #define IOMUXC_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT 0x09ac 628 #define IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT 0x09b0 629 #define IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT 0x09b4 630 #define IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT 0x09b8 631 #define IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT 0x09bc 632 #define IOMUXC_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT 0x09c0 633 #define IOMUXC_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT 0x09c4 634 #define IOMUXC_KPP_IPP_IND_COL_6_SELECT_INPUT 0x09c8 635 #define IOMUXC_KPP_IPP_IND_COL_7_SELECT_INPUT 0x09cc 636 #define IOMUXC_KPP_IPP_IND_ROW_4_SELECT_INPUT 0x09d0 637 #define IOMUXC_KPP_IPP_IND_ROW_5_SELECT_INPUT 0x09d4 638 #define IOMUXC_KPP_IPP_IND_ROW_6_SELECT_INPUT 0x09d8 639 #define IOMUXC_KPP_IPP_IND_ROW_7_SELECT_INPUT 0x09dc 640 #define IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT 0x09e0 641 #define IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT 0x09e4 642 #define IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT 0x09e8 643 #define IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT 0x09ec 644 #define IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT 0x09f0 645 #define IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT 0x09f4 646 #define IOMUXC_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT 0x09f8 647 #define IOMUXC_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT 0x09fc 648 #define IOMUXC_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT 0x0a00 649 #define IOMUXC_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT 0x0a04 650 #define IOMUXC_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT 0x0a08 651 #define IOMUXC_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT 0x0a0c 652 #define IOMUXC_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT 0x0a10 653 #define IOMUXC_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT 0x0a14 654 #define IOMUXC_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT 0x0a18 655 #define IOMUXC_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT 0x0a1c 656 #define IOMUXC_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT 0x0a20 657 #define IOMUXC_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT 0x0a24 658 659 /* MUX & PAD Control */ 660 661 #define MUX_PIN_AUD3_BB_CK \ 662 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_CK, \ 663 IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_CK) 664 #define MUX_PIN_AUD3_BB_FS \ 665 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_FS, \ 666 IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_FS) 667 #define MUX_PIN_AUD3_BB_RXD \ 668 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_RXD, \ 669 IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_RXD) 670 #define MUX_PIN_AUD3_BB_TXD \ 671 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_TXD, \ 672 IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_TXD) 673 #define MUX_PIN_BOOT_MODE0 \ 674 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0) 675 #define MUX_PIN_BOOT_MODE1 \ 676 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1) 677 #define MUX_PIN_CKIL \ 678 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_CKIL) 679 #define MUX_PIN_CLK_SS \ 680 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_CLK_SS) 681 #define MUX_PIN_CSI1_D10 \ 682 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D10, \ 683 IOMUXC_SW_PAD_CTL_PAD_CSI1_D10) 684 #define MUX_PIN_CSI1_D11 \ 685 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D11, \ 686 IOMUXC_SW_PAD_CTL_PAD_CSI1_D11) 687 #define MUX_PIN_CSI1_D12 \ 688 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D12, \ 689 IOMUXC_SW_PAD_CTL_PAD_CSI1_D12) 690 #define MUX_PIN_CSI1_D13 \ 691 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D13, \ 692 IOMUXC_SW_PAD_CTL_PAD_CSI1_D13) 693 #define MUX_PIN_CSI1_D14 \ 694 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D14, \ 695 IOMUXC_SW_PAD_CTL_PAD_CSI1_D14) 696 #define MUX_PIN_CSI1_D15 \ 697 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D15, \ 698 IOMUXC_SW_PAD_CTL_PAD_CSI1_D15) 699 #define MUX_PIN_CSI1_D16 \ 700 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D16, \ 701 IOMUXC_SW_PAD_CTL_PAD_CSI1_D16) 702 #define MUX_PIN_CSI1_D17 \ 703 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D17, \ 704 IOMUXC_SW_PAD_CTL_PAD_CSI1_D17) 705 #define MUX_PIN_CSI1_D18 \ 706 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D18, \ 707 IOMUXC_SW_PAD_CTL_PAD_CSI1_D18) 708 #define MUX_PIN_CSI1_D19 \ 709 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D19, \ 710 IOMUXC_SW_PAD_CTL_PAD_CSI1_D19) 711 #define MUX_PIN_CSI1_D8 \ 712 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D8, \ 713 IOMUXC_SW_PAD_CTL_PAD_CSI1_D8) 714 #define MUX_PIN_CSI1_D9 \ 715 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D9, \ 716 IOMUXC_SW_PAD_CTL_PAD_CSI1_D9) 717 #define MUX_PIN_CSI1_HSYNC \ 718 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_HSYNC, \ 719 IOMUXC_SW_PAD_CTL_PAD_CSI1_HSYNC) 720 #define MUX_PIN_CSI1_MCLK \ 721 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_CSI1_MCLK) 722 #define MUX_PIN_CSI1_PIXCLK \ 723 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_CSI1_PIXCLK) 724 #define MUX_PIN_CSI1_VSYNC \ 725 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_VSYNC, \ 726 IOMUXC_SW_PAD_CTL_PAD_CSI1_VSYNC) 727 #define MUX_PIN_CSI2_D12 \ 728 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D12, \ 729 IOMUXC_SW_PAD_CTL_PAD_CSI2_D12) 730 #define MUX_PIN_CSI2_D13 \ 731 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D13, \ 732 IOMUXC_SW_PAD_CTL_PAD_CSI2_D13) 733 #define MUX_PIN_CSI2_D14 \ 734 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D14, \ 735 IOMUXC_SW_PAD_CTL_PAD_CSI2_D14) 736 #define MUX_PIN_CSI2_D15 \ 737 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D15, \ 738 IOMUXC_SW_PAD_CTL_PAD_CSI2_D15) 739 #define MUX_PIN_CSI2_D16 \ 740 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D16, \ 741 IOMUXC_SW_PAD_CTL_PAD_CSI2_D16) 742 #define MUX_PIN_CSI2_D17 \ 743 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D17, \ 744 IOMUXC_SW_PAD_CTL_PAD_CSI2_D17) 745 #define MUX_PIN_CSI2_D18 \ 746 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D18, \ 747 IOMUXC_SW_PAD_CTL_PAD_CSI2_D18) 748 #define MUX_PIN_CSI2_D19 \ 749 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D19, \ 750 IOMUXC_SW_PAD_CTL_PAD_CSI2_D19) 751 #define MUX_PIN_CSI2_HSYNC \ 752 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_HSYNC, \ 753 IOMUXC_SW_PAD_CTL_PAD_CSI2_HSYNC) 754 #define MUX_PIN_CSI2_PIXCLK \ 755 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_PIXCLK, \ 756 IOMUXC_SW_PAD_CTL_PAD_CSI2_PIXCLK) 757 #define MUX_PIN_CSI2_VSYNC \ 758 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_VSYNC, \ 759 IOMUXC_SW_PAD_CTL_PAD_CSI2_VSYNC) 760 #define MUX_PIN_CSPI1_MISO \ 761 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_MISO, \ 762 IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO) 763 #define MUX_PIN_CSPI1_MOSI \ 764 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_MOSI, \ 765 IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI) 766 #define MUX_PIN_CSPI1_RDY \ 767 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_RDY, \ 768 IOMUXC_SW_PAD_CTL_PAD_CSPI1_RDY) 769 #define MUX_PIN_CSPI1_SCLK \ 770 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_SCLK, \ 771 IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK) 772 #define MUX_PIN_CSPI1_SS0 \ 773 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS0, \ 774 IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0) 775 #define MUX_PIN_CSPI1_SS1 \ 776 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS1, \ 777 IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1) 778 #define MUX_PIN_DI1_D0_CS \ 779 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_D0_CS, \ 780 IOMUXC_SW_PAD_CTL_PAD_DI1_D0_CS) 781 #define MUX_PIN_DI1_D1_CS \ 782 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_D1_CS, \ 783 IOMUXC_SW_PAD_CTL_PAD_DI1_D1_CS) 784 #define MUX_PIN_DI1_DISP_CLK \ 785 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DI1_DISP_CLK) 786 #define MUX_PIN_DI1_PIN11 \ 787 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN11, \ 788 IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11) 789 #define MUX_PIN_DI1_PIN12 \ 790 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN12, \ 791 IOMUXC_SW_PAD_CTL_PAD_DI1_PIN12) 792 #define MUX_PIN_DI1_PIN13 \ 793 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN13, \ 794 IOMUXC_SW_PAD_CTL_PAD_DI1_PIN13) 795 #define MUX_PIN_DI1_PIN15 \ 796 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DI1_PIN15) 797 #define MUX_PIN_DI1_PIN2 \ 798 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN2, \ 799 IOMUXC_SW_PAD_CTL_PAD_DI1_PIN2) 800 #define MUX_PIN_DI1_PIN3 \ 801 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN3, \ 802 IOMUXC_SW_PAD_CTL_PAD_DI1_PIN3) 803 #define MUX_PIN_DI2_DISP_CLK \ 804 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI2_DISP_CLK, \ 805 IOMUXC_SW_PAD_CTL_PAD_DI2_DISP_CLK) 806 #define MUX_PIN_DI2_PIN2 \ 807 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI2_PIN2, \ 808 IOMUXC_SW_PAD_CTL_PAD_DI2_PIN2) 809 #define MUX_PIN_DI2_PIN3 \ 810 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI2_PIN3, \ 811 IOMUXC_SW_PAD_CTL_PAD_DI2_PIN3) 812 #define MUX_PIN_DI2_PIN4 \ 813 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI2_PIN4, \ 814 IOMUXC_SW_PAD_CTL_PAD_DI2_PIN4) 815 #define MUX_PIN_DISP1_DAT0 \ 816 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT0, \ 817 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT0) 818 #define MUX_PIN_DISP1_DAT1 \ 819 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT1, \ 820 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT1) 821 #define MUX_PIN_DISP1_DAT10 \ 822 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT10, \ 823 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT10) 824 #define MUX_PIN_DISP1_DAT11 \ 825 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT11, \ 826 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT11) 827 #define MUX_PIN_DISP1_DAT12 \ 828 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT12, \ 829 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT12) 830 #define MUX_PIN_DISP1_DAT13 \ 831 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT13, \ 832 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT13) 833 #define MUX_PIN_DISP1_DAT14 \ 834 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT14, \ 835 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT14) 836 #define MUX_PIN_DISP1_DAT15 \ 837 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT15, \ 838 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT15) 839 #define MUX_PIN_DISP1_DAT16 \ 840 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT16, \ 841 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT16) 842 #define MUX_PIN_DISP1_DAT17 \ 843 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT17, \ 844 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT17) 845 #define MUX_PIN_DISP1_DAT18 \ 846 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT18, \ 847 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT18) 848 #define MUX_PIN_DISP1_DAT19 \ 849 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT19, \ 850 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT19) 851 #define MUX_PIN_DISP1_DAT2 \ 852 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT2, \ 853 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT2) 854 #define MUX_PIN_DISP1_DAT20 \ 855 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT20, \ 856 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT20) 857 #define MUX_PIN_DISP1_DAT21 \ 858 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT21, \ 859 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT21) 860 #define MUX_PIN_DISP1_DAT22 \ 861 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT22, \ 862 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT22) 863 #define MUX_PIN_DISP1_DAT23 \ 864 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT23, \ 865 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT23) 866 #define MUX_PIN_DISP1_DAT3 \ 867 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT3, \ 868 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT3) 869 #define MUX_PIN_DISP1_DAT4 \ 870 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT4, \ 871 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT4) 872 #define MUX_PIN_DISP1_DAT5 \ 873 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT5, \ 874 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT5) 875 #define MUX_PIN_DISP1_DAT6 \ 876 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT6, \ 877 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT6) 878 #define MUX_PIN_DISP1_DAT7 \ 879 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT7, \ 880 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT7) 881 #define MUX_PIN_DISP1_DAT8 \ 882 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT8, \ 883 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT8) 884 #define MUX_PIN_DISP1_DAT9 \ 885 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT9, \ 886 IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT9) 887 #define MUX_PIN_DISP2_DAT0 \ 888 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT0, \ 889 IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT0) 890 #define MUX_PIN_DISP2_DAT1 \ 891 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT1, \ 892 IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT1) 893 #define MUX_PIN_DISP2_DAT10 \ 894 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT10, \ 895 IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT10) 896 #define MUX_PIN_DISP2_DAT11 \ 897 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT11, \ 898 IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT11) 899 #define MUX_PIN_DISP2_DAT12 \ 900 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT12, \ 901 IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT12) 902 #define MUX_PIN_DISP2_DAT13 \ 903 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT13, \ 904 IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT13) 905 #define MUX_PIN_DISP2_DAT14 \ 906 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT14, \ 907 IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT14) 908 #define MUX_PIN_DISP2_DAT15 \ 909 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT15, \ 910 IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT15) 911 #define MUX_PIN_DISP2_DAT2 \ 912 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT2, \ 913 IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT2) 914 #define MUX_PIN_DISP2_DAT3 \ 915 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT3, \ 916 IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT3) 917 #define MUX_PIN_DISP2_DAT4 \ 918 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT4, \ 919 IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT4) 920 #define MUX_PIN_DISP2_DAT5 \ 921 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT5, \ 922 IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT5) 923 #define MUX_PIN_DISP2_DAT6 \ 924 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT6, \ 925 IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT6) 926 #define MUX_PIN_DISP2_DAT7 \ 927 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT7, \ 928 IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT7) 929 #define MUX_PIN_DISP2_DAT8 \ 930 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT8, \ 931 IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT8) 932 #define MUX_PIN_DISP2_DAT9 \ 933 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT9, \ 934 IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT9) 935 #define MUX_PIN_DISPB2_SER_CLK \ 936 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_CLK, \ 937 IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_CLK) 938 #define MUX_PIN_DISPB2_SER_DIN \ 939 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_DIN, \ 940 IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_DIN) 941 #define MUX_PIN_DISPB2_SER_DIO \ 942 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_DIO, \ 943 IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_DIO) 944 #define MUX_PIN_DISPB2_SER_RS \ 945 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_RS, \ 946 IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_RS) 947 #define MUX_PIN_DI_GP1 \ 948 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP1, \ 949 IOMUXC_SW_PAD_CTL_PAD_DI_GP1) 950 #define MUX_PIN_DI_GP2 \ 951 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP2, \ 952 IOMUXC_SW_PAD_CTL_PAD_DI_GP2) 953 #define MUX_PIN_DI_GP3 \ 954 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP3, \ 955 IOMUXC_SW_PAD_CTL_PAD_DI_GP3) 956 #define MUX_PIN_DI_GP4 \ 957 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP4, \ 958 IOMUXC_SW_PAD_CTL_PAD_DI_GP4) 959 #define MUX_PIN_DRAM_CAS \ 960 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS) 961 #define MUX_PIN_DRAM_CS0 \ 962 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0) 963 #define MUX_PIN_DRAM_CS1 \ 964 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DRAM_CS1, \ 965 IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1) 966 #define MUX_PIN_DRAM_DQM0 \ 967 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0) 968 #define MUX_PIN_DRAM_DQM1 \ 969 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1) 970 #define MUX_PIN_DRAM_DQM2 \ 971 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2) 972 #define MUX_PIN_DRAM_DQM3 \ 973 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3) 974 #define MUX_PIN_DRAM_RAS \ 975 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS) 976 #define MUX_PIN_DRAM_SDCKE0 \ 977 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0) 978 #define MUX_PIN_DRAM_SDCKE1 \ 979 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1) 980 #define MUX_PIN_DRAM_SDCLK \ 981 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK) 982 #define MUX_PIN_DRAM_SDQS0 \ 983 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0) 984 #define MUX_PIN_DRAM_SDQS1 \ 985 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1) 986 #define MUX_PIN_DRAM_SDQS2 \ 987 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2) 988 #define MUX_PIN_DRAM_SDQS3 \ 989 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3) 990 #define MUX_PIN_DRAM_SDWE \ 991 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE) 992 #define MUX_PIN_EIM_A16 \ 993 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A16, \ 994 IOMUXC_SW_PAD_CTL_PAD_EIM_A16) 995 #define MUX_PIN_EIM_A17 \ 996 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A17, \ 997 IOMUXC_SW_PAD_CTL_PAD_EIM_A17) 998 #define MUX_PIN_EIM_A18 \ 999 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A18, \ 1000 IOMUXC_SW_PAD_CTL_PAD_EIM_A18) 1001 #define MUX_PIN_EIM_A19 \ 1002 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A19, \ 1003 IOMUXC_SW_PAD_CTL_PAD_EIM_A19) 1004 #define MUX_PIN_EIM_A20 \ 1005 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A20, \ 1006 IOMUXC_SW_PAD_CTL_PAD_EIM_A20) 1007 #define MUX_PIN_EIM_A21 \ 1008 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A21, \ 1009 IOMUXC_SW_PAD_CTL_PAD_EIM_A21) 1010 #define MUX_PIN_EIM_A22 \ 1011 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A22, \ 1012 IOMUXC_SW_PAD_CTL_PAD_EIM_A22) 1013 #define MUX_PIN_EIM_A23 \ 1014 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A23, \ 1015 IOMUXC_SW_PAD_CTL_PAD_EIM_A23) 1016 #define MUX_PIN_EIM_A24 \ 1017 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A24, \ 1018 IOMUXC_SW_PAD_CTL_PAD_EIM_A24) 1019 #define MUX_PIN_EIM_A25 \ 1020 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A25, \ 1021 IOMUXC_SW_PAD_CTL_PAD_EIM_A25) 1022 #define MUX_PIN_EIM_A26 \ 1023 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A26, \ 1024 IOMUXC_SW_PAD_CTL_PAD_EIM_A26) 1025 #define MUX_PIN_EIM_A27 \ 1026 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A27, \ 1027 IOMUXC_SW_PAD_CTL_PAD_EIM_A27) 1028 #define MUX_PIN_EIM_BCLK \ 1029 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK) 1030 #define MUX_PIN_EIM_CRE \ 1031 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_CRE, \ 1032 IOMUXC_SW_PAD_CTL_PAD_EIM_CRE) 1033 #define MUX_PIN_EIM_CS0 \ 1034 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_CS0, \ 1035 IOMUXC_SW_PAD_CTL_PAD_EIM_CS0) 1036 #define MUX_PIN_EIM_CS1 \ 1037 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_CS1, \ 1038 IOMUXC_SW_PAD_CTL_PAD_EIM_CS1) 1039 #define MUX_PIN_EIM_CS2 \ 1040 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_CS2, \ 1041 IOMUXC_SW_PAD_CTL_PAD_EIM_CS2) 1042 #define MUX_PIN_EIM_CS3 \ 1043 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_CS3, \ 1044 IOMUXC_SW_PAD_CTL_PAD_EIM_CS3) 1045 #define MUX_PIN_EIM_CS4 \ 1046 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_CS4, \ 1047 IOMUXC_SW_PAD_CTL_PAD_EIM_CS4) 1048 #define MUX_PIN_EIM_CS5 \ 1049 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_CS5, \ 1050 IOMUXC_SW_PAD_CTL_PAD_EIM_CS5) 1051 #define MUX_PIN_EIM_D16 \ 1052 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D16, \ 1053 IOMUXC_SW_PAD_CTL_PAD_EIM_D16) 1054 #define MUX_PIN_EIM_D17 \ 1055 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D17, \ 1056 IOMUXC_SW_PAD_CTL_PAD_EIM_D17) 1057 #define MUX_PIN_EIM_D18 \ 1058 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D18, \ 1059 IOMUXC_SW_PAD_CTL_PAD_EIM_D18) 1060 #define MUX_PIN_EIM_D19 \ 1061 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D19, \ 1062 IOMUXC_SW_PAD_CTL_PAD_EIM_D19) 1063 #define MUX_PIN_EIM_D20 \ 1064 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D20, \ 1065 IOMUXC_SW_PAD_CTL_PAD_EIM_D20) 1066 #define MUX_PIN_EIM_D21 \ 1067 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D21, \ 1068 IOMUXC_SW_PAD_CTL_PAD_EIM_D21) 1069 #define MUX_PIN_EIM_D22 \ 1070 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D22, \ 1071 IOMUXC_SW_PAD_CTL_PAD_EIM_D22) 1072 #define MUX_PIN_EIM_D23 \ 1073 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D23, \ 1074 IOMUXC_SW_PAD_CTL_PAD_EIM_D23) 1075 #define MUX_PIN_EIM_D24 \ 1076 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D24, \ 1077 IOMUXC_SW_PAD_CTL_PAD_EIM_D24) 1078 #define MUX_PIN_EIM_D25 \ 1079 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D25, \ 1080 IOMUXC_SW_PAD_CTL_PAD_EIM_D25) 1081 #define MUX_PIN_EIM_D26 \ 1082 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D26, \ 1083 IOMUXC_SW_PAD_CTL_PAD_EIM_D26) 1084 #define MUX_PIN_EIM_D27 \ 1085 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D27, \ 1086 IOMUXC_SW_PAD_CTL_PAD_EIM_D27) 1087 #define MUX_PIN_EIM_D28 \ 1088 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D28, \ 1089 IOMUXC_SW_PAD_CTL_PAD_EIM_D28) 1090 #define MUX_PIN_EIM_D29 \ 1091 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D29, \ 1092 IOMUXC_SW_PAD_CTL_PAD_EIM_D29) 1093 #define MUX_PIN_EIM_D30 \ 1094 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D30, \ 1095 IOMUXC_SW_PAD_CTL_PAD_EIM_D30) 1096 #define MUX_PIN_EIM_D31 \ 1097 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D31, \ 1098 IOMUXC_SW_PAD_CTL_PAD_EIM_D31) 1099 #define MUX_PIN_EIM_DA0 \ 1100 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA0, \ 1101 IOMUX_PAD_NONE) 1102 #define MUX_PIN_EIM_DA1 \ 1103 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA1, \ 1104 IOMUX_PAD_NONE) 1105 #define MUX_PIN_EIM_DA10 \ 1106 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA10, \ 1107 IOMUX_PAD_NONE) 1108 #define MUX_PIN_EIM_DA11 \ 1109 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA11, \ 1110 IOMUX_PAD_NONE) 1111 #define MUX_PIN_EIM_DA12 \ 1112 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA12, \ 1113 IOMUX_PAD_NONE) 1114 #define MUX_PIN_EIM_DA13 \ 1115 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA13, \ 1116 IOMUX_PAD_NONE) 1117 #define MUX_PIN_EIM_DA14 \ 1118 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA14, \ 1119 IOMUX_PAD_NONE) 1120 #define MUX_PIN_EIM_DA15 \ 1121 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA15, \ 1122 IOMUX_PAD_NONE) 1123 #define MUX_PIN_EIM_DA2 \ 1124 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA2, \ 1125 IOMUX_PAD_NONE) 1126 #define MUX_PIN_EIM_DA3 \ 1127 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA3, \ 1128 IOMUX_PAD_NONE) 1129 #define MUX_PIN_EIM_DA4 \ 1130 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA4, \ 1131 IOMUX_PAD_NONE) 1132 #define MUX_PIN_EIM_DA5 \ 1133 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA5, \ 1134 IOMUX_PAD_NONE) 1135 #define MUX_PIN_EIM_DA6 \ 1136 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA6, \ 1137 IOMUX_PAD_NONE) 1138 #define MUX_PIN_EIM_DA7 \ 1139 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA7, \ 1140 IOMUX_PAD_NONE) 1141 #define MUX_PIN_EIM_DA8 \ 1142 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA8, \ 1143 IOMUX_PAD_NONE) 1144 #define MUX_PIN_EIM_DA9 \ 1145 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA9, \ 1146 IOMUX_PAD_NONE) 1147 #define MUX_PIN_EIM_DTACK \ 1148 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DTACK, \ 1149 IOMUXC_SW_PAD_CTL_PAD_EIM_DTACK) 1150 #define MUX_PIN_EIM_EB0 \ 1151 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_EB0, \ 1152 IOMUXC_SW_PAD_CTL_PAD_EIM_EB0) 1153 #define MUX_PIN_EIM_EB1 \ 1154 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_EB1, \ 1155 IOMUXC_SW_PAD_CTL_PAD_EIM_EB1) 1156 #define MUX_PIN_EIM_EB2 \ 1157 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_EB2, \ 1158 IOMUXC_SW_PAD_CTL_PAD_EIM_EB2) 1159 #define MUX_PIN_EIM_EB3 \ 1160 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_EB3, \ 1161 IOMUXC_SW_PAD_CTL_PAD_EIM_EB3) 1162 #define MUX_PIN_EIM_LBA \ 1163 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_LBA, \ 1164 IOMUXC_SW_PAD_CTL_PAD_EIM_LBA) 1165 #define MUX_PIN_EIM_OE \ 1166 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_OE, \ 1167 IOMUXC_SW_PAD_CTL_PAD_EIM_OE) 1168 #define MUX_PIN_EIM_RW \ 1169 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_EIM_RW) 1170 #define MUX_PIN_EIM_SDBA2 \ 1171 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_EIM_SDBA2) 1172 #define MUX_PIN_EIM_SDODT0 \ 1173 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT0) 1174 #define MUX_PIN_EIM_SDODT1 \ 1175 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT1) 1176 #define MUX_PIN_EIM_WAIT \ 1177 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT) 1178 #define MUX_PIN_GPIO1_0 \ 1179 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_0, \ 1180 IOMUXC_SW_PAD_CTL_PAD_GPIO1_0) 1181 #define MUX_PIN_GPIO1_1 \ 1182 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_1, \ 1183 IOMUXC_SW_PAD_CTL_PAD_GPIO1_1) 1184 #define MUX_PIN_GPIO1_2 \ 1185 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_2, \ 1186 IOMUXC_SW_PAD_CTL_PAD_GPIO1_2) 1187 #define MUX_PIN_GPIO1_3 \ 1188 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_3, \ 1189 IOMUXC_SW_PAD_CTL_PAD_GPIO1_3) 1190 #define MUX_PIN_GPIO1_4 \ 1191 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_4, \ 1192 IOMUXC_SW_PAD_CTL_PAD_GPIO1_4) 1193 #define MUX_PIN_GPIO1_5 \ 1194 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_5, \ 1195 IOMUXC_SW_PAD_CTL_PAD_GPIO1_5) 1196 #define MUX_PIN_GPIO1_6 \ 1197 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_6, \ 1198 IOMUXC_SW_PAD_CTL_PAD_GPIO1_6) 1199 #define MUX_PIN_GPIO1_7 \ 1200 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_7, \ 1201 IOMUXC_SW_PAD_CTL_PAD_GPIO1_7) 1202 #define MUX_PIN_GPIO1_8 \ 1203 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_8, \ 1204 IOMUXC_SW_PAD_CTL_PAD_GPIO1_8) 1205 #define MUX_PIN_GPIO1_9 \ 1206 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_9, \ 1207 IOMUXC_SW_PAD_CTL_PAD_GPIO1_9) 1208 #define MUX_PIN_GPIO_NAND \ 1209 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO_NAND, \ 1210 IOMUXC_SW_PAD_CTL_PAD_GPIO_NAND) 1211 #define MUX_PIN_I2C1_CLK \ 1212 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_I2C1_CLK, \ 1213 IOMUXC_SW_PAD_CTL_PAD_I2C1_CLK) 1214 #define MUX_PIN_I2C1_DAT \ 1215 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_I2C1_DAT, \ 1216 IOMUXC_SW_PAD_CTL_PAD_I2C1_DAT) 1217 #define MUX_PIN_JTAG_DE_B \ 1218 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_JTAG_DE_B, \ 1219 IOMUX_PAD_NONE) 1220 #define MUX_PIN_JTAG_MOD \ 1221 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD) 1222 #define MUX_PIN_JTAG_TCK \ 1223 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK) 1224 #define MUX_PIN_JTAG_TDI \ 1225 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI) 1226 #define MUX_PIN_JTAG_TMS \ 1227 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS) 1228 #define MUX_PIN_JTAG_TRSTB \ 1229 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB) 1230 #define MUX_PIN_KEY_COL0 \ 1231 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_COL0, \ 1232 IOMUXC_SW_PAD_CTL_PAD_KEY_COL0) 1233 #define MUX_PIN_KEY_COL1 \ 1234 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_COL1, \ 1235 IOMUXC_SW_PAD_CTL_PAD_KEY_COL1) 1236 #define MUX_PIN_KEY_COL2 \ 1237 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_COL2, \ 1238 IOMUXC_SW_PAD_CTL_PAD_KEY_COL2) 1239 #define MUX_PIN_KEY_COL3 \ 1240 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_COL3, \ 1241 IOMUXC_SW_PAD_CTL_PAD_KEY_COL3) 1242 #define MUX_PIN_KEY_COL4 \ 1243 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_COL4, \ 1244 IOMUXC_SW_PAD_CTL_PAD_KEY_COL4) 1245 #define MUX_PIN_KEY_COL5 \ 1246 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_COL5, \ 1247 IOMUXC_SW_PAD_CTL_PAD_KEY_COL5) 1248 #define MUX_PIN_KEY_ROW0 \ 1249 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0, \ 1250 IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0) 1251 #define MUX_PIN_KEY_ROW1 \ 1252 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1, \ 1253 IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1) 1254 #define MUX_PIN_KEY_ROW2 \ 1255 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2, \ 1256 IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2) 1257 #define MUX_PIN_KEY_ROW3 \ 1258 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3, \ 1259 IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3) 1260 #define MUX_PIN_NANDF_ALE \ 1261 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE, \ 1262 IOMUXC_SW_PAD_CTL_PAD_NANDF_ALE) 1263 #define MUX_PIN_NANDF_CLE \ 1264 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE, \ 1265 IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE) 1266 #define MUX_PIN_NANDF_CS0 \ 1267 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS0, \ 1268 IOMUXC_SW_PAD_CTL_PAD_NANDF_CS0) 1269 #define MUX_PIN_NANDF_CS1 \ 1270 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS1, \ 1271 IOMUXC_SW_PAD_CTL_PAD_NANDF_CS1) 1272 #define MUX_PIN_NANDF_CS2 \ 1273 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2, \ 1274 IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2) 1275 #define MUX_PIN_NANDF_CS3 \ 1276 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3, \ 1277 IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3) 1278 #define MUX_PIN_NANDF_CS4 \ 1279 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4, \ 1280 IOMUXC_SW_PAD_CTL_PAD_NANDF_CS4) 1281 #define MUX_PIN_NANDF_CS5 \ 1282 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5, \ 1283 IOMUXC_SW_PAD_CTL_PAD_NANDF_CS5) 1284 #define MUX_PIN_NANDF_CS6 \ 1285 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6, \ 1286 IOMUXC_SW_PAD_CTL_PAD_NANDF_CS6) 1287 #define MUX_PIN_NANDF_CS7 \ 1288 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS7, \ 1289 IOMUXC_SW_PAD_CTL_PAD_NANDF_CS7) 1290 #define MUX_PIN_NANDF_D0 \ 1291 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D0, \ 1292 IOMUXC_SW_PAD_CTL_PAD_NANDF_D0) 1293 #define MUX_PIN_NANDF_D1 \ 1294 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D1, \ 1295 IOMUXC_SW_PAD_CTL_PAD_NANDF_D1) 1296 #define MUX_PIN_NANDF_D10 \ 1297 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D10, \ 1298 IOMUXC_SW_PAD_CTL_PAD_NANDF_D10) 1299 #define MUX_PIN_NANDF_D11 \ 1300 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D11, \ 1301 IOMUXC_SW_PAD_CTL_PAD_NANDF_D11) 1302 #define MUX_PIN_NANDF_D12 \ 1303 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D12, \ 1304 IOMUXC_SW_PAD_CTL_PAD_NANDF_D12) 1305 #define MUX_PIN_NANDF_D13 \ 1306 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D13, \ 1307 IOMUXC_SW_PAD_CTL_PAD_NANDF_D13) 1308 #define MUX_PIN_NANDF_D14 \ 1309 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D14, \ 1310 IOMUXC_SW_PAD_CTL_PAD_NANDF_D14) 1311 #define MUX_PIN_NANDF_D15 \ 1312 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D15, \ 1313 IOMUXC_SW_PAD_CTL_PAD_NANDF_D15) 1314 #define MUX_PIN_NANDF_D2 \ 1315 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D2, \ 1316 IOMUXC_SW_PAD_CTL_PAD_NANDF_D2) 1317 #define MUX_PIN_NANDF_D3 \ 1318 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D3, \ 1319 IOMUXC_SW_PAD_CTL_PAD_NANDF_D3) 1320 #define MUX_PIN_NANDF_D4 \ 1321 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D4, \ 1322 IOMUXC_SW_PAD_CTL_PAD_NANDF_D4) 1323 #define MUX_PIN_NANDF_D5 \ 1324 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D5, \ 1325 IOMUXC_SW_PAD_CTL_PAD_NANDF_D5) 1326 #define MUX_PIN_NANDF_D6 \ 1327 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D6, \ 1328 IOMUXC_SW_PAD_CTL_PAD_NANDF_D6) 1329 #define MUX_PIN_NANDF_D7 \ 1330 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D7, \ 1331 IOMUXC_SW_PAD_CTL_PAD_NANDF_D7) 1332 #define MUX_PIN_NANDF_D8 \ 1333 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D8, \ 1334 IOMUXC_SW_PAD_CTL_PAD_NANDF_D8) 1335 #define MUX_PIN_NANDF_D9 \ 1336 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D9, \ 1337 IOMUXC_SW_PAD_CTL_PAD_NANDF_D9) 1338 #define MUX_PIN_NANDF_RB0 \ 1339 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0, \ 1340 IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0) 1341 #define MUX_PIN_NANDF_RB1 \ 1342 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_RB1, \ 1343 IOMUXC_SW_PAD_CTL_PAD_NANDF_RB1) 1344 #define MUX_PIN_NANDF_RB2 \ 1345 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_RB2, \ 1346 IOMUXC_SW_PAD_CTL_PAD_NANDF_RB2) 1347 #define MUX_PIN_NANDF_RB3 \ 1348 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_RB3, \ 1349 IOMUXC_SW_PAD_CTL_PAD_NANDF_RB3) 1350 #define MUX_PIN_NANDF_RDY_INT \ 1351 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_RDY_INT, \ 1352 IOMUXC_SW_PAD_CTL_PAD_NANDF_RDY_INT) 1353 #define MUX_PIN_NANDF_RE_B \ 1354 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_RE_B, \ 1355 IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B) 1356 #define MUX_PIN_NANDF_WE_B \ 1357 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_WE_B, \ 1358 IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B) 1359 #define MUX_PIN_NANDF_WP_B \ 1360 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B, \ 1361 IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B) 1362 #define MUX_PIN_OWIRE_LINE \ 1363 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_OWIRE_LINE, \ 1364 IOMUXC_SW_PAD_CTL_PAD_OWIRE_LINE) 1365 #define MUX_PIN_PMIC_INT_REQ \ 1366 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_PMIC_INT_REQ, \ 1367 IOMUXC_SW_PAD_CTL_PAD_PMIC_INT_REQ) 1368 #define MUX_PIN_PMIC_ON_REQ \ 1369 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ) 1370 #define MUX_PIN_PMIC_RDY \ 1371 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_PMIC_RDY) 1372 #define MUX_PIN_PMIC_STBY_REQ \ 1373 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ) 1374 #define MUX_PIN_POR_B \ 1375 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_POR_B) 1376 #define MUX_PIN_RESET_IN_B \ 1377 IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_RESET_IN_B) 1378 #define MUX_PIN_SD1_CLK \ 1379 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD1_CLK, \ 1380 IOMUXC_SW_PAD_CTL_PAD_SD1_CLK) 1381 #define MUX_PIN_SD1_CMD \ 1382 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD1_CMD, \ 1383 IOMUXC_SW_PAD_CTL_PAD_SD1_CMD) 1384 #define MUX_PIN_SD1_DATA0 \ 1385 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0, \ 1386 IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0) 1387 #define MUX_PIN_SD1_DATA1 \ 1388 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1, \ 1389 IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1) 1390 #define MUX_PIN_SD1_DATA2 \ 1391 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2, \ 1392 IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2) 1393 #define MUX_PIN_SD1_DATA3 \ 1394 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3, \ 1395 IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3) 1396 #define MUX_PIN_SD2_CLK \ 1397 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD2_CLK, \ 1398 IOMUXC_SW_PAD_CTL_PAD_SD2_CLK) 1399 #define MUX_PIN_SD2_CMD \ 1400 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD2_CMD, \ 1401 IOMUXC_SW_PAD_CTL_PAD_SD2_CMD) 1402 #define MUX_PIN_SD2_DATA0 \ 1403 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0, \ 1404 IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0) 1405 #define MUX_PIN_SD2_DATA1 \ 1406 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1, \ 1407 IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1) 1408 #define MUX_PIN_SD2_DATA2 \ 1409 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2, \ 1410 IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2) 1411 #define MUX_PIN_SD2_DATA3 \ 1412 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3, \ 1413 IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3) 1414 #define MUX_PIN_UART1_CTS \ 1415 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART1_CTS, \ 1416 IOMUXC_SW_PAD_CTL_PAD_UART1_CTS) 1417 #define MUX_PIN_UART1_RTS \ 1418 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART1_RTS, \ 1419 IOMUXC_SW_PAD_CTL_PAD_UART1_RTS) 1420 #define MUX_PIN_UART1_RXD \ 1421 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART1_RXD, \ 1422 IOMUXC_SW_PAD_CTL_PAD_UART1_RXD) 1423 #define MUX_PIN_UART1_TXD \ 1424 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART1_TXD, \ 1425 IOMUXC_SW_PAD_CTL_PAD_UART1_TXD) 1426 #define MUX_PIN_UART2_RXD \ 1427 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART2_RXD, \ 1428 IOMUXC_SW_PAD_CTL_PAD_UART2_RXD) 1429 #define MUX_PIN_UART2_TXD \ 1430 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART2_TXD, \ 1431 IOMUXC_SW_PAD_CTL_PAD_UART2_TXD) 1432 #define MUX_PIN_UART3_RXD \ 1433 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART3_RXD, \ 1434 IOMUXC_SW_PAD_CTL_PAD_UART3_RXD) 1435 #define MUX_PIN_UART3_TXD \ 1436 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART3_TXD, \ 1437 IOMUXC_SW_PAD_CTL_PAD_UART3_TXD) 1438 #define MUX_PIN_USBH1_CLK \ 1439 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_CLK, \ 1440 IOMUXC_SW_PAD_CTL_PAD_USBH1_CLK) 1441 #define MUX_PIN_USBH1_DATA0 \ 1442 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA0, \ 1443 IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA0) 1444 #define MUX_PIN_USBH1_DATA1 \ 1445 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA1, \ 1446 IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA1) 1447 #define MUX_PIN_USBH1_DATA2 \ 1448 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA2, \ 1449 IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA2) 1450 #define MUX_PIN_USBH1_DATA3 \ 1451 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA3, \ 1452 IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA3) 1453 #define MUX_PIN_USBH1_DATA4 \ 1454 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA4, \ 1455 IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA4) 1456 #define MUX_PIN_USBH1_DATA5 \ 1457 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA5, \ 1458 IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA5) 1459 #define MUX_PIN_USBH1_DATA6 \ 1460 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA6, \ 1461 IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA6) 1462 #define MUX_PIN_USBH1_DATA7 \ 1463 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA7, \ 1464 IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA7) 1465 #define MUX_PIN_USBH1_DIR \ 1466 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DIR, \ 1467 IOMUXC_SW_PAD_CTL_PAD_USBH1_DIR) 1468 #define MUX_PIN_USBH1_NXT \ 1469 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_NXT, \ 1470 IOMUXC_SW_PAD_CTL_PAD_USBH1_NXT) 1471 #define MUX_PIN_USBH1_STP \ 1472 IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_STP, \ 1473 IOMUXC_SW_PAD_CTL_PAD_USBH1_STP) 1474 1475 /* INPUT Control */ 1476 1477 #define MUX_IN_AUDMUX_P4_INPUT_DA_AMX \ 1478 IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT 1479 #define MUX_IN_AUDMUX_P4_INPUT_DB_AMX \ 1480 IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT 1481 #define MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX \ 1482 IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT 1483 #define MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX \ 1484 IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT 1485 #define MUX_IN_AUDMUX_P5_INPUT_DA_AMX \ 1486 IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT 1487 #define MUX_IN_AUDMUX_P5_INPUT_DB_AMX \ 1488 IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT 1489 #define MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX \ 1490 IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT 1491 #define MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX \ 1492 IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT 1493 #define MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX \ 1494 IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT 1495 #define MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX \ 1496 IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT 1497 #define MUX_IN_AUDMUX_P6_INPUT_DA_AMX \ 1498 IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT 1499 #define MUX_IN_AUDMUX_P6_INPUT_DB_AMX \ 1500 IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT 1501 #define MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX \ 1502 IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT 1503 #define MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX \ 1504 IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT 1505 #define MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX \ 1506 IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT 1507 #define MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX \ 1508 IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT 1509 #define MUX_IN_CCM_IPP_DI0_CLK \ 1510 IOMUXC_CCM_IPP_DI0_CLK_SELECT_INPUT 1511 #define MUX_IN_CCM_IPP_DI1_CLK \ 1512 IOMUXC_CCM_IPP_DI1_CLK_SELECT_INPUT 1513 #define MUX_IN_CCM_PLL1_BYPASS_CLK \ 1514 IOMUXC_CCM_PLL1_BYPASS_CLK_SELECT_INPUT 1515 #define MUX_IN_CCM_PLL2_BYPASS_CLK \ 1516 IOMUXC_CCM_PLL2_BYPASS_CLK_SELECT_INPUT 1517 #define MUX_IN_CSPI_IPP_CSPI_CLK_IN \ 1518 IOMUXC_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT 1519 #define MUX_IN_CSPI_IPP_IND_MISO \ 1520 IOMUXC_CSPI_IPP_IND_MISO_SELECT_INPUT 1521 #define MUX_IN_CSPI_IPP_IND_MOSI \ 1522 IOMUXC_CSPI_IPP_IND_MOSI_SELECT_INPUT 1523 #define MUX_IN_CSPI_IPP_IND_SS1_B \ 1524 IOMUXC_CSPI_IPP_IND_SS1_B_SELECT_INPUT 1525 #define MUX_IN_CSPI_IPP_IND_SS2_B \ 1526 IOMUXC_CSPI_IPP_IND_SS2_B_SELECT_INPUT 1527 #define MUX_IN_CSPI_IPP_IND_SS3_B \ 1528 IOMUXC_CSPI_IPP_IND_SS3_B_SELECT_INPUT 1529 #define MUX_IN_DPLLIP1_L1T_TOG_EN \ 1530 IOMUXC_DPLLIP1_L1T_TOG_EN_SELECT_INPUT 1531 #define MUX_IN_ECSPI2_IPP_IND_SS_B_1 \ 1532 IOMUXC_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT 1533 #define MUX_IN_ECSPI2_IPP_IND_SS_B_3 \ 1534 IOMUXC_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT 1535 #define MUX_IN_EMI_IPP_IND_RDY_INT \ 1536 IOMUXC_EMI_IPP_IND_RDY_INT_SELECT_INPUT 1537 #define MUX_IN_ESDHC3_IPP_DAT0_IN \ 1538 IOMUXC_ESDHC3_IPP_DAT0_IN_SELECT_INPUT 1539 #define MUX_IN_ESDHC3_IPP_DAT1_IN \ 1540 IOMUXC_ESDHC3_IPP_DAT1_IN_SELECT_INPUT 1541 #define MUX_IN_ESDHC3_IPP_DAT2_IN \ 1542 IOMUXC_ESDHC3_IPP_DAT2_IN_SELECT_INPUT 1543 #define MUX_IN_ESDHC3_IPP_DAT3_IN \ 1544 IOMUXC_ESDHC3_IPP_DAT3_IN_SELECT_INPUT 1545 #define MUX_IN_FEC_FEC_COL \ 1546 IOMUXC_FEC_FEC_COL_SELECT_INPUT 1547 #define MUX_IN_FEC_FEC_CRS \ 1548 IOMUXC_FEC_FEC_CRS_SELECT_INPUT 1549 #define MUX_IN_FEC_FEC_MDI \ 1550 IOMUXC_FEC_FEC_MDI_SELECT_INPUT 1551 #define MUX_IN_FEC_FEC_RDATA_0 \ 1552 IOMUXC_FEC_FEC_RDATA_0_SELECT_INPUT 1553 #define MUX_IN_FEC_FEC_RDATA_1 \ 1554 IOMUXC_FEC_FEC_RDATA_1_SELECT_INPUT 1555 #define MUX_IN_FEC_FEC_RDATA_2 \ 1556 IOMUXC_FEC_FEC_RDATA_2_SELECT_INPUT 1557 #define MUX_IN_FEC_FEC_RDATA_3 \ 1558 IOMUXC_FEC_FEC_RDATA_3_SELECT_INPUT 1559 #define MUX_IN_FEC_FEC_RX_CLK \ 1560 IOMUXC_FEC_FEC_RX_CLK_SELECT_INPUT 1561 #define MUX_IN_FEC_FEC_RX_DV \ 1562 IOMUXC_FEC_FEC_RX_DV_SELECT_INPUT 1563 #define MUX_IN_FEC_FEC_RX_ER \ 1564 IOMUXC_FEC_FEC_RX_ER_SELECT_INPUT 1565 #define MUX_IN_FEC_FEC_TX_CLK \ 1566 IOMUXC_FEC_FEC_TX_CLK_SELECT_INPUT 1567 #define MUX_IN_GPIO3_IPP_IND_G_IN_1 \ 1568 IOMUXC_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT 1569 #define MUX_IN_GPIO3_IPP_IND_G_IN_2 \ 1570 IOMUXC_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT 1571 #define MUX_IN_GPIO3_IPP_IND_G_IN_3 \ 1572 IOMUXC_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT 1573 #define MUX_IN_GPIO3_IPP_IND_G_IN_4 \ 1574 IOMUXC_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT 1575 #define MUX_IN_GPIO3_IPP_IND_G_IN_5 \ 1576 IOMUXC_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT 1577 #define MUX_IN_GPIO3_IPP_IND_G_IN_6 \ 1578 IOMUXC_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT 1579 #define MUX_IN_GPIO3_IPP_IND_G_IN_7 \ 1580 IOMUXC_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT 1581 #define MUX_IN_GPIO3_IPP_IND_G_IN_8 \ 1582 IOMUXC_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT 1583 #define MUX_IN_GPIO3_IPP_IND_G_IN_12 \ 1584 IOMUXC_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT 1585 #define MUX_IN_HSC_MIPI_MIX_PAR0_VSYNC \ 1586 IOMUXC_HSC_MIPI_MIX_PAR0_VSYNC_SELECT_INPUT 1587 #define MUX_IN_HSC_MIPI_MIX_PAR1_DI_WAIT \ 1588 IOMUXC_HSC_MIPI_MIX_PAR1_DI_WAIT_SELECT_INPUT 1589 #define MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG \ 1590 IOMUXC_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT 1591 #define MUX_IN_I2C1_IPP_SCL_IN \ 1592 IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT 1593 #define MUX_IN_I2C1_IPP_SDA_IN \ 1594 IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT 1595 #define MUX_IN_I2C2_IPP_SCL_IN \ 1596 IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT 1597 #define MUX_IN_I2C2_IPP_SDA_IN \ 1598 IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT 1599 #define MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D \ 1600 IOMUXC_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT 1601 #define MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D \ 1602 IOMUXC_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT 1603 #define MUX_IN_KPP_IPP_IND_COL_6 \ 1604 IOMUXC_KPP_IPP_IND_COL_6_SELECT_INPUT 1605 #define MUX_IN_KPP_IPP_IND_COL_7 \ 1606 IOMUXC_KPP_IPP_IND_COL_7_SELECT_INPUT 1607 #define MUX_IN_KPP_IPP_IND_ROW_4 \ 1608 IOMUXC_KPP_IPP_IND_ROW_4_SELECT_INPUT 1609 #define MUX_IN_KPP_IPP_IND_ROW_5 \ 1610 IOMUXC_KPP_IPP_IND_ROW_5_SELECT_INPUT 1611 #define MUX_IN_KPP_IPP_IND_ROW_6 \ 1612 IOMUXC_KPP_IPP_IND_ROW_6_SELECT_INPUT 1613 #define MUX_IN_KPP_IPP_IND_ROW_7 \ 1614 IOMUXC_KPP_IPP_IND_ROW_7_SELECT_INPUT 1615 #define MUX_IN_UART1_IPP_UART_RTS_B \ 1616 IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT 1617 #define MUX_IN_UART1_IPP_UART_RXD_MUX \ 1618 IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT 1619 #define MUX_IN_UART2_IPP_UART_RTS_B \ 1620 IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT 1621 #define MUX_IN_UART2_IPP_UART_RXD_MUX \ 1622 IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT 1623 #define MUX_IN_UART3_IPP_UART_RTS_B \ 1624 IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT 1625 #define MUX_IN_UART3_IPP_UART_RXD_MUX \ 1626 IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT 1627 #define MUX_IN_USBOH3_IPP_IND_UH3_CLK \ 1628 IOMUXC_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT 1629 #define MUX_IN_USBOH3_IPP_IND_UH3_DATA_0 \ 1630 IOMUXC_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT 1631 #define MUX_IN_USBOH3_IPP_IND_UH3_DATA_1 \ 1632 IOMUXC_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT 1633 #define MUX_IN_USBOH3_IPP_IND_UH3_DATA_2 \ 1634 IOMUXC_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT 1635 #define MUX_IN_USBOH3_IPP_IND_UH3_DATA_3 \ 1636 IOMUXC_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT 1637 #define MUX_IN_USBOH3_IPP_IND_UH3_DATA_4 \ 1638 IOMUXC_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT 1639 #define MUX_IN_USBOH3_IPP_IND_UH3_DATA_5 \ 1640 IOMUXC_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT 1641 #define MUX_IN_USBOH3_IPP_IND_UH3_DATA_6 \ 1642 IOMUXC_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT 1643 #define MUX_IN_USBOH3_IPP_IND_UH3_DATA_7 \ 1644 IOMUXC_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT 1645 #define MUX_IN_USBOH3_IPP_IND_UH3_DIR \ 1646 IOMUXC_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT 1647 #define MUX_IN_USBOH3_IPP_IND_UH3_NXT \ 1648 IOMUXC_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT 1649 #define MUX_IN_USBOH3_IPP_IND_UH3_STP \ 1650 IOMUXC_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT 1651 1652 #endif /* _IMX51_IOMUXREG_H */ 1653 1654
Indexes created Sun Oct 26 21:10:03 GMT 2025