imx51_ipuv3.c revision 1.1.16.1
1 /* $NetBSD: imx51_ipuv3.c,v 1.1.16.1 2014/08/10 06:53:51 tls Exp $ */ 2 3 /* 4 * Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: imx51_ipuv3.c,v 1.1.16.1 2014/08/10 06:53:51 tls Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/conf.h> 35 #include <sys/uio.h> 36 #include <sys/malloc.h> 37 #include <sys/kernel.h> /* for cold */ 38 #include <sys/pmf.h> 39 40 #include <uvm/uvm_extern.h> 41 42 #include <dev/cons.h> 43 #include <dev/wscons/wsconsio.h> 44 #include <dev/wscons/wsdisplayvar.h> 45 #include <dev/wscons/wscons_callbacks.h> 46 #include <dev/rasops/rasops.h> 47 #include <dev/wsfont/wsfont.h> 48 #include <dev/wscons/wsdisplay_vconsvar.h> 49 50 #include <sys/bus.h> 51 #include <machine/cpu.h> 52 #include <arm/cpufunc.h> 53 54 #include <arm/imx/imx51var.h> 55 #include <arm/imx/imx51reg.h> 56 #include <arm/imx/imx51_ipuv3var.h> 57 #include <arm/imx/imx51_ipuv3reg.h> 58 #include <arm/imx/imx51_ccmvar.h> 59 #include <arm/imx/imx51_ccmreg.h> 60 61 #include "imxccm.h" /* if CCM driver is configured into the kernel */ 62 #include "wsdisplay.h" 63 #include "opt_imx51_ipuv3.h" 64 65 /* 66 * Console variables. These are necessary since console is setup very early, 67 * before devices get attached. 68 */ 69 struct { 70 int is_console; 71 struct imx51_wsscreen_descr *descr; 72 struct wsdisplay_accessops *accessops; 73 const struct lcd_panel_geometry *geom; 74 } imx51_ipuv3_console; 75 76 #define IPUV3_READ(ipuv3, module, reg) \ 77 bus_space_read_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg)) 78 #define IPUV3_WRITE(ipuv3, module, reg, val) \ 79 bus_space_write_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg), (val)) 80 81 #ifdef IPUV3_DEBUG 82 int ipuv3_debug = IPUV3_DEBUG; 83 #define DPRINTFN(n,x) if (ipuv3_debug>(n)) printf x; else 84 #else 85 #define DPRINTFN(n,x) 86 #endif 87 88 int ipuv3intr(void *); 89 90 static void imx51_ipuv3_initialize(struct imx51_ipuv3_softc *, 91 const struct lcd_panel_geometry *); 92 #if NWSDISPLAY > 0 93 static void imx51_ipuv3_setup_rasops(struct imx51_ipuv3_softc *, 94 struct rasops_info *, struct imx51_wsscreen_descr *, 95 const struct lcd_panel_geometry *); 96 #endif 97 static void imx51_ipuv3_set_idma_param(uint32_t *, uint32_t, uint32_t); 98 99 static bool imx51_ipuv3_resume(device_t, const pmf_qual_t *); 100 static bool imx51_ipuv3_suspend(device_t, const pmf_qual_t *); 101 102 #ifdef IPUV3_DEBUG 103 static void 104 imx51_ipuv3_dump(struct imx51_ipuv3_softc *sc) 105 { 106 int i; 107 108 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 109 110 #define __DUMP(grp, reg) \ 111 DPRINTFN(4, ("%-16s = 0x%08X\n", #reg, IPUV3_READ(sc, grp, IPU_##reg))) 112 113 __DUMP(cm, CM_CONF); 114 __DUMP(cm, CM_DISP_GEN); 115 __DUMP(idmac, IDMAC_CONF); 116 __DUMP(idmac, IDMAC_CH_EN_1); 117 __DUMP(idmac, IDMAC_CH_EN_2); 118 __DUMP(idmac, IDMAC_CH_PRI_1); 119 __DUMP(idmac, IDMAC_CH_PRI_2); 120 __DUMP(idmac, IDMAC_BNDM_EN_1); 121 __DUMP(idmac, IDMAC_BNDM_EN_2); 122 __DUMP(cm, CM_CH_DB_MODE_SEL_0); 123 __DUMP(cm, CM_CH_DB_MODE_SEL_1); 124 __DUMP(dmfc, DMFC_WR_CHAN); 125 __DUMP(dmfc, DMFC_WR_CHAN_DEF); 126 __DUMP(dmfc, DMFC_DP_CHAN); 127 __DUMP(dmfc, DMFC_DP_CHAN_DEF); 128 __DUMP(dmfc, DMFC_IC_CTRL); 129 __DUMP(cm, CM_FS_PROC_FLOW1); 130 __DUMP(cm, CM_FS_PROC_FLOW2); 131 __DUMP(cm, CM_FS_PROC_FLOW3); 132 __DUMP(cm, CM_FS_DISP_FLOW1); 133 __DUMP(dc, DC_DISP_CONF1_0); 134 __DUMP(dc, DC_DISP_CONF2_0); 135 __DUMP(dc, DC_WR_CH_CONF_5); 136 137 printf("*** IPU ***\n"); 138 for (i = 0; i <= 0x17c; i += 4) 139 DPRINTFN(6, ("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, cm, i))); 140 printf("*** IDMAC ***\n"); 141 for (i = 0; i <= 0x104; i += 4) 142 DPRINTFN(6, ("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, idmac, i))); 143 printf("*** CPMEM ***\n"); 144 for (i = 0x5c0; i <= 0x600; i += 4) 145 DPRINTFN(6, ("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, cpmem, i))); 146 147 #undef __DUMP 148 149 } 150 #endif 151 152 static void 153 imx51_ipuv3_enable_display(struct imx51_ipuv3_softc *sc) 154 { 155 uint32_t reg = 0; 156 157 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 158 159 /* enable sub modules */ 160 reg = IPUV3_READ(sc, cm, IPU_CM_CONF); 161 reg |= CM_CONF_DP_EN | 162 CM_CONF_DC_EN | 163 CM_CONF_DMFC_EN | 164 CM_CONF_DI0_EN; 165 IPUV3_WRITE(sc, cm, IPU_CM_CONF, reg); 166 } 167 168 static void 169 imx51_ipuv3_dmfc_init(struct imx51_ipuv3_softc *sc) 170 { 171 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 172 173 /* IC channel is disabled */ 174 IPUV3_WRITE(sc, dmfc, IPU_DMFC_IC_CTRL, 175 IC_IN_PORT_DISABLE); 176 177 IPUV3_WRITE(sc, dmfc, IPU_DMFC_WR_CHAN, 0x00000000); 178 IPUV3_WRITE(sc, dmfc, IPU_DMFC_WR_CHAN_DEF, 0x20202020); 179 IPUV3_WRITE(sc, dmfc, IPU_DMFC_DP_CHAN, 0x00000094); 180 IPUV3_WRITE(sc, dmfc, IPU_DMFC_DP_CHAN_DEF, 0x202020F6); 181 182 IPUV3_WRITE(sc, dmfc, IPU_DMFC_GENERAL1, 183 DCDP_SYNC_PR_ROUNDROBIN); 184 185 #ifdef IPUV3_DEBUG 186 int i; 187 printf("*** DMFC ***\n"); 188 for (i = 0; i <= 0x34; i += 4) 189 printf("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, dmfc, i)); 190 191 printf("%s: DMFC_IC_CTRL 0x%08X\n", __func__, 192 IPUV3_READ(sc, dmfc, IPU_DMFC_IC_CTRL)); 193 printf("%s: IPU_DMFC_WR_CHAN 0x%08X\n", __func__, 194 IPUV3_READ(sc, dmfc, IPU_DMFC_WR_CHAN)); 195 printf("%s: IPU_DMFC_WR_CHAN_DEF 0x%08X\n", __func__, 196 IPUV3_READ(sc, dmfc, IPU_DMFC_WR_CHAN_DEF)); 197 printf("%s: IPU_DMFC_GENERAL1 0x%08X\n", __func__, 198 IPUV3_READ(sc, dmfc, IPU_DMFC_GENERAL1)); 199 #endif 200 } 201 202 static void 203 imx51_ipuv3_dc_map_clear(struct imx51_ipuv3_softc *sc, int map) 204 { 205 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 206 207 uint32_t reg; 208 uint32_t addr; 209 210 addr = IPU_DC_MAP_CONF_PNTR(map / 2); 211 reg = IPUV3_READ(sc, dc, addr); 212 reg &= ~(0xFFFF << (16 * (map & 0x1))); 213 IPUV3_WRITE(sc, dc, addr, reg); 214 } 215 216 static void 217 imx51_ipuv3_dc_map_conf(struct imx51_ipuv3_softc *sc, 218 int map, int byte, int offset, uint8_t mask) 219 { 220 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 221 222 uint32_t reg; 223 uint32_t addr; 224 225 addr = IPU_DC_MAP_CONF_MASK((map * 3 + byte) / 2); 226 reg = IPUV3_READ(sc, dc, addr); 227 reg &= ~(0xFFFF << (16 * ((map * 3 + byte) & 0x1))); 228 reg |= ((offset << 8) | mask) << (16 * ((map * 3 + byte) & 0x1)); 229 IPUV3_WRITE(sc, dc, addr, reg); 230 #ifdef IPUV3_DEBUG 231 printf("%s: addr 0x%08X reg 0x%08X\n", __func__, addr, reg); 232 #endif 233 234 addr = IPU_DC_MAP_CONF_PNTR(map / 2); 235 reg = IPUV3_READ(sc, dc, addr); 236 reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte))); 237 reg |= ((map * 3) + byte) << ((16 * (map & 0x1)) + (5 * byte)); 238 IPUV3_WRITE(sc, dc, addr, reg); 239 #ifdef IPUV3_DEBUG 240 printf("%s: addr 0x%08X reg 0x%08X\n", __func__, addr, reg); 241 #endif 242 } 243 244 static void 245 imx51_ipuv3_dc_template_command(struct imx51_ipuv3_softc *sc, 246 int index, int sync, int gluelogic, int waveform, int mapping, 247 int operand, int opecode, int stop) 248 { 249 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 250 251 uint32_t reg; 252 253 reg = (sync << 0) | 254 (gluelogic << 4) | 255 (waveform << 11) | 256 (mapping << 15) | 257 (operand << 20); 258 IPUV3_WRITE(sc, dctmpl, index * 8, reg); 259 #ifdef IPUV3_DEBUG 260 printf("%s: addr 0x%08X reg 0x%08X\n", __func__, index * 8, reg); 261 #endif 262 reg = (opecode << 0) | 263 (stop << 9); 264 IPUV3_WRITE(sc, dctmpl, index * 8 + 4, reg); 265 #ifdef IPUV3_DEBUG 266 printf("%s: addr 0x%08X reg 0x%08X\n", __func__, index * 8 + 4, reg); 267 #endif 268 } 269 270 static void 271 imx51_ipuv3_set_routine_link(struct imx51_ipuv3_softc *sc, 272 int base, int evt, int addr, int pri) 273 { 274 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 275 276 uint32_t reg; 277 278 reg = IPUV3_READ(sc, dc, IPU_DC_RL(base, evt)); 279 reg &= ~(0xFFFF << (16 * (evt & 0x1))); 280 reg |= ((addr << 8) | pri) << (16 * (evt & 0x1)); 281 IPUV3_WRITE(sc, dc, IPU_DC_RL(base, evt), reg); 282 #ifdef IPUV3_DEBUG 283 printf("%s: event %d addr %d priority %d\n", __func__, 284 evt, addr, pri); 285 printf("%s: %p = 0x%08X\n", __func__, 286 (void *)IPU_DC_RL(base, evt), reg); 287 #endif 288 } 289 290 static void 291 imx51_ipuv3_dc_init(struct imx51_ipuv3_softc *sc) 292 { 293 uint32_t reg; 294 295 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 296 297 imx51_ipuv3_dc_map_clear(sc, 0); 298 imx51_ipuv3_dc_map_conf(sc, 0, 0, 7, 0xff); 299 imx51_ipuv3_dc_map_conf(sc, 0, 1, 15, 0xff); 300 imx51_ipuv3_dc_map_conf(sc, 0, 2, 23, 0xff); 301 imx51_ipuv3_dc_map_clear(sc, 1); 302 imx51_ipuv3_dc_map_conf(sc, 1, 0, 5, 0xfc); 303 imx51_ipuv3_dc_map_conf(sc, 1, 1, 11, 0xfc); 304 imx51_ipuv3_dc_map_conf(sc, 1, 2, 17, 0xfc); 305 imx51_ipuv3_dc_map_clear(sc, 2); 306 imx51_ipuv3_dc_map_conf(sc, 2, 0, 15, 0xff); 307 imx51_ipuv3_dc_map_conf(sc, 2, 1, 23, 0xff); 308 imx51_ipuv3_dc_map_conf(sc, 2, 2, 7, 0xff); 309 imx51_ipuv3_dc_map_clear(sc, 3); 310 imx51_ipuv3_dc_map_conf(sc, 3, 0, 4, 0xf8); 311 imx51_ipuv3_dc_map_conf(sc, 3, 1, 10, 0xfc); 312 imx51_ipuv3_dc_map_conf(sc, 3, 2, 15, 0xf8); 313 imx51_ipuv3_dc_map_clear(sc, 4); 314 imx51_ipuv3_dc_map_conf(sc, 4, 0, 5, 0xfc); 315 imx51_ipuv3_dc_map_conf(sc, 4, 1, 13, 0xfc); 316 imx51_ipuv3_dc_map_conf(sc, 4, 2, 21, 0xfc); 317 318 /* microcode */ 319 imx51_ipuv3_dc_template_command(sc, 320 5, 5, 8, 1, 5, 0, 0x180, 1); 321 imx51_ipuv3_dc_template_command(sc, 322 6, 5, 4, 1, 5, 0, 0x180, 1); 323 imx51_ipuv3_dc_template_command(sc, 324 7, 5, 0, 1, 5, 0, 0x180, 1); 325 326 reg = (4 << 5) | 0x2; 327 IPUV3_WRITE(sc, dc, IPU_DC_WR_CH_CONF_5, reg); 328 IPUV3_WRITE(sc, dc, IPU_DC_WR_CH_CONF_1, 0x4); 329 IPUV3_WRITE(sc, dc, IPU_DC_WR_CH_ADDR_5, 0x0); 330 IPUV3_WRITE(sc, dc, IPU_DC_GEN, 0x44); 331 332 imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NL, 5, 3); 333 imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_EOL, 6, 2); 334 imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NEW_DATA, 7, 1); 335 imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NF, 0, 0); 336 imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NFIELD, 0, 0); 337 imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_EOF, 0, 0); 338 imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_EOFIELD, 0, 0); 339 imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NEW_CHAN, 0, 0); 340 imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NEW_ADDR, 0, 0); 341 342 #ifdef IPUV3_DEBUG 343 int i; 344 printf("*** DC ***\n"); 345 for (i = 0; i <= 0x1C8; i += 4) 346 printf("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, dc, i)); 347 printf("*** DCTEMPL ***\n"); 348 for (i = 0; i <= 0x100; i += 4) 349 printf("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, dctmpl, i)); 350 #endif 351 } 352 353 static void 354 imx51_ipuv3_dc_display_config(struct imx51_ipuv3_softc *sc, int width) 355 { 356 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 357 358 IPUV3_WRITE(sc, dc, IPU_DC_DISP_CONF2_0, width); 359 } 360 361 static void 362 imx51_ipuv3_di_sync_conf(struct imx51_ipuv3_softc *sc, int no, 363 uint32_t reg_gen0, uint32_t reg_gen1, uint32_t repeat) 364 { 365 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 366 367 uint32_t reg; 368 369 IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(no), reg_gen0); 370 IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(no), reg_gen1); 371 reg = IPUV3_READ(sc, di0, IPU_DI_STP_REP(no)); 372 reg &= ~DI_STP_REP_MASK(no); 373 reg |= repeat << DI_STP_REP_SHIFT(no); 374 IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(no), reg); 375 376 #ifdef IPUV3_DEBUG 377 printf("%s: no %d\n", __func__, no); 378 printf("%s: addr 0x%08X reg_gen0 0x%08X\n", __func__, 379 IPU_DI_SW_GEN0(no), reg_gen0); 380 printf("%s: addr 0x%08X reg_gen1 0x%08X\n", __func__, 381 IPU_DI_SW_GEN1(no), reg_gen1); 382 printf("%s: addr 0x%08X DI_STP_REP 0x%08X\n", __func__, 383 IPU_DI_STP_REP(no), reg); 384 #endif 385 } 386 387 static void 388 imx51_ipuv3_di_init(struct imx51_ipuv3_softc *sc) 389 { 390 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 391 392 uint32_t reg; 393 uint32_t div; 394 u_int ipuclk; 395 const struct lcd_panel_geometry *geom = sc->geometry; 396 397 #if NIMXCCM > 0 398 ipuclk = imx51_get_clock(IMX51CLK_IPU_HSP_CLK_ROOT); 399 #elif !defined(IMX51_IPU_HSP_CLOCK) 400 #error IMX51_CPU_HSP_CLOCK need to be defined. 401 #else 402 ipuclk = IMX51_IPU_HSP_CLOCK; 403 #endif 404 DPRINTFN(3, ("IPU HSP clock = %d\n", ipuclk)); 405 div = (ipuclk * 16) / geom->pixel_clk; 406 div = div < 16 ? 16 : div & 0xff8; 407 408 /* DI counter */ 409 reg = IPUV3_READ(sc, cm, IPU_CM_DISP_GEN); 410 reg &= ~(CM_DISP_GEN_DI1_COUNTER_RELEASE | 411 CM_DISP_GEN_DI0_COUNTER_RELEASE); 412 IPUV3_WRITE(sc, cm, IPU_CM_DISP_GEN, reg); 413 414 IPUV3_WRITE(sc, di0, IPU_DI_BS_CLKGEN0, div); 415 IPUV3_WRITE(sc, di0, IPU_DI_BS_CLKGEN1, 416 (div / 16) << DI_BS_CLKGEN1_DOWN_SHIFT); 417 #ifdef IPUV3_DEBUG 418 printf("%s: IPU_DI_BS_CLKGEN0 = 0x%08X\n", __func__, 419 IPUV3_READ(sc, di0, IPU_DI_BS_CLKGEN0)); 420 printf("%s: IPU_DI_BS_CLKGEN1 = 0x%08X\n", __func__, 421 IPUV3_READ(sc, di0, IPU_DI_BS_CLKGEN1)); 422 #endif 423 /* Display Time settings */ 424 reg = ((div / 16 - 1) << DI_DW_GEN_ACCESS_SIZE_SHIFT) | 425 ((div / 16 - 1) << DI_DW_GEN_COMPONNENT_SIZE_SHIFT) | 426 (3 << DI_DW_GEN_PIN_SHIFT(15)); 427 IPUV3_WRITE(sc, di0, IPU_DI_DW_GEN(0), reg); 428 #ifdef IPUV3_DEBUG 429 printf("%s: div = %d\n", __func__, div); 430 printf("%s: IPU_DI_DW_GEN(0) 0x%08X = 0x%08X\n", __func__, 431 IPU_DI_DW_GEN(0), reg); 432 #endif 433 434 /* Up & Down Data Wave Set */ 435 reg = (div / 16 * 2) << DI_DW_SET_DOWN_SHIFT; 436 IPUV3_WRITE(sc, di0, IPU_DI_DW_SET(0, 3), reg); 437 #ifdef IPUV3_DEBUG 438 printf("%s: IPU_DI_DW_SET(0, 3) 0x%08X = 0x%08X\n", __func__, 439 IPU_DI_DW_SET(0, 3), reg); 440 #endif 441 442 /* internal HSCYNC */ 443 imx51_ipuv3_di_sync_conf(sc, 1, 444 __DI_SW_GEN0(geom->panel_width + geom->hsync_width + 445 geom->left + geom->right - 1, 1, 0, 0), 446 __DI_SW_GEN1(0, 1, 0, 0, 0, 0, 0), 447 0); 448 449 /* HSYNC */ 450 imx51_ipuv3_di_sync_conf(sc, 2, 451 __DI_SW_GEN0(geom->panel_width + geom->hsync_width + 452 geom->left + geom->right - 1, 1, 0, 1), 453 __DI_SW_GEN1(1, 1, 0, geom->hsync_width * 2, 1, 0, 0), 454 0); 455 456 /* VSYNC */ 457 imx51_ipuv3_di_sync_conf(sc, 3, 458 __DI_SW_GEN0(geom->panel_height + geom->vsync_width + 459 geom->upper + geom->lower - 1, 2, 0, 0), 460 __DI_SW_GEN1(1, 1, 0, geom->vsync_width * 2, 2, 0, 0), 461 0); 462 463 IPUV3_WRITE(sc, di0, IPU_DI_SCR_CONF, 464 geom->panel_height + geom->vsync_width + geom->upper + 465 geom->lower - 1); 466 467 /* Active Lines Start */ 468 imx51_ipuv3_di_sync_conf(sc, 4, 469 __DI_SW_GEN0(0, 3, geom->vsync_width + geom->upper, 3), 470 __DI_SW_GEN1(0, 0, 4, 0, 0, 0, 0), 471 geom->panel_height); 472 473 /* Active Clock Start */ 474 imx51_ipuv3_di_sync_conf(sc, 5, 475 __DI_SW_GEN0(0, 1, geom->hsync_width + geom->left, 1), 476 __DI_SW_GEN1(0, 0, 5, 0, 0, 0, 0), 477 geom->panel_width); 478 479 IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(6), 0); 480 IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(6), 0); 481 IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(7), 0); 482 IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(7), 0); 483 IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(8), 0); 484 IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(8), 0); 485 IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(9), 0); 486 IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(9), 0); 487 488 reg = IPUV3_READ(sc, di0, IPU_DI_STP_REP(6)); 489 reg &= ~DI_STP_REP_MASK(6); 490 IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(6), reg); 491 IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(7), 0); 492 IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(9), 0); 493 494 IPUV3_WRITE(sc, di0, IPU_DI_GENERAL, 0); 495 reg = ((3 - 1) << DI_SYNC_AS_GEN_VSYNC_SEL_SHIFT) | 0x2; 496 IPUV3_WRITE(sc, di0, IPU_DI_SYNC_AS_GEN, reg); 497 IPUV3_WRITE(sc, di0, IPU_DI_POL, DI_POL_DRDY_POLARITY_15); 498 499 /* release DI counter */ 500 reg = IPUV3_READ(sc, cm, IPU_CM_DISP_GEN); 501 reg |= CM_DISP_GEN_DI0_COUNTER_RELEASE; 502 IPUV3_WRITE(sc, cm, IPU_CM_DISP_GEN, reg); 503 504 #ifdef IPUV3_DEBUG 505 int i; 506 printf("*** DI0 ***\n"); 507 for (i = 0; i <= 0x174; i += 4) 508 printf("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, di0, i)); 509 510 printf("%s: IPU_CM_DISP_GEN : 0x%08X\n", __func__, 511 IPUV3_READ(sc, cm, IPU_CM_DISP_GEN)); 512 printf("%s: IPU_DI_SYNC_AS_GEN : 0x%08X\n", __func__, 513 IPUV3_READ(sc, di0, IPU_DI_SYNC_AS_GEN)); 514 printf("%s: IPU_DI_GENERAL : 0x%08X\n", __func__, 515 IPUV3_READ(sc, di0, IPU_DI_GENERAL)); 516 printf("%s: IPU_DI_POL : 0x%08X\n", __func__, 517 IPUV3_READ(sc, di0, IPU_DI_POL)); 518 #endif 519 } 520 521 522 void 523 imx51_ipuv3_geometry(struct imx51_ipuv3_softc *sc, 524 const struct lcd_panel_geometry *geom) 525 { 526 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 527 528 sc->geometry = geom; 529 530 #ifdef IPUV3_DEBUG 531 printf("%s: screen height = %d\n",__func__ , geom->panel_height); 532 printf("%s: width = %d\n",__func__ , geom->panel_width); 533 printf("%s: IPU Clock = %d\n", __func__, 534 imx51_get_clock(IMX51CLK_IPU_HSP_CLK_ROOT)); 535 printf("%s: Pixel Clock = %d\n", __func__, geom->pixel_clk); 536 #endif 537 538 imx51_ipuv3_di_init(sc); 539 540 #ifdef IPUV3_DEBUG 541 printf("%s: IPU_CM_DISP_GEN : 0x%08X\n", __func__, 542 IPUV3_READ(sc, cm, IPU_CM_DISP_GEN)); 543 #endif 544 545 imx51_ipuv3_dc_display_config(sc, geom->panel_width); 546 547 return; 548 } 549 550 /* 551 * Initialize the IPUV3 controller. 552 */ 553 static void 554 imx51_ipuv3_initialize(struct imx51_ipuv3_softc *sc, 555 const struct lcd_panel_geometry *geom) 556 { 557 uint32_t reg; 558 559 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 560 561 IPUV3_WRITE(sc, cm, IPU_CM_CONF, 0); 562 563 /* reset */ 564 IPUV3_WRITE(sc, cm, IPU_CM_MEM_RST, CM_MEM_START | CM_MEM_EN); 565 while (IPUV3_READ(sc, cm, IPU_CM_MEM_RST) & CM_MEM_START) 566 ; /* wait */ 567 568 imx51_ipuv3_dmfc_init(sc); 569 imx51_ipuv3_dc_init(sc); 570 571 imx51_ipuv3_geometry(sc, geom); 572 573 /* set global alpha */ 574 IPUV3_WRITE(sc, dp, IPU_DP_GRAPH_WIND_CTRL_SYNC, 0x80 << 24); 575 IPUV3_WRITE(sc, dp, IPU_DP_COM_CONF_SYNC, DP_DP_GWAM_SYNC); 576 577 reg = IPUV3_READ(sc, cm, IPU_CM_DISP_GEN); 578 reg |= CM_DISP_GEN_MCU_MAX_BURST_STOP | 579 CM_DISP_GEN_MCU_T(0x8); 580 IPUV3_WRITE(sc, cm, IPU_CM_DISP_GEN, reg); 581 } 582 583 static void 584 imx51_ipuv3_init_screen(void *cookie, struct vcons_screen *scr, 585 int existing, long *defattr) 586 { 587 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 588 589 struct imx51_ipuv3_softc *sc = cookie; 590 struct rasops_info *ri = &scr->scr_ri; 591 struct imx51_wsscreen_descr *descr = imx51_ipuv3_console.descr; 592 593 if ((scr == &sc->console) && (sc->vd.active != NULL)) 594 return; 595 596 ri->ri_bits = sc->active->buf_va; 597 598 scr->scr_flags |= VCONS_DONT_READ; 599 if (existing) 600 ri->ri_flg |= RI_CLEAR; 601 602 imx51_ipuv3_setup_rasops(sc, ri, descr, sc->geometry); 603 604 ri->ri_caps = WSSCREEN_WSCOLORS; 605 606 rasops_reconfig(ri, 607 ri->ri_height / ri->ri_font->fontheight, 608 ri->ri_width / ri->ri_font->fontwidth); 609 610 ri->ri_hw = scr; 611 } 612 613 /* 614 * Common driver attachment code. 615 */ 616 void 617 imx51_ipuv3_attach_sub(struct imx51_ipuv3_softc *sc, 618 struct axi_attach_args *axia, const struct lcd_panel_geometry *geom) 619 { 620 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 621 622 bus_space_tag_t iot = axia->aa_iot; 623 bus_space_handle_t ioh; 624 int error; 625 626 aprint_normal(": i.MX51 IPUV3 controller\n"); 627 628 sc->n_screens = 0; 629 LIST_INIT(&sc->screens); 630 631 sc->iot = iot; 632 sc->dma_tag = &imx_bus_dma_tag; 633 634 /* map controller registers */ 635 error = bus_space_map(iot, IPU_CM_BASE, IPU_CM_SIZE, 0, &ioh); 636 if (error) 637 goto fail_retarn_cm; 638 sc->cm_ioh = ioh; 639 640 /* map Display Multi FIFO Controller registers */ 641 error = bus_space_map(iot, IPU_DMFC_BASE, IPU_DMFC_SIZE, 0, &ioh); 642 if (error) 643 goto fail_retarn_dmfc; 644 sc->dmfc_ioh = ioh; 645 646 /* map Display Interface registers */ 647 error = bus_space_map(iot, IPU_DI0_BASE, IPU_DI0_SIZE, 0, &ioh); 648 if (error) 649 goto fail_retarn_di0; 650 sc->di0_ioh = ioh; 651 652 /* map Display Processor registers */ 653 error = bus_space_map(iot, IPU_DP_BASE, IPU_DP_SIZE, 0, &ioh); 654 if (error) 655 goto fail_retarn_dp; 656 sc->dp_ioh = ioh; 657 658 /* map Display Controller registers */ 659 error = bus_space_map(iot, IPU_DC_BASE, IPU_DC_SIZE, 0, &ioh); 660 if (error) 661 goto fail_retarn_dc; 662 sc->dc_ioh = ioh; 663 664 /* map Image DMA Controller registers */ 665 error = bus_space_map(iot, IPU_IDMAC_BASE, IPU_IDMAC_SIZE, 0, &ioh); 666 if (error) 667 goto fail_retarn_idmac; 668 sc->idmac_ioh = ioh; 669 670 /* map CPMEM registers */ 671 error = bus_space_map(iot, IPU_CPMEM_BASE, IPU_CPMEM_SIZE, 0, &ioh); 672 if (error) 673 goto fail_retarn_cpmem; 674 sc->cpmem_ioh = ioh; 675 676 /* map DCTEMPL registers */ 677 error = bus_space_map(iot, IPU_DCTMPL_BASE, IPU_DCTMPL_SIZE, 0, &ioh); 678 if (error) 679 goto fail_retarn_dctmpl; 680 sc->dctmpl_ioh = ioh; 681 682 #ifdef notyet 683 sc->ih = imx51_ipuv3_intr_establish(IMX51_INT_IPUV3, IPL_BIO, 684 ipuv3intr, sc); 685 if (sc->ih == NULL) { 686 aprint_error_dev(sc->dev, 687 "unable to establish interrupt at irq %d\n", 688 IMX51_INT_IPUV3); 689 return; 690 } 691 #endif 692 693 imx51_ipuv3_initialize(sc, geom); 694 695 #if NWSDISPLAY > 0 696 struct imx51_wsscreen_descr *descr = imx51_ipuv3_console.descr; 697 struct imx51_ipuv3_screen *scr; 698 699 sc->mode = WSDISPLAYIO_MODE_EMUL; 700 error = imx51_ipuv3_new_screen(sc, descr->depth, &scr); 701 if (error) { 702 aprint_error_dev(sc->dev, 703 "unable to create new screen (errno=%d)", error); 704 return; 705 } 706 sc->active = scr; 707 708 vcons_init(&sc->vd, sc, &descr->c, 709 imx51_ipuv3_console.accessops); 710 sc->vd.init_screen = imx51_ipuv3_init_screen; 711 712 #ifdef IPUV3_DEBUG 713 printf("%s: IPUV3 console ? %d\n", __func__, imx51_ipuv3_console.is_console); 714 #endif 715 716 struct rasops_info *ri; 717 long defattr; 718 ri = &sc->console.scr_ri; 719 720 vcons_init_screen(&sc->vd, &sc->console, 1, 721 &defattr); 722 sc->console.scr_flags |= VCONS_SCREEN_IS_STATIC; 723 724 descr->c.nrows = ri->ri_rows; 725 descr->c.ncols = ri->ri_cols; 726 descr->c.textops = &ri->ri_ops; 727 descr->c.capabilities = ri->ri_caps; 728 729 if (imx51_ipuv3_console.is_console) { 730 wsdisplay_cnattach(&descr->c, ri, 0, 0, defattr); 731 aprint_normal_dev(sc->dev, "console\n"); 732 } 733 734 vcons_replay_msgbuf(&sc->console); 735 736 imx51_ipuv3_start_dma(sc, scr); 737 #endif 738 739 if (!pmf_device_register(sc->dev, imx51_ipuv3_suspend, 740 imx51_ipuv3_resume)) { 741 aprint_error_dev(sc->dev, "can't establish power hook\n"); 742 } 743 744 return; 745 746 fail_retarn_dctmpl: 747 bus_space_unmap(sc->iot, sc->cpmem_ioh, IPU_CPMEM_SIZE); 748 fail_retarn_cpmem: 749 bus_space_unmap(sc->iot, sc->idmac_ioh, IPU_IDMAC_SIZE); 750 fail_retarn_idmac: 751 bus_space_unmap(sc->iot, sc->dc_ioh, IPU_DC_SIZE); 752 fail_retarn_dp: 753 bus_space_unmap(sc->iot, sc->dp_ioh, IPU_DP_SIZE); 754 fail_retarn_dc: 755 bus_space_unmap(sc->iot, sc->di0_ioh, IPU_DI0_SIZE); 756 fail_retarn_di0: 757 bus_space_unmap(sc->iot, sc->dmfc_ioh, IPU_DMFC_SIZE); 758 fail_retarn_dmfc: 759 bus_space_unmap(sc->iot, sc->dc_ioh, IPU_CM_SIZE); 760 fail_retarn_cm: 761 aprint_error_dev(sc->dev, 762 "failed to map registers (errno=%d)\n", error); 763 return; 764 } 765 766 int 767 imx51_ipuv3_cnattach(bool isconsole, struct imx51_wsscreen_descr *descr, 768 struct wsdisplay_accessops *accessops, 769 const struct lcd_panel_geometry *geom) 770 { 771 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 772 imx51_ipuv3_console.descr = descr; 773 imx51_ipuv3_console.geom = geom; 774 imx51_ipuv3_console.accessops = accessops; 775 imx51_ipuv3_console.is_console = isconsole; 776 return 0; 777 } 778 779 #ifdef notyet 780 /* 781 * Interrupt handler. 782 */ 783 int 784 ipuv3intr(void *arg) 785 { 786 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 787 788 struct imx51_ipuv3_softc *sc = (struct imx51_ipuv3_softc *)arg; 789 bus_space_tag_t iot = sc->iot; 790 bus_space_handle_t ioh = sc->dc_ioh; 791 uint32_t status; 792 793 status = IPUV3_READ(ioh, V3CR); 794 /* Clear stickey status bits */ 795 IPUV3_WRITE(ioh, V3CR, status); 796 797 return 1; 798 } 799 #endif 800 801 static void 802 imx51_ipuv3_write_dmaparam(struct imx51_ipuv3_softc *sc, 803 int ch, uint32_t *value, int size) 804 { 805 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 806 807 int i; 808 uint32_t addr = ch * 0x40; 809 810 for (i = 0; i < size; i++) { 811 IPUV3_WRITE(sc, cpmem, addr + ((i % 5) * 0x4) + 812 ((i / 5) * 0x20), value[i]); 813 #ifdef IPUV3_DEBUG 814 printf("%s: addr = 0x%08X, val = 0x%08X\n", __func__, 815 addr + ((i % 5) * 0x4) + ((i / 5) * 0x20), 816 IPUV3_READ(sc, cpmem, addr + ((i % 5) * 0x4) + 817 ((i / 5) * 0x20))); 818 #endif 819 } 820 } 821 822 static void 823 imx51_ipuv3_build_param(struct imx51_ipuv3_softc *sc, 824 struct imx51_ipuv3_screen *scr, 825 uint32_t *params) 826 { 827 const struct lcd_panel_geometry *geom = sc->geometry; 828 829 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 830 831 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_FW, 832 (geom->panel_width - 1)); 833 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_FH, 834 (geom->panel_height - 1)); 835 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_EBA0, 836 scr->segs[0].ds_addr >> 3); 837 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_EBA1, 838 scr->segs[0].ds_addr >> 3); 839 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_SL, 840 (scr->stride - 1)); 841 842 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_PFS, 0x7); 843 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_NPB, 32 - 1); 844 845 switch (scr->depth) { 846 case 32: 847 /* ARBG888 */ 848 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_BPP, 0x0); 849 850 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS0, 0); 851 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS1, 8); 852 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS2, 16); 853 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS3, 24); 854 855 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID0, 8 - 1); 856 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID1, 8 - 1); 857 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID2, 8 - 1); 858 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID3, 8 - 1); 859 break; 860 case 24: 861 /* RBG888 */ 862 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_BPP, 0x1); 863 864 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS0, 0); 865 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS1, 8); 866 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS2, 16); 867 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS3, 24); 868 869 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID0, 8 - 1); 870 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID1, 8 - 1); 871 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID2, 8 - 1); 872 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID3, 0); 873 break; 874 case 16: 875 /* RBG565 */ 876 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_BPP, 0x3); 877 878 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS0, 0); 879 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS1, 5); 880 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS2, 11); 881 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS3, 16); 882 883 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID0, 5 - 1); 884 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID1, 6 - 1); 885 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID2, 5 - 1); 886 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID3, 0); 887 break; 888 default: 889 panic("%s: unsupported depth %d\n", __func__, scr->depth); 890 break; 891 } 892 893 imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_ID, 1); 894 } 895 896 static void 897 imx51_ipuv3_set_idma_param(uint32_t *params, uint32_t name, uint32_t val) 898 { 899 int word = (name >> 16) & 0xff; 900 int shift = (name >> 8) & 0xff; 901 int width = name & 0xff; 902 int index; 903 904 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 905 906 index = word * 5; 907 index += shift / 32; 908 shift = shift % 32; 909 910 params[index] |= val << shift; 911 shift = 32 - shift; 912 913 if (width > shift) 914 params[index+1] |= val >> shift; 915 } 916 917 /* 918 * Enable DMA to cause the display to be refreshed periodically. 919 * This brings the screen to life... 920 */ 921 void 922 imx51_ipuv3_start_dma(struct imx51_ipuv3_softc *sc, 923 struct imx51_ipuv3_screen *scr) 924 { 925 int save; 926 uint32_t params[10]; 927 uint32_t reg; 928 929 DPRINTFN(3, ("%s: Pixel depth = %d\n", __func__, scr->depth)); 930 931 reg = IPUV3_READ(sc, idmac, IPU_IDMAC_CH_EN_1); 932 reg &= ~__BIT(CH_PANNEL_BG); 933 IPUV3_WRITE(sc, idmac, IPU_IDMAC_CH_EN_1, reg); 934 935 memset(params, 0, sizeof(params)); 936 imx51_ipuv3_build_param(sc, scr, params); 937 938 save = disable_interrupts(I32_bit); 939 940 /* IDMAC configuration */ 941 imx51_ipuv3_write_dmaparam(sc, CH_PANNEL_BG, params, 942 sizeof(params) / sizeof(params[0])); 943 944 IPUV3_WRITE(sc, idmac, IPU_IDMAC_CH_PRI_1, __BIT(CH_PANNEL_BG)); 945 946 /* double buffer */ 947 reg = IPUV3_READ(sc, cm, IPU_CM_CH_DB_MODE_SEL_0); 948 reg |= __BIT(CH_PANNEL_BG); 949 IPUV3_WRITE(sc, cm, IPU_CM_CH_DB_MODE_SEL_0, reg); 950 951 reg = IPUV3_READ(sc, idmac, IPU_IDMAC_CH_EN_1); 952 reg |= __BIT(CH_PANNEL_BG); 953 IPUV3_WRITE(sc, idmac, IPU_IDMAC_CH_EN_1, reg); 954 955 reg = IPUV3_READ(sc, cm, IPU_CM_GPR); 956 reg &= ~CM_GPR_IPU_CH_BUF0_RDY0_CLR; 957 IPUV3_WRITE(sc, cm, IPU_CM_GPR, reg); 958 959 IPUV3_WRITE(sc, cm, IPU_CM_CUR_BUF_0, __BIT(CH_PANNEL_BG)); 960 961 restore_interrupts(save); 962 963 imx51_ipuv3_enable_display(sc); 964 965 #ifdef IPUV3_DEBUG 966 imx51_ipuv3_dump(sc); 967 #endif 968 } 969 970 /* 971 * Disable screen refresh. 972 */ 973 static void 974 imx51_ipuv3_stop_dma(struct imx51_ipuv3_softc *sc) 975 { 976 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 977 978 return; 979 } 980 981 /* 982 * Create and initialize a new screen buffer. 983 */ 984 int 985 imx51_ipuv3_new_screen(struct imx51_ipuv3_softc *sc, int depth, 986 struct imx51_ipuv3_screen **scrpp) 987 { 988 const struct lcd_panel_geometry *geometry; 989 struct imx51_ipuv3_screen *scr = NULL; 990 int width, height; 991 bus_size_t size; 992 int error; 993 int busdma_flag = (cold ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK); 994 995 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 996 997 geometry = sc->geometry; 998 999 width = geometry->panel_width; 1000 height = geometry->panel_height; 1001 1002 scr = malloc(sizeof(*scr), M_DEVBUF, M_NOWAIT); 1003 if (scr == NULL) 1004 return ENOMEM; 1005 1006 memset(scr, 0, sizeof(*scr)); 1007 1008 scr->nsegs = 0; 1009 scr->depth = depth; 1010 scr->stride = width * depth / 8; 1011 scr->buf_size = size = scr->stride * height; 1012 scr->buf_va = NULL; 1013 1014 error = bus_dmamem_alloc(sc->dma_tag, size, 16, 0, scr->segs, 1, 1015 &scr->nsegs, busdma_flag); 1016 1017 if (error || scr->nsegs != 1) { 1018 /* XXX: 1019 * Actually we can handle nsegs>1 case by means 1020 * of multiple DMA descriptors for a panel. It 1021 * will make code here a bit hairly. 1022 */ 1023 if (error == 0) 1024 error = E2BIG; 1025 goto bad; 1026 } 1027 1028 error = bus_dmamem_map(sc->dma_tag, scr->segs, scr->nsegs, size, 1029 (void **)&scr->buf_va, busdma_flag | BUS_DMA_COHERENT); 1030 if (error) 1031 goto bad; 1032 1033 memset(scr->buf_va, 0, scr->buf_size); 1034 1035 /* map memory for DMA */ 1036 error = bus_dmamap_create(sc->dma_tag, 1024*1024*2, 1, 1024*1024*2, 0, 1037 busdma_flag, &scr->dma); 1038 if (error) 1039 goto bad; 1040 1041 error = bus_dmamap_load(sc->dma_tag, scr->dma, scr->buf_va, size, 1042 NULL, busdma_flag); 1043 if (error) 1044 goto bad; 1045 1046 LIST_INSERT_HEAD(&sc->screens, scr, link); 1047 sc->n_screens++; 1048 1049 #ifdef IPUV3_DEBUG 1050 printf("%s: screen buffer width %d\n", __func__, width); 1051 printf("%s: screen buffer height %d\n", __func__, height); 1052 printf("%s: screen buffer depth %d\n", __func__, depth); 1053 printf("%s: screen buffer stride %d\n", __func__, scr->stride); 1054 printf("%s: screen buffer size 0x%08X\n", __func__, 1055 (uint32_t)scr->buf_size); 1056 printf("%s: screen buffer addr virtual %p\n", __func__, scr->buf_va); 1057 printf("%s: screen buffer addr physical %p\n", __func__, 1058 (void *)scr->segs[0].ds_addr); 1059 #endif 1060 1061 scr->map_size = size; /* used when unmap this. */ 1062 1063 *scrpp = scr; 1064 1065 return 0; 1066 1067 bad: 1068 #ifdef IPUV3_DEBUG 1069 printf("%s: error = 0x%08X\n", __func__, error); 1070 #endif 1071 if (scr) { 1072 if (scr->buf_va) 1073 bus_dmamem_unmap(sc->dma_tag, scr->buf_va, size); 1074 if (scr->nsegs) 1075 bus_dmamem_free(sc->dma_tag, scr->segs, scr->nsegs); 1076 free(scr, M_DEVBUF); 1077 } 1078 *scrpp = NULL; 1079 return error; 1080 } 1081 1082 #if NWSDISPLAY > 0 1083 /* 1084 * Initialize rasops for a screen, as well as struct wsscreen_descr if this 1085 * is the first screen creation. 1086 */ 1087 static void 1088 imx51_ipuv3_setup_rasops(struct imx51_ipuv3_softc *sc, struct rasops_info *rinfo, 1089 struct imx51_wsscreen_descr *descr, 1090 const struct lcd_panel_geometry *geom) 1091 { 1092 1093 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 1094 1095 rinfo->ri_flg = descr->flags; 1096 rinfo->ri_depth = descr->depth; 1097 rinfo->ri_width = geom->panel_width; 1098 rinfo->ri_height = geom->panel_height; 1099 rinfo->ri_stride = rinfo->ri_width * rinfo->ri_depth / 8; 1100 1101 /* swap B and R */ 1102 if (descr->depth == 16) { 1103 rinfo->ri_rnum = 5; 1104 rinfo->ri_rpos = 11; 1105 rinfo->ri_gnum = 6; 1106 rinfo->ri_gpos = 5; 1107 rinfo->ri_bnum = 5; 1108 rinfo->ri_bpos = 0; 1109 } 1110 1111 if (descr->c.nrows == 0) { 1112 /* get rasops to compute screen size the first time */ 1113 rasops_init(rinfo, 100, 100); 1114 } else { 1115 rasops_init(rinfo, descr->c.nrows, descr->c.ncols); 1116 } 1117 1118 descr->c.nrows = rinfo->ri_rows; 1119 descr->c.ncols = rinfo->ri_cols; 1120 descr->c.capabilities = rinfo->ri_caps; 1121 descr->c.textops = &rinfo->ri_ops; 1122 } 1123 #endif 1124 /* 1125 * Power management 1126 */ 1127 static bool 1128 imx51_ipuv3_suspend(device_t dv, const pmf_qual_t *qual) 1129 { 1130 struct imx51_ipuv3_softc *sc = device_private(dv); 1131 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 1132 if (sc->active) 1133 imx51_ipuv3_stop_dma(sc); 1134 return true; 1135 } 1136 1137 static bool 1138 imx51_ipuv3_resume(device_t dv, const pmf_qual_t *qual) 1139 { 1140 struct imx51_ipuv3_softc *sc = device_private(dv); 1141 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 1142 if (sc->active) { 1143 imx51_ipuv3_initialize(sc, sc->geometry); 1144 imx51_ipuv3_start_dma(sc, sc->active); 1145 } 1146 return true; 1147 } 1148 1149 #if NWSDISPLAY > 0 1150 int 1151 imx51_ipuv3_show_screen(void *v, void *cookie, int waitok, 1152 void (*cb)(void *, int, int), void *cbarg) 1153 { 1154 struct vcons_data *vd = v; 1155 struct imx51_ipuv3_softc *sc = vd->cookie; 1156 struct imx51_ipuv3_screen *scr = cookie, *old; 1157 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 1158 1159 old = sc->active; 1160 if (old == scr) 1161 return 0; 1162 if (old) 1163 imx51_ipuv3_stop_dma(sc); 1164 imx51_ipuv3_start_dma(sc, scr); 1165 sc->active = scr; 1166 return 0; 1167 } 1168 1169 int 1170 imx51_ipuv3_alloc_screen(void *v, const struct wsscreen_descr *_type, 1171 void **cookiep, int *curxp, int *curyp, long *attrp) 1172 { 1173 struct vcons_data *vd = v; 1174 struct imx51_ipuv3_softc *sc = vd->cookie; 1175 struct imx51_ipuv3_screen *scr; 1176 const struct imx51_wsscreen_descr *type = 1177 (const struct imx51_wsscreen_descr *)_type; 1178 int error; 1179 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 1180 1181 error = imx51_ipuv3_new_screen(sc, type->depth, &scr); 1182 if (error) 1183 return error; 1184 1185 /* 1186 * initialize raster operation for this screen. 1187 */ 1188 scr->rinfo.ri_flg = 0; 1189 scr->rinfo.ri_depth = type->depth; 1190 scr->rinfo.ri_bits = scr->buf_va; 1191 scr->rinfo.ri_width = sc->geometry->panel_width; 1192 scr->rinfo.ri_height = sc->geometry->panel_height; 1193 scr->rinfo.ri_stride = scr->rinfo.ri_width * scr->rinfo.ri_depth / 8; 1194 #ifdef CPU_XSCALE_PXA270 1195 if (scr->rinfo.ri_depth > 16) 1196 scr->rinfo.ri_stride = scr->rinfo.ri_width * 4; 1197 #endif 1198 scr->rinfo.ri_wsfcookie = -1; /* XXX */ 1199 1200 rasops_init(&scr->rinfo, type->c.nrows, type->c.ncols); 1201 1202 (*scr->rinfo.ri_ops.allocattr)(&scr->rinfo, 0, 0, 0, attrp); 1203 1204 *cookiep = scr; 1205 *curxp = 0; 1206 *curyp = 0; 1207 1208 return 0; 1209 } 1210 1211 void 1212 imx51_ipuv3_free_screen(void *v, void *cookie) 1213 { 1214 struct vcons_data *vd = v; 1215 struct imx51_ipuv3_softc *sc = vd->cookie; 1216 struct imx51_ipuv3_screen *scr = cookie; 1217 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 1218 1219 LIST_REMOVE(scr, link); 1220 sc->n_screens--; 1221 if (scr == sc->active) { 1222 /* at first, we need to stop LCD DMA */ 1223 sc->active = NULL; 1224 1225 printf("lcd_free on active screen\n"); 1226 1227 imx51_ipuv3_stop_dma(sc); 1228 } 1229 1230 if (scr->buf_va) 1231 bus_dmamem_unmap(sc->dma_tag, scr->buf_va, scr->map_size); 1232 if (scr->nsegs > 0) 1233 bus_dmamem_free(sc->dma_tag, scr->segs, scr->nsegs); 1234 free(scr, M_DEVBUF); 1235 } 1236 1237 int 1238 imx51_ipuv3_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 1239 struct lwp *l) 1240 { 1241 struct vcons_data *vd = v; 1242 struct imx51_ipuv3_softc *sc = vd->cookie; 1243 struct wsdisplay_fbinfo *wsdisp_info; 1244 struct vcons_screen *ms = vd->active; 1245 1246 DPRINTFN(5, ("%s : cmd 0x%X (%d)\n", __func__, (u_int)cmd, (int)IOCGROUP(cmd))); 1247 1248 switch (cmd) { 1249 case WSDISPLAYIO_GTYPE: 1250 *(int *)data = WSDISPLAY_TYPE_IMXIPU; 1251 return 0; 1252 1253 case WSDISPLAYIO_GINFO: 1254 wsdisp_info = (struct wsdisplay_fbinfo *)data; 1255 wsdisp_info->height = ms->scr_ri.ri_height; 1256 wsdisp_info->width = ms->scr_ri.ri_width; 1257 wsdisp_info->depth = ms->scr_ri.ri_depth; 1258 wsdisp_info->cmsize = 0; 1259 return 0; 1260 1261 case WSDISPLAYIO_LINEBYTES: 1262 *(u_int *)data = ms->scr_ri.ri_stride; 1263 return 0; 1264 1265 case WSDISPLAYIO_GETCMAP: 1266 case WSDISPLAYIO_PUTCMAP: 1267 return EPASSTHROUGH; /* XXX Colormap */ 1268 1269 case WSDISPLAYIO_SVIDEO: 1270 if (*(int *)data == WSDISPLAYIO_VIDEO_ON) { 1271 /* turn it on */ 1272 } 1273 else { 1274 /* start IPUV3 shutdown */ 1275 /* sleep until interrupt */ 1276 } 1277 return 0; 1278 1279 case WSDISPLAYIO_GVIDEO: 1280 *(u_int *)data = WSDISPLAYIO_VIDEO_ON; 1281 return 0; 1282 1283 case WSDISPLAYIO_GCURPOS: 1284 case WSDISPLAYIO_SCURPOS: 1285 case WSDISPLAYIO_GCURMAX: 1286 case WSDISPLAYIO_GCURSOR: 1287 case WSDISPLAYIO_SCURSOR: 1288 return EPASSTHROUGH; /* XXX */ 1289 case WSDISPLAYIO_SMODE: 1290 { 1291 int new_mode = *(int*)data; 1292 1293 /* notify the bus backend */ 1294 if (new_mode != sc->mode) { 1295 sc->mode = new_mode; 1296 if(new_mode == WSDISPLAYIO_MODE_EMUL) 1297 vcons_redraw_screen(ms); 1298 } 1299 } 1300 return 0; 1301 } 1302 1303 return EPASSTHROUGH; 1304 } 1305 1306 paddr_t 1307 imx51_ipuv3_mmap(void *v, void *vs, off_t offset, int prot) 1308 { 1309 DPRINTFN(5, ("%s : %d\n", __func__, __LINE__)); 1310 1311 struct vcons_data *vd = v; 1312 struct imx51_ipuv3_softc *sc = vd->cookie; 1313 struct imx51_ipuv3_screen *scr = sc->active; 1314 1315 return bus_dmamem_mmap(sc->dma_tag, scr->segs, scr->nsegs, 1316 offset, prot, 1317 BUS_DMA_WAITOK | BUS_DMA_COHERENT); 1318 } 1319 #endif /* NWSDISPLAY > 0 */ 1320 1321
Indexes created Thu Oct 02 10:09:58 GMT 2025