imx51_ipuv3var.h revision 1.1.2.2
1 1.1.2.2 mrg /* $NetBSD: imx51_ipuv3var.h,v 1.1.2.2 2012/04/29 23:04:38 mrg Exp $ */ 2 1.1.2.2 mrg 3 1.1.2.2 mrg /* 4 1.1.2.2 mrg * Copyright (c) 2009, 2011, 2012 Genetec Corporation. All rights reserved. 5 1.1.2.2 mrg * Written by Hashimoto Kenichi for Genetec Corporation. 6 1.1.2.2 mrg * 7 1.1.2.2 mrg * Redistribution and use in source and binary forms, with or without 8 1.1.2.2 mrg * modification, are permitted provided that the following conditions 9 1.1.2.2 mrg * are met: 10 1.1.2.2 mrg * 1. Redistributions of source code must retain the above copyright 11 1.1.2.2 mrg * notice, this list of conditions and the following disclaimer. 12 1.1.2.2 mrg * 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 mrg * notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 mrg * documentation and/or other materials provided with the distribution. 15 1.1.2.2 mrg * 16 1.1.2.2 mrg * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 17 1.1.2.2 mrg * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 1.1.2.2 mrg * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 1.1.2.2 mrg * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 20 1.1.2.2 mrg * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 1.1.2.2 mrg * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 1.1.2.2 mrg * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 1.1.2.2 mrg * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 1.1.2.2 mrg * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 1.1.2.2 mrg * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 1.1.2.2 mrg * POSSIBILITY OF SUCH DAMAGE. 27 1.1.2.2 mrg */ 28 1.1.2.2 mrg 29 1.1.2.2 mrg 30 1.1.2.2 mrg #ifndef _ARM_IMX_IMX51_IPUV3_H 31 1.1.2.2 mrg #define _ARM_IMX_IMX51_IPUV3_H 32 1.1.2.2 mrg 33 1.1.2.2 mrg #include <sys/bus.h> 34 1.1.2.2 mrg #include <dev/rasops/rasops.h> 35 1.1.2.2 mrg #include <dev/wscons/wsdisplay_vconsvar.h> 36 1.1.2.2 mrg 37 1.1.2.2 mrg /* IPUV3 Contoroller */ 38 1.1.2.2 mrg struct imx51_ipuv3_screen { 39 1.1.2.2 mrg LIST_ENTRY(imx51_ipuv3_screen) link; 40 1.1.2.2 mrg 41 1.1.2.2 mrg /* Frame buffer */ 42 1.1.2.2 mrg bus_dmamap_t dma; 43 1.1.2.2 mrg bus_dma_segment_t segs[1]; 44 1.1.2.2 mrg int nsegs; 45 1.1.2.2 mrg size_t buf_size; 46 1.1.2.2 mrg size_t map_size; 47 1.1.2.2 mrg void *buf_va; 48 1.1.2.2 mrg int depth; 49 1.1.2.2 mrg int stride; 50 1.1.2.2 mrg 51 1.1.2.2 mrg /* DMA frame descriptor */ 52 1.1.2.2 mrg struct ipuv3_dma_descriptor *dma_desc; 53 1.1.2.2 mrg paddr_t dma_desc_pa; 54 1.1.2.2 mrg }; 55 1.1.2.2 mrg 56 1.1.2.2 mrg struct lcd_panel_geometry { 57 1.1.2.2 mrg short panel_width; 58 1.1.2.2 mrg short panel_height; 59 1.1.2.2 mrg 60 1.1.2.2 mrg uint32_t pixel_clk; 61 1.1.2.2 mrg 62 1.1.2.2 mrg short hsync_width; 63 1.1.2.2 mrg short left; 64 1.1.2.2 mrg short right; 65 1.1.2.2 mrg 66 1.1.2.2 mrg short vsync_width; 67 1.1.2.2 mrg short upper; 68 1.1.2.2 mrg short lower; 69 1.1.2.2 mrg 70 1.1.2.2 mrg short panel_info; 71 1.1.2.2 mrg #define IPUV3PANEL_SHARP (1<<0) /* sharp panel */ 72 1.1.2.2 mrg uint32_t panel_sig_pol; 73 1.1.2.2 mrg }; 74 1.1.2.2 mrg 75 1.1.2.2 mrg struct imx51_ipuv3_softc { 76 1.1.2.2 mrg device_t dev; 77 1.1.2.2 mrg 78 1.1.2.2 mrg /* control register */ 79 1.1.2.2 mrg bus_space_tag_t iot; 80 1.1.2.2 mrg bus_space_handle_t cm_ioh; /* CM */ 81 1.1.2.2 mrg bus_space_handle_t dmfc_ioh; /* DMFC */ 82 1.1.2.2 mrg bus_space_handle_t di0_ioh; /* DI 0 */ 83 1.1.2.2 mrg bus_space_handle_t dp_ioh; /* DP */ 84 1.1.2.2 mrg bus_space_handle_t dc_ioh; /* DC */ 85 1.1.2.2 mrg bus_space_handle_t idmac_ioh; /* IDMAC */ 86 1.1.2.2 mrg bus_space_handle_t cpmem_ioh; /* CPMEM */ 87 1.1.2.2 mrg bus_space_handle_t dctmpl_ioh; /* DCTMPL */ 88 1.1.2.2 mrg bus_dma_tag_t dma_tag; 89 1.1.2.2 mrg 90 1.1.2.2 mrg uint32_t flags; 91 1.1.2.2 mrg #define FLAG_NOUSE_ACBIAS (1U<<0) 92 1.1.2.2 mrg 93 1.1.2.2 mrg const struct lcd_panel_geometry *geometry; 94 1.1.2.2 mrg 95 1.1.2.2 mrg int n_screens; 96 1.1.2.2 mrg LIST_HEAD(, imx51_ipuv3_screen) screens; 97 1.1.2.2 mrg struct imx51_ipuv3_screen *active; 98 1.1.2.2 mrg void *ih; /* interrupt handler */ 99 1.1.2.2 mrg 100 1.1.2.2 mrg /* virtual console support */ 101 1.1.2.2 mrg struct vcons_data vd; 102 1.1.2.2 mrg struct vcons_screen console; 103 1.1.2.2 mrg int mode; 104 1.1.2.2 mrg }; 105 1.1.2.2 mrg 106 1.1.2.2 mrg /* 107 1.1.2.2 mrg * we need bits-per-pixel value to configure wsdisplay screen 108 1.1.2.2 mrg */ 109 1.1.2.2 mrg struct imx51_wsscreen_descr { 110 1.1.2.2 mrg struct wsscreen_descr c; /* standard descriptor */ 111 1.1.2.2 mrg int depth; /* bits per pixel */ 112 1.1.2.2 mrg int flags; /* rasops flags */ 113 1.1.2.2 mrg }; 114 1.1.2.2 mrg 115 1.1.2.2 mrg struct imx51_ipuv3_softc; 116 1.1.2.2 mrg 117 1.1.2.2 mrg void imx51_ipuv3_attach_sub(struct imx51_ipuv3_softc *, 118 1.1.2.2 mrg struct axi_attach_args *, const struct lcd_panel_geometry *); 119 1.1.2.2 mrg int imx51_ipuv3_cnattach(const struct lcd_panel_geometry *); 120 1.1.2.2 mrg void imx51_ipuv3_start_dma(struct imx51_ipuv3_softc *, 121 1.1.2.2 mrg struct imx51_ipuv3_screen *); 122 1.1.2.2 mrg 123 1.1.2.2 mrg void imx51_ipuv3_geometry(struct imx51_ipuv3_softc *, 124 1.1.2.2 mrg const struct lcd_panel_geometry *); 125 1.1.2.2 mrg int imx51_ipuv3_new_screen(struct imx51_ipuv3_softc *, int, 126 1.1.2.2 mrg struct imx51_ipuv3_screen **); 127 1.1.2.2 mrg 128 1.1.2.2 mrg int imx51_ipuv3_ioctl(void *, void *, u_long, void *, int, struct lwp *); 129 1.1.2.2 mrg paddr_t imx51_ipuv3_mmap(void *, void *, off_t, int); 130 1.1.2.2 mrg 131 1.1.2.2 mrg void imx51_ipuv3_power(int, void *); 132 1.1.2.2 mrg void imx51_ipuv3_suspend(struct imx51_ipuv3_softc *); 133 1.1.2.2 mrg void imx51_ipuv3_resume(struct imx51_ipuv3_softc *); 134 1.1.2.2 mrg 135 1.1.2.2 mrg extern const struct wsdisplay_emulops imx51_ipuv3_emulops; 136 1.1.2.2 mrg 137 1.1.2.2 mrg #endif /* _ARM_IMX_IMX51_IPUV3_H */ 138
Indexes created Fri Oct 03 02:09:57 GMT 2025