Home | History | Annotate | Line # | Download | only in imx
imx51_tzic.c revision 1.4.16.1
      1  1.4.16.1   rmind /*	$NetBSD: imx51_tzic.c,v 1.4.16.1 2014/05/18 17:44:58 rmind Exp $	*/
      2       1.1     bsh 
      3       1.1     bsh /*-
      4       1.1     bsh  * Copyright (c) 2010 SHIMIZU Ryo <ryo (at) nerv.org>
      5       1.1     bsh  * All rights reserved.
      6       1.1     bsh  *
      7       1.1     bsh  * Redistribution and use in source and binary forms, with or without
      8       1.1     bsh  * modification, are permitted provided that the following conditions
      9       1.1     bsh  * are met:
     10       1.1     bsh  * 1. Redistributions of source code must retain the above copyright
     11       1.1     bsh  *    notice, this list of conditions and the following disclaimer.
     12       1.1     bsh  * 2. Redistributions in binary form must reproduce the above copyright
     13       1.1     bsh  *    notice, this list of conditions and the following disclaimer in the
     14       1.1     bsh  *    documentation and/or other materials provided with the distribution.
     15       1.1     bsh  *
     16       1.1     bsh  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17       1.1     bsh  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     18       1.1     bsh  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     19       1.1     bsh  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
     20       1.1     bsh  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     21       1.1     bsh  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     22       1.1     bsh  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     23       1.1     bsh  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
     24       1.1     bsh  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
     25       1.1     bsh  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     26       1.1     bsh  * POSSIBILITY OF SUCH DAMAGE.
     27       1.1     bsh  */
     28       1.1     bsh #include <sys/cdefs.h>
     29  1.4.16.1   rmind __KERNEL_RCSID(0, "$NetBSD: imx51_tzic.c,v 1.4.16.1 2014/05/18 17:44:58 rmind Exp $");
     30       1.1     bsh 
     31       1.1     bsh #define	_INTR_PRIVATE	/* for arm/pic/picvar.h */
     32       1.1     bsh 
     33       1.1     bsh #include "locators.h"
     34       1.1     bsh 
     35       1.1     bsh #include <sys/param.h>
     36       1.1     bsh #include <sys/evcnt.h>
     37       1.1     bsh #include <sys/device.h>
     38       1.1     bsh #include <sys/atomic.h>
     39       1.1     bsh 
     40       1.1     bsh #include <machine/intr.h>
     41       1.3  dyoung #include <sys/bus.h>
     42       1.1     bsh 
     43       1.1     bsh #include <uvm/uvm_extern.h>
     44       1.1     bsh 
     45       1.1     bsh #include <arm/cpu.h>
     46       1.1     bsh #include <arm/armreg.h>
     47       1.1     bsh #include <arm/cpufunc.h>
     48       1.1     bsh 
     49       1.1     bsh #include <machine/autoconf.h>
     50       1.1     bsh 
     51       1.1     bsh #include <arm/imx/imx51reg.h>
     52       1.1     bsh #include <arm/imx/imx51var.h>
     53       1.1     bsh #include <arm/imx/imx51_tzicreg.h>
     54       1.1     bsh 
     55       1.1     bsh static int tzic_match(device_t, cfdata_t, void *);
     56       1.1     bsh static void tzic_attach(device_t, device_t, void *);
     57       1.1     bsh 
     58       1.1     bsh /* for arm/pic */
     59       1.1     bsh static void tzic_unblock_irqs(struct pic_softc *, size_t, uint32_t);
     60       1.1     bsh static void tzic_block_irqs(struct pic_softc *, size_t, uint32_t);
     61       1.1     bsh static void tzic_establish_irq(struct pic_softc *, struct intrsource *);
     62       1.1     bsh static void tzic_source_name(struct pic_softc *, int, char *, size_t);
     63       1.1     bsh 
     64       1.1     bsh struct tzic_softc {
     65       1.1     bsh 	device_t sc_dev;
     66       1.1     bsh 	struct pic_softc sc_pic;
     67       1.1     bsh 	bus_space_tag_t sc_iot;
     68       1.1     bsh 	bus_space_handle_t sc_ioh;
     69       1.1     bsh 	uint32_t sc_enabled_mask[4];
     70       1.1     bsh };
     71       1.1     bsh 
     72       1.1     bsh const struct pic_ops tzic_pic_ops = {
     73       1.1     bsh 	.pic_unblock_irqs = tzic_unblock_irqs,
     74       1.1     bsh 	.pic_block_irqs = tzic_block_irqs,
     75       1.1     bsh 	.pic_establish_irq = tzic_establish_irq,
     76       1.1     bsh 	.pic_source_name = tzic_source_name
     77       1.1     bsh };
     78       1.1     bsh 
     79       1.1     bsh static void tzic_intr_init(struct tzic_softc * const);
     80       1.1     bsh 
     81       1.1     bsh static const char * const tzic_intr_source_names[] = TZIC_INTR_SOURCE_NAMES;
     82       1.1     bsh 
     83       1.1     bsh extern struct cfdriver tzic_cd;
     84       1.1     bsh 
     85       1.1     bsh #define	PIC_TO_SOFTC(pic) \
     86       1.1     bsh 	((struct tzic_softc *)((char *)(pic) - \
     87       1.1     bsh 		offsetof(struct tzic_softc, sc_pic)))
     88       1.1     bsh 
     89       1.1     bsh #define	INTC_READ(tzic, reg) \
     90       1.1     bsh 	bus_space_read_4((tzic)->sc_iot, (tzic)->sc_ioh, (reg))
     91       1.1     bsh #define	INTC_WRITE(tzic, reg, val) \
     92       1.1     bsh 	bus_space_write_4((tzic)->sc_iot, (tzic)->sc_ioh, (reg), (val))
     93       1.1     bsh 
     94       1.1     bsh /* use [7:4] of interrupt priority.
     95       1.1     bsh  * 0 is the highest priority.
     96       1.1     bsh  */
     97       1.1     bsh #define	HW_TO_SW_IPL(ipl)	(IPL_HIGH - ((ipl) >> 3))
     98       1.1     bsh #define	SW_TO_HW_IPL(ipl)	((IPL_HIGH - (ipl)) << 3)
     99       1.1     bsh 
    100       1.1     bsh CFATTACH_DECL_NEW(tzic, sizeof(struct tzic_softc),
    101       1.1     bsh     tzic_match, tzic_attach, NULL, NULL);
    102       1.1     bsh 
    103       1.1     bsh struct tzic_softc *tzic_softc;
    104       1.1     bsh 
    105       1.1     bsh int
    106       1.1     bsh tzic_match(device_t parent, cfdata_t self, void *aux)
    107       1.1     bsh {
    108       1.1     bsh 	struct axi_attach_args *aa;
    109       1.1     bsh 
    110       1.1     bsh 	aa = aux;
    111       1.1     bsh 
    112       1.1     bsh 	if (aa->aa_addr != TZIC_BASE)
    113       1.1     bsh 		return 0;
    114       1.1     bsh 
    115       1.1     bsh 	return 1;
    116       1.1     bsh }
    117       1.1     bsh 
    118       1.1     bsh void
    119       1.1     bsh tzic_attach(device_t parent, device_t self, void *aux)
    120       1.1     bsh {
    121       1.1     bsh 	struct tzic_softc *tzic = device_private(self);
    122       1.1     bsh 	struct axi_attach_args * const aa = aux;
    123       1.1     bsh 	int error;
    124       1.1     bsh 
    125       1.1     bsh 	KASSERT(aa->aa_irqbase != AXICF_IRQBASE_DEFAULT);
    126       1.1     bsh 	KASSERT(self->dv_unit == 0);
    127       1.1     bsh 
    128       1.1     bsh 	aprint_normal(": TrustZone Interrupt Controller\n");
    129       1.1     bsh 	aprint_naive("\n");
    130       1.1     bsh 
    131       1.1     bsh 	tzic->sc_dev = self;
    132       1.1     bsh 	tzic->sc_iot = aa->aa_iot;
    133       1.1     bsh 
    134       1.1     bsh 	tzic_softc = tzic;
    135       1.1     bsh 
    136       1.1     bsh 	if (aa->aa_size == AXICF_SIZE_DEFAULT)
    137       1.1     bsh 		aa->aa_size = TZIC_SIZE;
    138       1.1     bsh 
    139       1.1     bsh 	error = bus_space_map(tzic->sc_iot, aa->aa_addr, aa->aa_size, 0, &tzic->sc_ioh);
    140       1.1     bsh 
    141       1.1     bsh 	if (error) {
    142       1.1     bsh 		panic("tzic_attach: failed to map register %#x-%#x: %d",
    143       1.1     bsh 		    (uint32_t)aa->aa_addr,
    144       1.1     bsh 		    (uint32_t)(aa->aa_addr + aa->aa_size - 1),
    145       1.1     bsh 		    error);
    146       1.1     bsh 	}
    147       1.1     bsh 
    148       1.1     bsh 	tzic_intr_init(tzic);
    149       1.1     bsh 
    150       1.1     bsh 	tzic->sc_pic.pic_ops = &tzic_pic_ops;
    151       1.1     bsh 	tzic->sc_pic.pic_maxsources = TZIC_INTNUM;
    152       1.1     bsh 	strlcpy(tzic->sc_pic.pic_name, device_xname(self),
    153       1.1     bsh 	    sizeof(tzic->sc_pic.pic_name));
    154       1.1     bsh 
    155       1.1     bsh 	pic_add(&tzic->sc_pic, aa->aa_irqbase);
    156       1.1     bsh 
    157       1.1     bsh 	aprint_normal_dev(tzic->sc_dev, "interrupts %d..%d  register VA:%p\n",
    158       1.1     bsh 	    aa->aa_irqbase, aa->aa_irqbase + TZIC_INTNUM,
    159       1.1     bsh 	    (void *)tzic->sc_ioh);
    160       1.1     bsh 
    161       1.1     bsh 	/* Everything is all set.  Enable the interrupts. */
    162       1.1     bsh 	enable_interrupts(I32_bit|F32_bit);
    163       1.1     bsh }
    164       1.1     bsh 
    165       1.1     bsh 
    166       1.1     bsh void
    167       1.1     bsh tzic_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
    168       1.1     bsh {
    169       1.1     bsh 	struct tzic_softc * const tzic = PIC_TO_SOFTC(pic);
    170       1.1     bsh 	const size_t group = irq_base / 32;
    171       1.1     bsh 
    172       1.1     bsh 	KASSERT((irq_mask & tzic->sc_enabled_mask[group]) == 0);
    173       1.1     bsh 
    174       1.1     bsh 	tzic->sc_enabled_mask[group] |= irq_mask;
    175       1.1     bsh 	INTC_WRITE(tzic, TZIC_ENSET(group), irq_mask);
    176       1.1     bsh }
    177       1.1     bsh 
    178       1.1     bsh void
    179       1.1     bsh tzic_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
    180       1.1     bsh {
    181       1.1     bsh 	struct tzic_softc * const tzic = PIC_TO_SOFTC(pic);
    182       1.1     bsh 	const size_t group = irq_base / 32;
    183       1.1     bsh 
    184       1.1     bsh 	tzic->sc_enabled_mask[group] &= ~irq_mask;
    185       1.1     bsh 
    186       1.1     bsh 	INTC_WRITE(tzic, TZIC_ENCLEAR(group), irq_mask);
    187       1.1     bsh }
    188       1.1     bsh 
    189       1.1     bsh /*
    190       1.1     bsh  * Called with interrupts disabled
    191       1.1     bsh  */
    192       1.1     bsh static int
    193       1.1     bsh find_pending_irqs(struct tzic_softc *tzic, size_t group)
    194       1.1     bsh {
    195       1.1     bsh 	uint32_t pending = 0;
    196       1.1     bsh 
    197       1.1     bsh 	KASSERT( group <= 3 );
    198       1.1     bsh 
    199       1.1     bsh 	pending = INTC_READ(tzic, TZIC_PND(group));
    200       1.1     bsh 
    201       1.1     bsh 	KASSERT((tzic->sc_enabled_mask[group] & pending) == pending);
    202       1.1     bsh 
    203       1.1     bsh 	if (pending == 0)
    204       1.1     bsh 		return 0;
    205       1.1     bsh 
    206       1.1     bsh 	return pic_mark_pending_sources(&tzic->sc_pic, group * 32, pending);
    207       1.1     bsh }
    208       1.1     bsh 
    209       1.1     bsh void
    210       1.1     bsh tzic_establish_irq(struct pic_softc *pic, struct intrsource *is)
    211       1.1     bsh {
    212       1.1     bsh 	struct tzic_softc * const tzic = PIC_TO_SOFTC(pic);
    213       1.1     bsh 	int priority_shift;
    214       1.1     bsh 	int priority_offset;
    215       1.1     bsh 	uint32_t reg;
    216       1.1     bsh 
    217       1.1     bsh 	KASSERT(is->is_irq < 128);
    218       1.1     bsh 	KASSERT(is->is_ipl < 16);
    219       1.1     bsh 	KASSERT(is->is_type == IST_LEVEL);
    220       1.1     bsh 
    221       1.1     bsh 	priority_shift = (is->is_irq % 4) * 8;
    222       1.1     bsh 	priority_offset = (is->is_irq / 4);
    223       1.1     bsh 	reg = INTC_READ(tzic, TZIC_PRIORITY(priority_offset));
    224       1.1     bsh 	reg &= ~(0xff << priority_shift);
    225       1.1     bsh 	reg |= SW_TO_HW_IPL(is->is_ipl) << priority_shift;
    226       1.1     bsh 	INTC_WRITE(tzic, TZIC_PRIORITY(priority_offset), reg);
    227       1.1     bsh }
    228       1.1     bsh 
    229       1.1     bsh void
    230       1.1     bsh tzic_source_name(struct pic_softc *pic, int irq, char *buf, size_t len)
    231       1.1     bsh {
    232       1.1     bsh 	strlcpy(buf, tzic_intr_source_names[irq], len);
    233       1.1     bsh }
    234       1.1     bsh 
    235       1.1     bsh void
    236       1.1     bsh imx51_irq_handler(void *frame)
    237       1.1     bsh {
    238       1.1     bsh 	struct cpu_info * const ci = curcpu();
    239       1.1     bsh 	const int oldipl = ci->ci_cpl;
    240       1.1     bsh 	const uint32_t oldipl_mask = __BIT(oldipl);
    241       1.1     bsh 	int ipl_mask = 0;
    242       1.1     bsh 
    243       1.2    matt 	ci->ci_data.cpu_nintr++;
    244       1.1     bsh 
    245       1.1     bsh 	if (tzic_softc->sc_enabled_mask[0])
    246       1.1     bsh 		ipl_mask |= find_pending_irqs(tzic_softc, 0);
    247       1.1     bsh 	if (tzic_softc->sc_enabled_mask[1])
    248       1.1     bsh 		ipl_mask |= find_pending_irqs(tzic_softc, 1);
    249       1.1     bsh 	if (tzic_softc->sc_enabled_mask[2])
    250       1.1     bsh 		ipl_mask |= find_pending_irqs(tzic_softc, 2);
    251       1.1     bsh 	if (tzic_softc->sc_enabled_mask[3])
    252       1.1     bsh 		ipl_mask |= find_pending_irqs(tzic_softc, 3);
    253       1.1     bsh 
    254       1.1     bsh 	if ((ipl_mask & ~oldipl_mask) > oldipl_mask)
    255       1.1     bsh 		pic_do_pending_ints(I32_bit, oldipl, frame);
    256       1.1     bsh }
    257       1.1     bsh 
    258       1.1     bsh static void
    259       1.1     bsh tzic_intr_init(struct tzic_softc * const tzic)
    260       1.1     bsh {
    261       1.1     bsh 	int i;
    262       1.1     bsh 
    263       1.1     bsh 	disable_interrupts(I32_bit|F32_bit);
    264       1.1     bsh 
    265  1.4.16.1   rmind 	(void) INTC_READ(tzic, TZIC_INTCNTL);
    266       1.1     bsh 	INTC_WRITE(tzic, TZIC_INTCNTL, INTCNTL_NSEN_MASK|INTCNTL_NSEN|INTCNTL_EN);
    267  1.4.16.1   rmind 	(void) INTC_READ(tzic, TZIC_INTCNTL);
    268       1.1     bsh 	INTC_WRITE(tzic, TZIC_PRIOMASK, SW_TO_HW_IPL(IPL_NONE));
    269  1.4.16.1   rmind 	(void) INTC_READ(tzic, TZIC_PRIOMASK);
    270       1.1     bsh 
    271       1.1     bsh 	INTC_WRITE(tzic, TZIC_SYNCCTRL, 0x00);
    272  1.4.16.1   rmind 	(void) INTC_READ(tzic, TZIC_SYNCCTRL);
    273       1.1     bsh 
    274       1.1     bsh 	/* route all interrupts to IRQ.  secure interrupts are for FIQ */
    275       1.1     bsh 	for (i = 0; i < 4; i++)
    276       1.1     bsh 		INTC_WRITE(tzic, TZIC_INTSEC(i), 0xffffffff);
    277       1.1     bsh 
    278       1.1     bsh 	/* disable all interrupts */
    279       1.1     bsh 	for (i = 0; i < 4; i++)
    280       1.1     bsh 		INTC_WRITE(tzic, TZIC_ENCLEAR(i), 0xffffffff);
    281       1.1     bsh 
    282       1.1     bsh }
    283