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imxclock.c revision 1.2.22.1
      1  1.2.22.1  rmind /*	$NetBSD: imxclock.c,v 1.2.22.1 2011/03/05 20:49:35 rmind Exp $ */
      2  1.2.22.1  rmind /*
      3  1.2.22.1  rmind  * Copyright (c) 2009, 2010  Genetec corp.  All rights reserved.
      4  1.2.22.1  rmind  * Written by Hashimoto Kenichi for Genetec corp.
      5  1.2.22.1  rmind  *
      6  1.2.22.1  rmind  * Redistribution and use in source and binary forms, with or without
      7  1.2.22.1  rmind  * modification, are permitted provided that the following conditions
      8  1.2.22.1  rmind  * are met:
      9  1.2.22.1  rmind  * 1. Redistributions of source code must retain the above copyright
     10  1.2.22.1  rmind  *    notice, this list of conditions and the following disclaimer.
     11  1.2.22.1  rmind  * 2. Redistributions in binary form must reproduce the above copyright
     12  1.2.22.1  rmind  *    notice, this list of conditions and the following disclaimer in the
     13  1.2.22.1  rmind  *    documentation and/or other materials provided with the distribution.
     14  1.2.22.1  rmind  *
     15  1.2.22.1  rmind  * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
     16  1.2.22.1  rmind  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     17  1.2.22.1  rmind  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     18  1.2.22.1  rmind  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORP.
     19  1.2.22.1  rmind  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     20  1.2.22.1  rmind  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     21  1.2.22.1  rmind  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     22  1.2.22.1  rmind  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     23  1.2.22.1  rmind  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     24  1.2.22.1  rmind  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     25  1.2.22.1  rmind  * POSSIBILITY OF SUCH DAMAGE.
     26  1.2.22.1  rmind  */
     27  1.2.22.1  rmind 
     28  1.2.22.1  rmind /*
     29  1.2.22.1  rmind  * common part for i.MX31 and i.MX51
     30  1.2.22.1  rmind  */
     31  1.2.22.1  rmind 
     32  1.2.22.1  rmind #include <sys/param.h>
     33  1.2.22.1  rmind #include <sys/systm.h>
     34  1.2.22.1  rmind #include <sys/kernel.h>
     35  1.2.22.1  rmind #include <sys/evcnt.h>
     36  1.2.22.1  rmind #include <sys/atomic.h>
     37       1.2   matt #include <sys/time.h>
     38  1.2.22.1  rmind #include <sys/timetc.h>
     39  1.2.22.1  rmind 
     40  1.2.22.1  rmind #include <sys/types.h>
     41  1.2.22.1  rmind #include <sys/device.h>
     42  1.2.22.1  rmind 
     43  1.2.22.1  rmind #include <machine/intr.h>
     44  1.2.22.1  rmind #include <machine/bus.h>
     45  1.2.22.1  rmind 
     46  1.2.22.1  rmind #include <arm/cpu.h>
     47  1.2.22.1  rmind #include <arm/armreg.h>
     48  1.2.22.1  rmind #include <arm/cpufunc.h>
     49  1.2.22.1  rmind 
     50  1.2.22.1  rmind #include <arm/imx/imxclockvar.h>
     51  1.2.22.1  rmind #include <arm/imx/imxepitreg.h>
     52  1.2.22.1  rmind 
     53  1.2.22.1  rmind static u_int imx_epit_get_timecount(struct timecounter *);
     54  1.2.22.1  rmind static int imxclock_intr(void *);
     55  1.2.22.1  rmind 
     56  1.2.22.1  rmind static struct timecounter imx_epit_timecounter = {
     57  1.2.22.1  rmind 	imx_epit_get_timecount,	/* get_timecount */
     58  1.2.22.1  rmind 	0,			/* no poll_pps */
     59  1.2.22.1  rmind 	0xffffffff,		/* counter_mask */
     60  1.2.22.1  rmind 	0,			/* frequency */
     61  1.2.22.1  rmind 	"epit",			/* name */
     62  1.2.22.1  rmind 	100,			/* quality */
     63  1.2.22.1  rmind 	NULL,			/* prev */
     64  1.2.22.1  rmind 	NULL,			/* next */
     65  1.2.22.1  rmind };
     66  1.2.22.1  rmind 
     67  1.2.22.1  rmind static volatile uint32_t imxclock_base;
     68       1.2   matt 
     69       1.2   matt void
     70       1.2   matt cpu_initclocks(void)
     71       1.2   matt {
     72  1.2.22.1  rmind 	uint32_t reg;
     73  1.2.22.1  rmind 	int freq;
     74  1.2.22.1  rmind 
     75  1.2.22.1  rmind 	if (!epit1_sc) {
     76  1.2.22.1  rmind 		panic("%s: driver has not been initialized!", __FUNCTION__);
     77  1.2.22.1  rmind 	}
     78  1.2.22.1  rmind 
     79  1.2.22.1  rmind 	freq = imxclock_get_timerfreq(epit1_sc);
     80  1.2.22.1  rmind 	imx_epit_timecounter.tc_frequency = freq;
     81  1.2.22.1  rmind 	tc_init(&imx_epit_timecounter);
     82  1.2.22.1  rmind 
     83  1.2.22.1  rmind 	epit1_sc->sc_reload_value = freq / hz - 1;
     84  1.2.22.1  rmind 
     85  1.2.22.1  rmind 	/* stop all timers */
     86  1.2.22.1  rmind 	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCR, 0);
     87  1.2.22.1  rmind 	bus_space_write_4(epit2_sc->sc_iot, epit2_sc->sc_ioh, EPIT_EPITCR, 0);
     88  1.2.22.1  rmind 
     89  1.2.22.1  rmind 	aprint_normal("clock: hz=%d stathz = %d\n", hz, stathz);
     90  1.2.22.1  rmind 
     91  1.2.22.1  rmind 	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITLR,
     92  1.2.22.1  rmind 			  epit1_sc->sc_reload_value);
     93  1.2.22.1  rmind 	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCMPR, 0);
     94  1.2.22.1  rmind 
     95  1.2.22.1  rmind 	reg = EPITCR_ENMOD | EPITCR_IOVW | EPITCR_RLD;
     96  1.2.22.1  rmind 	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCR, reg);
     97  1.2.22.1  rmind 	reg |= EPITCR_EN | EPITCR_OCIEN | EPITCR_CLKSRC_HIGH |
     98  1.2.22.1  rmind 		EPITCR_WAITEN | EPITCR_DOZEN | EPITCR_STOPEN;
     99  1.2.22.1  rmind 	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCR, reg);
    100  1.2.22.1  rmind 
    101  1.2.22.1  rmind 	epit1_sc->sc_ih = intr_establish(epit1_sc->sc_intr, IPL_CLOCK,
    102  1.2.22.1  rmind 	    IST_LEVEL, imxclock_intr, epit1_sc);
    103       1.2   matt }
    104       1.2   matt 
    105       1.2   matt #if 0
    106       1.2   matt void
    107       1.2   matt microtime(struct timeval *tvp)
    108       1.2   matt {
    109       1.2   matt }
    110       1.2   matt #endif
    111       1.2   matt 
    112       1.2   matt void
    113       1.2   matt setstatclockrate(int schz)
    114       1.2   matt {
    115       1.2   matt }
    116  1.2.22.1  rmind 
    117  1.2.22.1  rmind static int
    118  1.2.22.1  rmind imxclock_intr(void *arg)
    119  1.2.22.1  rmind {
    120  1.2.22.1  rmind 	struct imxclock_softc *sc = arg;
    121  1.2.22.1  rmind 
    122  1.2.22.1  rmind 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, EPIT_EPITSR, 1);
    123  1.2.22.1  rmind 	atomic_add_32(&imxclock_base, sc->sc_reload_value);
    124  1.2.22.1  rmind 
    125  1.2.22.1  rmind 	hardclock((struct clockframe *)arg);
    126  1.2.22.1  rmind 
    127  1.2.22.1  rmind 	return 1;
    128  1.2.22.1  rmind }
    129  1.2.22.1  rmind 
    130  1.2.22.1  rmind u_int
    131  1.2.22.1  rmind imx_epit_get_timecount(struct timecounter *tc)
    132  1.2.22.1  rmind {
    133  1.2.22.1  rmind 	uint32_t counter;
    134  1.2.22.1  rmind 	uint32_t base;
    135  1.2.22.1  rmind 	u_int oldirqstate;
    136  1.2.22.1  rmind 
    137  1.2.22.1  rmind 	oldirqstate = disable_interrupts(I32_bit);
    138  1.2.22.1  rmind 	counter = bus_space_read_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCNT);
    139  1.2.22.1  rmind 	base = imxclock_base;
    140  1.2.22.1  rmind 	restore_interrupts(oldirqstate);
    141  1.2.22.1  rmind 
    142  1.2.22.1  rmind 	return base - counter;
    143  1.2.22.1  rmind }
    144