Home | History | Annotate | Line # | Download | only in imx
imxclock.c revision 1.4.6.2
      1  1.4.6.2     mrg /*	$NetBSD: imxclock.c,v 1.4.6.2 2012/06/02 11:08:53 mrg Exp $ */
      2      1.3     bsh /*
      3      1.3     bsh  * Copyright (c) 2009, 2010  Genetec corp.  All rights reserved.
      4      1.3     bsh  * Written by Hashimoto Kenichi for Genetec corp.
      5      1.3     bsh  *
      6      1.3     bsh  * Redistribution and use in source and binary forms, with or without
      7      1.3     bsh  * modification, are permitted provided that the following conditions
      8      1.3     bsh  * are met:
      9      1.3     bsh  * 1. Redistributions of source code must retain the above copyright
     10      1.3     bsh  *    notice, this list of conditions and the following disclaimer.
     11      1.3     bsh  * 2. Redistributions in binary form must reproduce the above copyright
     12      1.3     bsh  *    notice, this list of conditions and the following disclaimer in the
     13      1.3     bsh  *    documentation and/or other materials provided with the distribution.
     14      1.3     bsh  *
     15      1.3     bsh  * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
     16      1.3     bsh  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     17      1.3     bsh  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     18      1.3     bsh  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORP.
     19      1.3     bsh  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     20      1.3     bsh  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     21      1.3     bsh  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     22      1.3     bsh  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     23      1.3     bsh  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     24      1.3     bsh  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     25      1.3     bsh  * POSSIBILITY OF SUCH DAMAGE.
     26      1.3     bsh  */
     27      1.3     bsh 
     28      1.3     bsh /*
     29      1.3     bsh  * common part for i.MX31 and i.MX51
     30      1.3     bsh  */
     31      1.3     bsh 
     32      1.3     bsh #include <sys/param.h>
     33      1.3     bsh #include <sys/systm.h>
     34      1.3     bsh #include <sys/kernel.h>
     35      1.3     bsh #include <sys/evcnt.h>
     36      1.3     bsh #include <sys/atomic.h>
     37      1.3     bsh #include <sys/time.h>
     38      1.3     bsh #include <sys/timetc.h>
     39      1.3     bsh 
     40      1.2    matt #include <sys/types.h>
     41      1.3     bsh #include <sys/device.h>
     42      1.3     bsh 
     43      1.3     bsh #include <machine/intr.h>
     44      1.4  dyoung #include <sys/bus.h>
     45      1.3     bsh 
     46      1.3     bsh #include <arm/cpu.h>
     47      1.3     bsh #include <arm/armreg.h>
     48      1.3     bsh #include <arm/cpufunc.h>
     49      1.3     bsh 
     50      1.3     bsh #include <arm/imx/imxclockvar.h>
     51      1.3     bsh #include <arm/imx/imxepitreg.h>
     52      1.3     bsh 
     53      1.3     bsh static u_int imx_epit_get_timecount(struct timecounter *);
     54      1.3     bsh static int imxclock_intr(void *);
     55      1.3     bsh 
     56      1.3     bsh static struct timecounter imx_epit_timecounter = {
     57      1.3     bsh 	imx_epit_get_timecount,	/* get_timecount */
     58      1.3     bsh 	0,			/* no poll_pps */
     59      1.3     bsh 	0xffffffff,		/* counter_mask */
     60      1.3     bsh 	0,			/* frequency */
     61      1.3     bsh 	"epit",			/* name */
     62      1.3     bsh 	100,			/* quality */
     63      1.3     bsh 	NULL,			/* prev */
     64      1.3     bsh 	NULL,			/* next */
     65      1.3     bsh };
     66      1.3     bsh 
     67      1.3     bsh static volatile uint32_t imxclock_base;
     68      1.2    matt 
     69      1.2    matt void
     70      1.2    matt cpu_initclocks(void)
     71      1.2    matt {
     72      1.3     bsh 	uint32_t reg;
     73  1.4.6.1     mrg 	u_int freq;
     74      1.3     bsh 
     75      1.3     bsh 	if (!epit1_sc) {
     76      1.3     bsh 		panic("%s: driver has not been initialized!", __FUNCTION__);
     77      1.3     bsh 	}
     78      1.3     bsh 
     79      1.3     bsh 	freq = imxclock_get_timerfreq(epit1_sc);
     80      1.3     bsh 	imx_epit_timecounter.tc_frequency = freq;
     81      1.3     bsh 	tc_init(&imx_epit_timecounter);
     82      1.3     bsh 
     83  1.4.6.1     mrg 	aprint_verbose_dev(epit1_sc->sc_dev,
     84  1.4.6.1     mrg 			   "timer clock frequency %d\n", freq);
     85  1.4.6.1     mrg 
     86      1.3     bsh 	epit1_sc->sc_reload_value = freq / hz - 1;
     87      1.3     bsh 
     88      1.3     bsh 	/* stop all timers */
     89      1.3     bsh 	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCR, 0);
     90      1.3     bsh 	bus_space_write_4(epit2_sc->sc_iot, epit2_sc->sc_ioh, EPIT_EPITCR, 0);
     91      1.3     bsh 
     92      1.3     bsh 	aprint_normal("clock: hz=%d stathz = %d\n", hz, stathz);
     93      1.3     bsh 
     94      1.3     bsh 	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITLR,
     95      1.3     bsh 			  epit1_sc->sc_reload_value);
     96      1.3     bsh 	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCMPR, 0);
     97      1.3     bsh 
     98  1.4.6.1     mrg 	reg = EPITCR_ENMOD | EPITCR_IOVW | EPITCR_RLD | epit1_sc->sc_clksrc;
     99  1.4.6.1     mrg 	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh,
    100  1.4.6.1     mrg 	    EPIT_EPITCR, reg);
    101  1.4.6.1     mrg 	reg |= EPITCR_EN | EPITCR_OCIEN | EPITCR_WAITEN | EPITCR_DOZEN |
    102  1.4.6.1     mrg 		EPITCR_STOPEN;
    103  1.4.6.1     mrg 	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh,
    104  1.4.6.1     mrg 	    EPIT_EPITCR, reg);
    105      1.3     bsh 
    106      1.3     bsh 	epit1_sc->sc_ih = intr_establish(epit1_sc->sc_intr, IPL_CLOCK,
    107  1.4.6.2     mrg 	    IST_LEVEL, imxclock_intr, NULL);
    108      1.2    matt }
    109      1.2    matt 
    110      1.2    matt #if 0
    111      1.2    matt void
    112      1.2    matt microtime(struct timeval *tvp)
    113      1.2    matt {
    114      1.2    matt }
    115      1.2    matt #endif
    116      1.2    matt 
    117      1.2    matt void
    118      1.2    matt setstatclockrate(int schz)
    119      1.2    matt {
    120      1.2    matt }
    121      1.3     bsh 
    122      1.3     bsh static int
    123      1.3     bsh imxclock_intr(void *arg)
    124      1.3     bsh {
    125  1.4.6.2     mrg 	struct imxclock_softc *sc = epit1_sc;
    126      1.3     bsh 
    127      1.3     bsh 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, EPIT_EPITSR, 1);
    128      1.3     bsh 	atomic_add_32(&imxclock_base, sc->sc_reload_value);
    129      1.3     bsh 
    130      1.3     bsh 	hardclock((struct clockframe *)arg);
    131      1.3     bsh 
    132      1.3     bsh 	return 1;
    133      1.3     bsh }
    134      1.3     bsh 
    135      1.3     bsh u_int
    136      1.3     bsh imx_epit_get_timecount(struct timecounter *tc)
    137      1.3     bsh {
    138      1.3     bsh 	uint32_t counter;
    139      1.3     bsh 	uint32_t base;
    140      1.3     bsh 	u_int oldirqstate;
    141      1.3     bsh 
    142      1.3     bsh 	oldirqstate = disable_interrupts(I32_bit);
    143      1.3     bsh 	counter = bus_space_read_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCNT);
    144      1.3     bsh 	base = imxclock_base;
    145      1.3     bsh 	restore_interrupts(oldirqstate);
    146      1.3     bsh 
    147      1.3     bsh 	return base - counter;
    148      1.3     bsh }
    149