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imxclock.c revision 1.4 
      1 /*	$NetBSD: imxclock.c,v 1.4 2011/07/01 20:27:50 dyoung Exp $ */
      2 /*
      3  * Copyright (c) 2009, 2010  Genetec corp.  All rights reserved.
      4  * Written by Hashimoto Kenichi for Genetec corp.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
     16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     17  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     18  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORP.
     19  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     20  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     21  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     22  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     23  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     25  * POSSIBILITY OF SUCH DAMAGE.
     26  */
     27 
     28 /*
     29  * common part for i.MX31 and i.MX51
     30  */
     31 
     32 #include <sys/param.h>
     33 #include <sys/systm.h>
     34 #include <sys/kernel.h>
     35 #include <sys/evcnt.h>
     36 #include <sys/atomic.h>
     37 #include <sys/time.h>
     38 #include <sys/timetc.h>
     39 
     40 #include <sys/types.h>
     41 #include <sys/device.h>
     42 
     43 #include <machine/intr.h>
     44 #include <sys/bus.h>
     45 
     46 #include <arm/cpu.h>
     47 #include <arm/armreg.h>
     48 #include <arm/cpufunc.h>
     49 
     50 #include <arm/imx/imxclockvar.h>
     51 #include <arm/imx/imxepitreg.h>
     52 
     53 static u_int imx_epit_get_timecount(struct timecounter *);
     54 static int imxclock_intr(void *);
     55 
     56 static struct timecounter imx_epit_timecounter = {
     57 	imx_epit_get_timecount,	/* get_timecount */
     58 	0,			/* no poll_pps */
     59 	0xffffffff,		/* counter_mask */
     60 	0,			/* frequency */
     61 	"epit",			/* name */
     62 	100,			/* quality */
     63 	NULL,			/* prev */
     64 	NULL,			/* next */
     65 };
     66 
     67 static volatile uint32_t imxclock_base;
     68 
     69 void
     70 cpu_initclocks(void)
     71 {
     72 	uint32_t reg;
     73 	int freq;
     74 
     75 	if (!epit1_sc) {
     76 		panic("%s: driver has not been initialized!", __FUNCTION__);
     77 	}
     78 
     79 	freq = imxclock_get_timerfreq(epit1_sc);
     80 	imx_epit_timecounter.tc_frequency = freq;
     81 	tc_init(&imx_epit_timecounter);
     82 
     83 	epit1_sc->sc_reload_value = freq / hz - 1;
     84 
     85 	/* stop all timers */
     86 	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCR, 0);
     87 	bus_space_write_4(epit2_sc->sc_iot, epit2_sc->sc_ioh, EPIT_EPITCR, 0);
     88 
     89 	aprint_normal("clock: hz=%d stathz = %d\n", hz, stathz);
     90 
     91 	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITLR,
     92 			  epit1_sc->sc_reload_value);
     93 	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCMPR, 0);
     94 
     95 	reg = EPITCR_ENMOD | EPITCR_IOVW | EPITCR_RLD;
     96 	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCR, reg);
     97 	reg |= EPITCR_EN | EPITCR_OCIEN | EPITCR_CLKSRC_HIGH |
     98 		EPITCR_WAITEN | EPITCR_DOZEN | EPITCR_STOPEN;
     99 	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCR, reg);
    100 
    101 	epit1_sc->sc_ih = intr_establish(epit1_sc->sc_intr, IPL_CLOCK,
    102 	    IST_LEVEL, imxclock_intr, epit1_sc);
    103 }
    104 
    105 #if 0
    106 void
    107 microtime(struct timeval *tvp)
    108 {
    109 }
    110 #endif
    111 
    112 void
    113 setstatclockrate(int schz)
    114 {
    115 }
    116 
    117 static int
    118 imxclock_intr(void *arg)
    119 {
    120 	struct imxclock_softc *sc = arg;
    121 
    122 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, EPIT_EPITSR, 1);
    123 	atomic_add_32(&imxclock_base, sc->sc_reload_value);
    124 
    125 	hardclock((struct clockframe *)arg);
    126 
    127 	return 1;
    128 }
    129 
    130 u_int
    131 imx_epit_get_timecount(struct timecounter *tc)
    132 {
    133 	uint32_t counter;
    134 	uint32_t base;
    135 	u_int oldirqstate;
    136 
    137 	oldirqstate = disable_interrupts(I32_bit);
    138 	counter = bus_space_read_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCNT);
    139 	base = imxclock_base;
    140 	restore_interrupts(oldirqstate);
    141 
    142 	return base - counter;
    143 }
    144