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imxclock.c revision 1.5 
      1 /*	$NetBSD: imxclock.c,v 1.5 2012/04/17 09:33:31 bsh Exp $ */
      2 /*
      3  * Copyright (c) 2009, 2010  Genetec corp.  All rights reserved.
      4  * Written by Hashimoto Kenichi for Genetec corp.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
     16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     17  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     18  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORP.
     19  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     20  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     21  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     22  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     23  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     25  * POSSIBILITY OF SUCH DAMAGE.
     26  */
     27 
     28 /*
     29  * common part for i.MX31 and i.MX51
     30  */
     31 
     32 #include <sys/param.h>
     33 #include <sys/systm.h>
     34 #include <sys/kernel.h>
     35 #include <sys/evcnt.h>
     36 #include <sys/atomic.h>
     37 #include <sys/time.h>
     38 #include <sys/timetc.h>
     39 
     40 #include <sys/types.h>
     41 #include <sys/device.h>
     42 
     43 #include <machine/intr.h>
     44 #include <sys/bus.h>
     45 
     46 #include <arm/cpu.h>
     47 #include <arm/armreg.h>
     48 #include <arm/cpufunc.h>
     49 
     50 #include <arm/imx/imxclockvar.h>
     51 #include <arm/imx/imxepitreg.h>
     52 
     53 static u_int imx_epit_get_timecount(struct timecounter *);
     54 static int imxclock_intr(void *);
     55 
     56 static struct timecounter imx_epit_timecounter = {
     57 	imx_epit_get_timecount,	/* get_timecount */
     58 	0,			/* no poll_pps */
     59 	0xffffffff,		/* counter_mask */
     60 	0,			/* frequency */
     61 	"epit",			/* name */
     62 	100,			/* quality */
     63 	NULL,			/* prev */
     64 	NULL,			/* next */
     65 };
     66 
     67 static volatile uint32_t imxclock_base;
     68 
     69 void
     70 cpu_initclocks(void)
     71 {
     72 	uint32_t reg;
     73 	u_int freq;
     74 
     75 	if (!epit1_sc) {
     76 		panic("%s: driver has not been initialized!", __FUNCTION__);
     77 	}
     78 
     79 	freq = imxclock_get_timerfreq(epit1_sc);
     80 	imx_epit_timecounter.tc_frequency = freq;
     81 	tc_init(&imx_epit_timecounter);
     82 
     83 	aprint_verbose_dev(epit1_sc->sc_dev,
     84 			   "timer clock frequency %d\n", freq);
     85 
     86 	epit1_sc->sc_reload_value = freq / hz - 1;
     87 
     88 	/* stop all timers */
     89 	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCR, 0);
     90 	bus_space_write_4(epit2_sc->sc_iot, epit2_sc->sc_ioh, EPIT_EPITCR, 0);
     91 
     92 	aprint_normal("clock: hz=%d stathz = %d\n", hz, stathz);
     93 
     94 	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITLR,
     95 			  epit1_sc->sc_reload_value);
     96 	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCMPR, 0);
     97 
     98 	reg = EPITCR_ENMOD | EPITCR_IOVW | EPITCR_RLD | epit1_sc->sc_clksrc;
     99 	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh,
    100 	    EPIT_EPITCR, reg);
    101 	reg |= EPITCR_EN | EPITCR_OCIEN | EPITCR_WAITEN | EPITCR_DOZEN |
    102 		EPITCR_STOPEN;
    103 	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh,
    104 	    EPIT_EPITCR, reg);
    105 
    106 	epit1_sc->sc_ih = intr_establish(epit1_sc->sc_intr, IPL_CLOCK,
    107 	    IST_LEVEL, imxclock_intr, epit1_sc);
    108 }
    109 
    110 #if 0
    111 void
    112 microtime(struct timeval *tvp)
    113 {
    114 }
    115 #endif
    116 
    117 void
    118 setstatclockrate(int schz)
    119 {
    120 }
    121 
    122 static int
    123 imxclock_intr(void *arg)
    124 {
    125 	struct imxclock_softc *sc = arg;
    126 
    127 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, EPIT_EPITSR, 1);
    128 	atomic_add_32(&imxclock_base, sc->sc_reload_value);
    129 
    130 	hardclock((struct clockframe *)arg);
    131 
    132 	return 1;
    133 }
    134 
    135 u_int
    136 imx_epit_get_timecount(struct timecounter *tc)
    137 {
    138 	uint32_t counter;
    139 	uint32_t base;
    140 	u_int oldirqstate;
    141 
    142 	oldirqstate = disable_interrupts(I32_bit);
    143 	counter = bus_space_read_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCNT);
    144 	base = imxclock_base;
    145 	restore_interrupts(oldirqstate);
    146 
    147 	return base - counter;
    148 }
    149