1 1.1 bsh /*- 2 1.1 bsh * Copyright (c) 2007 The NetBSD Foundation, Inc. 3 1.1 bsh * All rights reserved. 4 1.1 bsh * 5 1.1 bsh * This code is derived from software contributed to The NetBSD Foundation 6 1.1 bsh * by Matt Thomas. 7 1.1 bsh * 8 1.1 bsh * Redistribution and use in source and binary forms, with or without 9 1.1 bsh * modification, are permitted provided that the following conditions 10 1.1 bsh * are met: 11 1.1 bsh * 1. Redistributions of source code must retain the above copyright 12 1.1 bsh * notice, this list of conditions and the following disclaimer. 13 1.1 bsh * 2. Redistributions in binary form must reproduce the above copyright 14 1.1 bsh * notice, this list of conditions and the following disclaimer in the 15 1.1 bsh * documentation and/or other materials provided with the distribution. 16 1.1 bsh * 17 1.1 bsh * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 1.1 bsh * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 1.1 bsh * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 1.1 bsh * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 1.1 bsh * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 1.1 bsh * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 1.1 bsh * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 1.1 bsh * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 1.1 bsh * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 1.1 bsh * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 1.1 bsh * POSSIBILITY OF SUCH DAMAGE. 28 1.1 bsh */ 29 1.1 bsh #ifndef _ARM_IMX_IMXGPIOREG_H 30 1.1 bsh #define _ARM_IMX_IMXGPIOREG_H 31 1.1 bsh 32 1.1 bsh #define GPIO_SIZE 0x0020 /* Size of GPIO registers */ 33 1.1 bsh 34 1.1 bsh #define GPIO_DR 0x0000 /* GPIO Data (RW) */ 35 1.1 bsh #define GPIO_DIR 0x0004 /* GPIO Direction (RW), 1=Output */ 36 1.1 bsh #define GPIO_PSR 0x0008 /* GPIO Pad Status (R) */ 37 1.1 bsh #define GPIO_ICR1 0x000c /* GPIO Interrupt Configuration 1 (RW) */ 38 1.1 bsh #define GPIO_ICR2 0x0010 /* GPIO Interrupt Configuration 2 (RW) */ 39 1.1 bsh #define GPIO_IMR 0x0014 /* GPIO Interrupt Mask (RW) */ 40 1.1 bsh #define GPIO_ISR 0x0018 /* GPIO Interrupt Status (RW, W1C) */ 41 1.1 bsh #define GPIO_EDGE_SEL 0x001c /* GPIO Edge Select Register (i.MX51 only) */ 42 1.1 bsh 43 1.1 bsh #define GPIO_ICR_LEVEL_LOW 0 44 1.1 bsh #define GPIO_ICR_LEVEL_HIGH 1 45 1.1 bsh #define GPIO_ICR_EDGE_RISING 2 46 1.1 bsh #define GPIO_ICR_EDGE_FALLING 3 47 1.1 bsh 48 1.2 bsh #define GPIO_NPINS 32 49 1.1 bsh 50 1.1 bsh #endif /* _ARM_IMX_IMXGPIOREG_H */ 51