imxi2c.c revision 1.1.6.2 1 1.1.6.2 tls /* $NetBSD: imxi2c.c,v 1.1.6.2 2014/08/20 00:02:46 tls Exp $ */
2 1.1.6.2 tls
3 1.1.6.2 tls /*
4 1.1.6.2 tls * Copyright (c) 2012 Genetec Corporation. All rights reserved.
5 1.1.6.2 tls * Written by Hashimoto Kenichi for Genetec Corporation.
6 1.1.6.2 tls *
7 1.1.6.2 tls * Redistribution and use in source and binary forms, with or without
8 1.1.6.2 tls * modification, are permitted provided that the following conditions
9 1.1.6.2 tls * are met:
10 1.1.6.2 tls * 1. Redistributions of source code must retain the above copyright
11 1.1.6.2 tls * notice, this list of conditions and the following disclaimer.
12 1.1.6.2 tls * 2. Redistributions in binary form must reproduce the above copyright
13 1.1.6.2 tls * notice, this list of conditions and the following disclaimer in the
14 1.1.6.2 tls * documentation and/or other materials provided with the distribution.
15 1.1.6.2 tls *
16 1.1.6.2 tls * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
17 1.1.6.2 tls * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 1.1.6.2 tls * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 1.1.6.2 tls * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20 1.1.6.2 tls * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 1.1.6.2 tls * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 1.1.6.2 tls * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 1.1.6.2 tls * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 1.1.6.2 tls * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 1.1.6.2 tls * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 1.1.6.2 tls * SUCH DAMAGE.
27 1.1.6.2 tls */
28 1.1.6.2 tls
29 1.1.6.2 tls #include <sys/cdefs.h>
30 1.1.6.2 tls __KERNEL_RCSID(0, "$NetBSD: imxi2c.c,v 1.1.6.2 2014/08/20 00:02:46 tls Exp $");
31 1.1.6.2 tls
32 1.1.6.2 tls #include "opt_imx.h"
33 1.1.6.2 tls
34 1.1.6.2 tls #include <sys/param.h>
35 1.1.6.2 tls #include <sys/bus.h>
36 1.1.6.2 tls #include <sys/device.h>
37 1.1.6.2 tls #include <sys/kernel.h>
38 1.1.6.2 tls #include <sys/systm.h>
39 1.1.6.2 tls #include <sys/mutex.h>
40 1.1.6.2 tls
41 1.1.6.2 tls #include <dev/i2c/i2cvar.h>
42 1.1.6.2 tls #include <arm/imx/imxi2creg.h>
43 1.1.6.2 tls #include <arm/imx/imxi2cvar.h>
44 1.1.6.2 tls
45 1.1.6.2 tls #include <arm/imx/imx51_ccmvar.h>
46 1.1.6.2 tls
47 1.1.6.2 tls #define I2C_READ(sc, reg) \
48 1.1.6.2 tls bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, reg)
49 1.1.6.2 tls #define I2C_WRITE(sc, reg, val) \
50 1.1.6.2 tls bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, reg, val)
51 1.1.6.2 tls
52 1.1.6.2 tls #define I2C_TIMEOUT 1000 /* protocol timeout, in uSecs */
53 1.1.6.2 tls
54 1.1.6.2 tls static int imxi2c_i2c_acquire_bus(void *, int);
55 1.1.6.2 tls static void imxi2c_i2c_release_bus(void *, int);
56 1.1.6.2 tls static int imxi2c_i2c_exec(void *, u_int, u_int16_t, const void *, size_t, void *,
57 1.1.6.2 tls size_t, int);
58 1.1.6.2 tls
59 1.1.6.2 tls static int imxi2c_wait(struct imxi2c_softc *, int);
60 1.1.6.2 tls static int imxi2c_wait_bus(struct imxi2c_softc *, int);
61 1.1.6.2 tls
62 1.1.6.2 tls struct clk_div {
63 1.1.6.2 tls uint8_t ic_val;
64 1.1.6.2 tls int div;
65 1.1.6.2 tls };
66 1.1.6.2 tls
67 1.1.6.2 tls static const struct clk_div i2c_clk_div[] = {
68 1.1.6.2 tls {0x20, 22}, {0x21, 24}, {0x22, 26}, {0x23, 28},
69 1.1.6.2 tls {0x00, 30}, {0x01, 32}, {0x24, 32}, {0x02, 36},
70 1.1.6.2 tls {0x25, 36}, {0x26, 40}, {0x03, 42}, {0x27, 44},
71 1.1.6.2 tls {0x04, 48}, {0x28, 48}, {0x05, 52}, {0x29, 56},
72 1.1.6.2 tls {0x06, 60}, {0x2A, 64}, {0x07, 72}, {0x2B, 72},
73 1.1.6.2 tls {0x08, 80}, {0x2C, 80}, {0x09, 88}, {0x2D, 96},
74 1.1.6.2 tls {0x0A, 104}, {0x2E, 112}, {0x0B, 128}, {0x2F, 128},
75 1.1.6.2 tls {0x0C, 144}, {0x0D, 160}, {0x30, 160}, {0x0E, 192},
76 1.1.6.2 tls {0x31, 192}, {0x32, 224}, {0x0F, 240}, {0x33, 256},
77 1.1.6.2 tls {0x10, 288}, {0x11, 320}, {0x34, 320}, {0x12, 384},
78 1.1.6.2 tls {0x35, 384}, {0x36, 448}, {0x13, 480}, {0x37, 512},
79 1.1.6.2 tls {0x14, 576}, {0x15, 640}, {0x38, 640}, {0x16, 768},
80 1.1.6.2 tls {0x39, 768}, {0x3A, 896}, {0x17, 960}, {0x3B, 1024},
81 1.1.6.2 tls {0x18, 1152}, {0x19, 1280}, {0x3C, 1280}, {0x1A, 1536},
82 1.1.6.2 tls {0x3D, 1536}, {0x3E, 1792}, {0x1B, 1920}, {0x3F, 2048},
83 1.1.6.2 tls {0x1C, 2304}, {0x1D, 2560}, {0x1E, 3072}, {0x1F, 3840},
84 1.1.6.2 tls };
85 1.1.6.2 tls
86 1.1.6.2 tls CFATTACH_DECL_NEW(imxi2c, sizeof(struct imxi2c_softc),
87 1.1.6.2 tls imxi2c_match, imxi2c_attach, NULL, NULL);
88 1.1.6.2 tls
89 1.1.6.2 tls int
90 1.1.6.2 tls imxi2c_attach_common(device_t parent, device_t self,
91 1.1.6.2 tls bus_space_tag_t iot, paddr_t iobase, size_t size, int intr, int flags)
92 1.1.6.2 tls {
93 1.1.6.2 tls struct imxi2c_softc *sc = device_private(self);
94 1.1.6.2 tls struct i2cbus_attach_args iba;
95 1.1.6.2 tls int error;
96 1.1.6.2 tls
97 1.1.6.2 tls aprint_normal(": i.MX IIC bus controller\n");
98 1.1.6.2 tls
99 1.1.6.2 tls sc->sc_dev = self;
100 1.1.6.2 tls sc->sc_iot = iot;
101 1.1.6.2 tls if (size <= 0)
102 1.1.6.2 tls size = I2C_SIZE;
103 1.1.6.2 tls error = bus_space_map(sc->sc_iot, iobase, size, 0, &sc->sc_ioh);
104 1.1.6.2 tls if (error) {
105 1.1.6.2 tls aprint_error_dev(sc->sc_dev,
106 1.1.6.2 tls "failed to map registers (errno=%d)\n", error);
107 1.1.6.2 tls return 1;
108 1.1.6.2 tls }
109 1.1.6.2 tls
110 1.1.6.2 tls mutex_init(&sc->sc_buslock, MUTEX_DEFAULT, IPL_NONE);
111 1.1.6.2 tls
112 1.1.6.2 tls sc->sc_i2c.ic_cookie = sc;
113 1.1.6.2 tls sc->sc_i2c.ic_acquire_bus = imxi2c_i2c_acquire_bus;
114 1.1.6.2 tls sc->sc_i2c.ic_release_bus = imxi2c_i2c_release_bus;
115 1.1.6.2 tls sc->sc_i2c.ic_send_start = NULL;
116 1.1.6.2 tls sc->sc_i2c.ic_send_stop = NULL;
117 1.1.6.2 tls sc->sc_i2c.ic_initiate_xfer = NULL;
118 1.1.6.2 tls sc->sc_i2c.ic_read_byte = NULL;
119 1.1.6.2 tls sc->sc_i2c.ic_write_byte = NULL;
120 1.1.6.2 tls sc->sc_i2c.ic_exec = imxi2c_i2c_exec;
121 1.1.6.2 tls
122 1.1.6.2 tls memset(&iba, 0, sizeof(iba));
123 1.1.6.2 tls iba.iba_tag = &sc->sc_i2c;
124 1.1.6.2 tls
125 1.1.6.2 tls return 0;
126 1.1.6.2 tls }
127 1.1.6.2 tls
128 1.1.6.2 tls int
129 1.1.6.2 tls imxi2c_set_freq(device_t self, long freq, int speed)
130 1.1.6.2 tls {
131 1.1.6.2 tls struct imxi2c_softc *sc = device_private(self);
132 1.1.6.2 tls bool found = false;
133 1.1.6.2 tls int index;
134 1.1.6.2 tls
135 1.1.6.2 tls for (index = 0; index < __arraycount(i2c_clk_div); index++) {
136 1.1.6.2 tls if (freq / i2c_clk_div[index].div < speed) {
137 1.1.6.2 tls found = true;
138 1.1.6.2 tls break;
139 1.1.6.2 tls }
140 1.1.6.2 tls }
141 1.1.6.2 tls
142 1.1.6.2 tls if (found == false)
143 1.1.6.2 tls I2C_WRITE(sc, I2C_IFDR, 0x1f);
144 1.1.6.2 tls else
145 1.1.6.2 tls I2C_WRITE(sc, I2C_IFDR, i2c_clk_div[index].ic_val);
146 1.1.6.2 tls
147 1.1.6.2 tls return 0;
148 1.1.6.2 tls }
149 1.1.6.2 tls
150 1.1.6.2 tls
151 1.1.6.2 tls static int
152 1.1.6.2 tls imxi2c_wait(struct imxi2c_softc *sc, int flags)
153 1.1.6.2 tls {
154 1.1.6.2 tls for (int i = I2C_TIMEOUT; i >= 0; --i) {
155 1.1.6.2 tls uint16_t sr = I2C_READ(sc, I2C_I2SR);
156 1.1.6.2 tls if (sr & I2SR_IIF) {
157 1.1.6.2 tls I2C_WRITE(sc, I2C_I2SR, 0);
158 1.1.6.2 tls if (sr & I2SR_IAL)
159 1.1.6.2 tls return EIO;
160 1.1.6.2 tls if ((sr & I2SR_ICF) == 0)
161 1.1.6.2 tls return EIO;
162 1.1.6.2 tls if ((flags & I2C_F_READ) == 0 && (sr & I2SR_RXAK))
163 1.1.6.2 tls return EIO;
164 1.1.6.2 tls return 0;
165 1.1.6.2 tls }
166 1.1.6.2 tls delay(1);
167 1.1.6.2 tls }
168 1.1.6.2 tls
169 1.1.6.2 tls return ETIMEDOUT;
170 1.1.6.2 tls }
171 1.1.6.2 tls
172 1.1.6.2 tls static int
173 1.1.6.2 tls imxi2c_wait_bus(struct imxi2c_softc *sc, int status)
174 1.1.6.2 tls {
175 1.1.6.2 tls for (int i = I2C_TIMEOUT; i >= 0; --i) {
176 1.1.6.2 tls uint16_t sr = I2C_READ(sc, I2C_I2SR);
177 1.1.6.2 tls if ((sr & I2SR_IBB) == status)
178 1.1.6.2 tls return 0;
179 1.1.6.2 tls delay(1);
180 1.1.6.2 tls }
181 1.1.6.2 tls
182 1.1.6.2 tls return ETIMEDOUT;
183 1.1.6.2 tls }
184 1.1.6.2 tls
185 1.1.6.2 tls static int
186 1.1.6.2 tls imxi2c_i2c_acquire_bus(void *cookie, int flags)
187 1.1.6.2 tls {
188 1.1.6.2 tls struct imxi2c_softc *sc = cookie;
189 1.1.6.2 tls
190 1.1.6.2 tls mutex_enter(&sc->sc_buslock);
191 1.1.6.2 tls return 0;
192 1.1.6.2 tls }
193 1.1.6.2 tls
194 1.1.6.2 tls static void
195 1.1.6.2 tls imxi2c_i2c_release_bus(void *cookie, int flags)
196 1.1.6.2 tls {
197 1.1.6.2 tls struct imxi2c_softc *sc = cookie;
198 1.1.6.2 tls
199 1.1.6.2 tls mutex_exit(&sc->sc_buslock);
200 1.1.6.2 tls return;
201 1.1.6.2 tls }
202 1.1.6.2 tls
203 1.1.6.2 tls static int
204 1.1.6.2 tls imxi2c_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *vcmd,
205 1.1.6.2 tls size_t cmdlen, void *vbuf, size_t buflen, int flags)
206 1.1.6.2 tls {
207 1.1.6.2 tls struct imxi2c_softc *sc = cookie;
208 1.1.6.2 tls const uint8_t *cmdbuf = vcmd;
209 1.1.6.2 tls uint8_t *buf = vbuf;
210 1.1.6.2 tls int err = 0;
211 1.1.6.2 tls size_t len;
212 1.1.6.2 tls uint16_t val;
213 1.1.6.2 tls
214 1.1.6.2 tls /* Clear the bus. */
215 1.1.6.2 tls I2C_WRITE(sc, I2C_I2SR, 0);
216 1.1.6.2 tls I2C_WRITE(sc, I2C_I2CR, I2CR_IEN);
217 1.1.6.2 tls err = imxi2c_wait_bus(sc, 0);
218 1.1.6.2 tls if (err)
219 1.1.6.2 tls return err;
220 1.1.6.2 tls
221 1.1.6.2 tls if (cmdlen > 0) {
222 1.1.6.2 tls I2C_WRITE(sc, I2C_I2CR, I2CR_IEN | I2CR_MSTA | I2CR_MTX);
223 1.1.6.2 tls err = imxi2c_wait_bus(sc, I2SR_IBB);
224 1.1.6.2 tls if (err)
225 1.1.6.2 tls goto out;
226 1.1.6.2 tls I2C_WRITE(sc, I2C_I2DR, addr<<1);
227 1.1.6.2 tls err = imxi2c_wait(sc, I2C_F_WRITE);
228 1.1.6.2 tls if (err)
229 1.1.6.2 tls goto out;
230 1.1.6.2 tls len = cmdlen;
231 1.1.6.2 tls while (len--) {
232 1.1.6.2 tls I2C_WRITE(sc, I2C_I2DR, *cmdbuf++);
233 1.1.6.2 tls err = imxi2c_wait(sc, I2C_F_WRITE);
234 1.1.6.2 tls if (err)
235 1.1.6.2 tls goto out;
236 1.1.6.2 tls }
237 1.1.6.2 tls }
238 1.1.6.2 tls
239 1.1.6.2 tls if (I2C_OP_READ_P(op) && buflen > 0) {
240 1.1.6.2 tls /* RESTART if we did write a command above. */
241 1.1.6.2 tls val = I2CR_IEN | I2CR_MSTA | I2CR_MTX;
242 1.1.6.2 tls if (cmdlen > 0)
243 1.1.6.2 tls val |= I2CR_RSTA;
244 1.1.6.2 tls I2C_WRITE(sc, I2C_I2CR, val);
245 1.1.6.2 tls err = imxi2c_wait_bus(sc, I2SR_IBB);
246 1.1.6.2 tls if (err)
247 1.1.6.2 tls goto out;
248 1.1.6.2 tls I2C_WRITE(sc, I2C_I2DR, addr<<1 | 0x1);
249 1.1.6.2 tls err = imxi2c_wait(sc, I2C_F_WRITE);
250 1.1.6.2 tls if (err)
251 1.1.6.2 tls goto out;
252 1.1.6.2 tls
253 1.1.6.2 tls /* NACK if we're only sending one byte. */
254 1.1.6.2 tls val = I2CR_IEN | I2CR_MSTA;
255 1.1.6.2 tls if (buflen == 1)
256 1.1.6.2 tls val |= I2CR_TXAK;
257 1.1.6.2 tls I2C_WRITE(sc, I2C_I2CR, val);
258 1.1.6.2 tls
259 1.1.6.2 tls /* Dummy read. */
260 1.1.6.2 tls I2C_READ(sc, I2C_I2DR);
261 1.1.6.2 tls
262 1.1.6.2 tls len = buflen;
263 1.1.6.2 tls while (len--) {
264 1.1.6.2 tls err = imxi2c_wait(sc, I2C_F_READ);
265 1.1.6.2 tls if (err)
266 1.1.6.2 tls goto out;
267 1.1.6.2 tls
268 1.1.6.2 tls if (len == 1) {
269 1.1.6.2 tls /* NACK on last byte. */
270 1.1.6.2 tls val = I2CR_IEN | I2CR_MSTA | I2CR_TXAK;
271 1.1.6.2 tls I2C_WRITE(sc, I2C_I2CR, val);
272 1.1.6.2 tls } else if (len == 0) {
273 1.1.6.2 tls /* STOP after last byte. */
274 1.1.6.2 tls val = I2CR_IEN | I2CR_TXAK;
275 1.1.6.2 tls I2C_WRITE(sc, I2C_I2CR, val);
276 1.1.6.2 tls }
277 1.1.6.2 tls *buf++ = I2C_READ(sc, I2C_I2DR);
278 1.1.6.2 tls }
279 1.1.6.2 tls }
280 1.1.6.2 tls
281 1.1.6.2 tls if (I2C_OP_WRITE_P(op) && cmdlen == 0 && buflen > 0) {
282 1.1.6.2 tls /* START if we didn't write a command. */
283 1.1.6.2 tls I2C_WRITE(sc, I2C_I2CR, I2CR_IEN | I2CR_MSTA | I2CR_MTX);
284 1.1.6.2 tls err = imxi2c_wait_bus(sc, I2SR_IBB);
285 1.1.6.2 tls if (err)
286 1.1.6.2 tls goto out;
287 1.1.6.2 tls I2C_WRITE(sc, I2C_I2DR, addr<<1);
288 1.1.6.2 tls err = imxi2c_wait(sc, I2C_F_WRITE);
289 1.1.6.2 tls if (err)
290 1.1.6.2 tls goto out;
291 1.1.6.2 tls }
292 1.1.6.2 tls
293 1.1.6.2 tls if (I2C_OP_WRITE_P(op) && buflen > 0) {
294 1.1.6.2 tls len = buflen;
295 1.1.6.2 tls while (len--) {
296 1.1.6.2 tls I2C_WRITE(sc, I2C_I2DR, *buf++);
297 1.1.6.2 tls err = imxi2c_wait(sc, I2C_F_WRITE);
298 1.1.6.2 tls if (err)
299 1.1.6.2 tls goto out;
300 1.1.6.2 tls }
301 1.1.6.2 tls }
302 1.1.6.2 tls
303 1.1.6.2 tls out:
304 1.1.6.2 tls if (err)
305 1.1.6.2 tls printf("%s: i2c bus error\n", __func__);
306 1.1.6.2 tls
307 1.1.6.2 tls /* STOP if we're still holding the bus. */
308 1.1.6.2 tls I2C_WRITE(sc, I2C_I2CR, I2CR_IEN);
309 1.1.6.2 tls imxi2c_wait_bus(sc, 0);
310 1.1.6.2 tls
311 1.1.6.2 tls return err;
312 1.1.6.2 tls }
313