imxi2c.c revision 1.1.6.2
1 /* $NetBSD: imxi2c.c,v 1.1.6.2 2014/08/20 00:02:46 tls Exp $ */ 2 3 /* 4 * Copyright (c) 2012 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: imxi2c.c,v 1.1.6.2 2014/08/20 00:02:46 tls Exp $"); 31 32 #include "opt_imx.h" 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/kernel.h> 38 #include <sys/systm.h> 39 #include <sys/mutex.h> 40 41 #include <dev/i2c/i2cvar.h> 42 #include <arm/imx/imxi2creg.h> 43 #include <arm/imx/imxi2cvar.h> 44 45 #include <arm/imx/imx51_ccmvar.h> 46 47 #define I2C_READ(sc, reg) \ 48 bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, reg) 49 #define I2C_WRITE(sc, reg, val) \ 50 bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, reg, val) 51 52 #define I2C_TIMEOUT 1000 /* protocol timeout, in uSecs */ 53 54 static int imxi2c_i2c_acquire_bus(void *, int); 55 static void imxi2c_i2c_release_bus(void *, int); 56 static int imxi2c_i2c_exec(void *, u_int, u_int16_t, const void *, size_t, void *, 57 size_t, int); 58 59 static int imxi2c_wait(struct imxi2c_softc *, int); 60 static int imxi2c_wait_bus(struct imxi2c_softc *, int); 61 62 struct clk_div { 63 uint8_t ic_val; 64 int div; 65 }; 66 67 static const struct clk_div i2c_clk_div[] = { 68 {0x20, 22}, {0x21, 24}, {0x22, 26}, {0x23, 28}, 69 {0x00, 30}, {0x01, 32}, {0x24, 32}, {0x02, 36}, 70 {0x25, 36}, {0x26, 40}, {0x03, 42}, {0x27, 44}, 71 {0x04, 48}, {0x28, 48}, {0x05, 52}, {0x29, 56}, 72 {0x06, 60}, {0x2A, 64}, {0x07, 72}, {0x2B, 72}, 73 {0x08, 80}, {0x2C, 80}, {0x09, 88}, {0x2D, 96}, 74 {0x0A, 104}, {0x2E, 112}, {0x0B, 128}, {0x2F, 128}, 75 {0x0C, 144}, {0x0D, 160}, {0x30, 160}, {0x0E, 192}, 76 {0x31, 192}, {0x32, 224}, {0x0F, 240}, {0x33, 256}, 77 {0x10, 288}, {0x11, 320}, {0x34, 320}, {0x12, 384}, 78 {0x35, 384}, {0x36, 448}, {0x13, 480}, {0x37, 512}, 79 {0x14, 576}, {0x15, 640}, {0x38, 640}, {0x16, 768}, 80 {0x39, 768}, {0x3A, 896}, {0x17, 960}, {0x3B, 1024}, 81 {0x18, 1152}, {0x19, 1280}, {0x3C, 1280}, {0x1A, 1536}, 82 {0x3D, 1536}, {0x3E, 1792}, {0x1B, 1920}, {0x3F, 2048}, 83 {0x1C, 2304}, {0x1D, 2560}, {0x1E, 3072}, {0x1F, 3840}, 84 }; 85 86 CFATTACH_DECL_NEW(imxi2c, sizeof(struct imxi2c_softc), 87 imxi2c_match, imxi2c_attach, NULL, NULL); 88 89 int 90 imxi2c_attach_common(device_t parent, device_t self, 91 bus_space_tag_t iot, paddr_t iobase, size_t size, int intr, int flags) 92 { 93 struct imxi2c_softc *sc = device_private(self); 94 struct i2cbus_attach_args iba; 95 int error; 96 97 aprint_normal(": i.MX IIC bus controller\n"); 98 99 sc->sc_dev = self; 100 sc->sc_iot = iot; 101 if (size <= 0) 102 size = I2C_SIZE; 103 error = bus_space_map(sc->sc_iot, iobase, size, 0, &sc->sc_ioh); 104 if (error) { 105 aprint_error_dev(sc->sc_dev, 106 "failed to map registers (errno=%d)\n", error); 107 return 1; 108 } 109 110 mutex_init(&sc->sc_buslock, MUTEX_DEFAULT, IPL_NONE); 111 112 sc->sc_i2c.ic_cookie = sc; 113 sc->sc_i2c.ic_acquire_bus = imxi2c_i2c_acquire_bus; 114 sc->sc_i2c.ic_release_bus = imxi2c_i2c_release_bus; 115 sc->sc_i2c.ic_send_start = NULL; 116 sc->sc_i2c.ic_send_stop = NULL; 117 sc->sc_i2c.ic_initiate_xfer = NULL; 118 sc->sc_i2c.ic_read_byte = NULL; 119 sc->sc_i2c.ic_write_byte = NULL; 120 sc->sc_i2c.ic_exec = imxi2c_i2c_exec; 121 122 memset(&iba, 0, sizeof(iba)); 123 iba.iba_tag = &sc->sc_i2c; 124 125 return 0; 126 } 127 128 int 129 imxi2c_set_freq(device_t self, long freq, int speed) 130 { 131 struct imxi2c_softc *sc = device_private(self); 132 bool found = false; 133 int index; 134 135 for (index = 0; index < __arraycount(i2c_clk_div); index++) { 136 if (freq / i2c_clk_div[index].div < speed) { 137 found = true; 138 break; 139 } 140 } 141 142 if (found == false) 143 I2C_WRITE(sc, I2C_IFDR, 0x1f); 144 else 145 I2C_WRITE(sc, I2C_IFDR, i2c_clk_div[index].ic_val); 146 147 return 0; 148 } 149 150 151 static int 152 imxi2c_wait(struct imxi2c_softc *sc, int flags) 153 { 154 for (int i = I2C_TIMEOUT; i >= 0; --i) { 155 uint16_t sr = I2C_READ(sc, I2C_I2SR); 156 if (sr & I2SR_IIF) { 157 I2C_WRITE(sc, I2C_I2SR, 0); 158 if (sr & I2SR_IAL) 159 return EIO; 160 if ((sr & I2SR_ICF) == 0) 161 return EIO; 162 if ((flags & I2C_F_READ) == 0 && (sr & I2SR_RXAK)) 163 return EIO; 164 return 0; 165 } 166 delay(1); 167 } 168 169 return ETIMEDOUT; 170 } 171 172 static int 173 imxi2c_wait_bus(struct imxi2c_softc *sc, int status) 174 { 175 for (int i = I2C_TIMEOUT; i >= 0; --i) { 176 uint16_t sr = I2C_READ(sc, I2C_I2SR); 177 if ((sr & I2SR_IBB) == status) 178 return 0; 179 delay(1); 180 } 181 182 return ETIMEDOUT; 183 } 184 185 static int 186 imxi2c_i2c_acquire_bus(void *cookie, int flags) 187 { 188 struct imxi2c_softc *sc = cookie; 189 190 mutex_enter(&sc->sc_buslock); 191 return 0; 192 } 193 194 static void 195 imxi2c_i2c_release_bus(void *cookie, int flags) 196 { 197 struct imxi2c_softc *sc = cookie; 198 199 mutex_exit(&sc->sc_buslock); 200 return; 201 } 202 203 static int 204 imxi2c_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *vcmd, 205 size_t cmdlen, void *vbuf, size_t buflen, int flags) 206 { 207 struct imxi2c_softc *sc = cookie; 208 const uint8_t *cmdbuf = vcmd; 209 uint8_t *buf = vbuf; 210 int err = 0; 211 size_t len; 212 uint16_t val; 213 214 /* Clear the bus. */ 215 I2C_WRITE(sc, I2C_I2SR, 0); 216 I2C_WRITE(sc, I2C_I2CR, I2CR_IEN); 217 err = imxi2c_wait_bus(sc, 0); 218 if (err) 219 return err; 220 221 if (cmdlen > 0) { 222 I2C_WRITE(sc, I2C_I2CR, I2CR_IEN | I2CR_MSTA | I2CR_MTX); 223 err = imxi2c_wait_bus(sc, I2SR_IBB); 224 if (err) 225 goto out; 226 I2C_WRITE(sc, I2C_I2DR, addr<<1); 227 err = imxi2c_wait(sc, I2C_F_WRITE); 228 if (err) 229 goto out; 230 len = cmdlen; 231 while (len--) { 232 I2C_WRITE(sc, I2C_I2DR, *cmdbuf++); 233 err = imxi2c_wait(sc, I2C_F_WRITE); 234 if (err) 235 goto out; 236 } 237 } 238 239 if (I2C_OP_READ_P(op) && buflen > 0) { 240 /* RESTART if we did write a command above. */ 241 val = I2CR_IEN | I2CR_MSTA | I2CR_MTX; 242 if (cmdlen > 0) 243 val |= I2CR_RSTA; 244 I2C_WRITE(sc, I2C_I2CR, val); 245 err = imxi2c_wait_bus(sc, I2SR_IBB); 246 if (err) 247 goto out; 248 I2C_WRITE(sc, I2C_I2DR, addr<<1 | 0x1); 249 err = imxi2c_wait(sc, I2C_F_WRITE); 250 if (err) 251 goto out; 252 253 /* NACK if we're only sending one byte. */ 254 val = I2CR_IEN | I2CR_MSTA; 255 if (buflen == 1) 256 val |= I2CR_TXAK; 257 I2C_WRITE(sc, I2C_I2CR, val); 258 259 /* Dummy read. */ 260 I2C_READ(sc, I2C_I2DR); 261 262 len = buflen; 263 while (len--) { 264 err = imxi2c_wait(sc, I2C_F_READ); 265 if (err) 266 goto out; 267 268 if (len == 1) { 269 /* NACK on last byte. */ 270 val = I2CR_IEN | I2CR_MSTA | I2CR_TXAK; 271 I2C_WRITE(sc, I2C_I2CR, val); 272 } else if (len == 0) { 273 /* STOP after last byte. */ 274 val = I2CR_IEN | I2CR_TXAK; 275 I2C_WRITE(sc, I2C_I2CR, val); 276 } 277 *buf++ = I2C_READ(sc, I2C_I2DR); 278 } 279 } 280 281 if (I2C_OP_WRITE_P(op) && cmdlen == 0 && buflen > 0) { 282 /* START if we didn't write a command. */ 283 I2C_WRITE(sc, I2C_I2CR, I2CR_IEN | I2CR_MSTA | I2CR_MTX); 284 err = imxi2c_wait_bus(sc, I2SR_IBB); 285 if (err) 286 goto out; 287 I2C_WRITE(sc, I2C_I2DR, addr<<1); 288 err = imxi2c_wait(sc, I2C_F_WRITE); 289 if (err) 290 goto out; 291 } 292 293 if (I2C_OP_WRITE_P(op) && buflen > 0) { 294 len = buflen; 295 while (len--) { 296 I2C_WRITE(sc, I2C_I2DR, *buf++); 297 err = imxi2c_wait(sc, I2C_F_WRITE); 298 if (err) 299 goto out; 300 } 301 } 302 303 out: 304 if (err) 305 printf("%s: i2c bus error\n", __func__); 306 307 /* STOP if we're still holding the bus. */ 308 I2C_WRITE(sc, I2C_I2CR, I2CR_IEN); 309 imxi2c_wait_bus(sc, 0); 310 311 return err; 312 } 313
Indexes created Fri Oct 03 02:09:57 GMT 2025