imxspi.c revision 1.2.10.2
1 1.2.10.2 tls /* $NetBSD: imxspi.c,v 1.2.10.2 2014/08/20 00:02:46 tls Exp $ */ 2 1.2.10.2 tls 3 1.2.10.2 tls /*- 4 1.2.10.2 tls * Copyright (c) 2014 Genetec Corporation. All rights reserved. 5 1.2.10.2 tls * Written by Hashimoto Kenichi for Genetec Corporation. 6 1.2.10.2 tls * 7 1.2.10.2 tls * Redistribution and use in source and binary forms, with or without 8 1.2.10.2 tls * modification, are permitted provided that the following conditions 9 1.2.10.2 tls * are met: 10 1.2.10.2 tls * 1. Redistributions of source code must retain the above copyright 11 1.2.10.2 tls * notice, this list of conditions and the following disclaimer. 12 1.2.10.2 tls * 2. Redistributions in binary form must reproduce the above copyright 13 1.2.10.2 tls * notice, this list of conditions and the following disclaimer in the 14 1.2.10.2 tls * documentation and/or other materials provided with the distribution. 15 1.2.10.2 tls * 16 1.2.10.2 tls * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 17 1.2.10.2 tls * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 1.2.10.2 tls * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 1.2.10.2 tls * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 20 1.2.10.2 tls * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 1.2.10.2 tls * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 1.2.10.2 tls * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 1.2.10.2 tls * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 1.2.10.2 tls * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 1.2.10.2 tls * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 1.2.10.2 tls * POSSIBILITY OF SUCH DAMAGE. 27 1.2.10.2 tls */ 28 1.2.10.2 tls 29 1.2.10.2 tls /* 30 1.2.10.2 tls * this module support CSPI and eCSPI. 31 1.2.10.2 tls * i.MX51 have 2 eCSPI and 1 CSPI modules. 32 1.2.10.2 tls */ 33 1.2.10.2 tls 34 1.2.10.2 tls #include <sys/cdefs.h> 35 1.2.10.2 tls __KERNEL_RCSID(0, "$NetBSD: imxspi.c,v 1.2.10.2 2014/08/20 00:02:46 tls Exp $"); 36 1.2.10.2 tls 37 1.2.10.2 tls #include "opt_imx.h" 38 1.2.10.2 tls #include "opt_imxspi.h" 39 1.2.10.2 tls 40 1.2.10.2 tls #include <sys/param.h> 41 1.2.10.2 tls #include <sys/systm.h> 42 1.2.10.2 tls #include <sys/kernel.h> 43 1.2.10.2 tls #include <sys/device.h> 44 1.2.10.2 tls #include <sys/errno.h> 45 1.2.10.2 tls #include <sys/proc.h> 46 1.2.10.2 tls #include <sys/intr.h> 47 1.2.10.2 tls 48 1.2.10.2 tls #include <sys/bus.h> 49 1.2.10.2 tls #include <machine/cpu.h> 50 1.2.10.2 tls #include <machine/intr.h> 51 1.2.10.2 tls 52 1.2.10.2 tls #include <arm/imx/imxspivar.h> 53 1.2.10.2 tls #include <arm/imx/imxspireg.h> 54 1.2.10.2 tls 55 1.2.10.2 tls /* SPI service routines */ 56 1.2.10.2 tls static int imxspi_configure_enhanced(void *, int, int, int); 57 1.2.10.2 tls static int imxspi_configure(void *, int, int, int); 58 1.2.10.2 tls static int imxspi_transfer(void *, struct spi_transfer *); 59 1.2.10.2 tls static int imxspi_intr(void *); 60 1.2.10.2 tls 61 1.2.10.2 tls /* internal stuff */ 62 1.2.10.2 tls void imxspi_done(struct imxspi_softc *, int); 63 1.2.10.2 tls void imxspi_send(struct imxspi_softc *); 64 1.2.10.2 tls void imxspi_recv(struct imxspi_softc *); 65 1.2.10.2 tls void imxspi_sched(struct imxspi_softc *); 66 1.2.10.2 tls 67 1.2.10.2 tls #define IMXSPI(x) \ 68 1.2.10.2 tls ((sc->sc_enhanced) ? __CONCAT(ECSPI_, x) : __CONCAT(CSPI_, x)) 69 1.2.10.2 tls #define READ_REG(sc, x) \ 70 1.2.10.2 tls bus_space_read_4(sc->sc_iot, sc->sc_ioh, IMXSPI(x)) 71 1.2.10.2 tls #define WRITE_REG(sc, x, v) \ 72 1.2.10.2 tls bus_space_write_4(sc->sc_iot, sc->sc_ioh, IMXSPI(x), (v)) 73 1.2.10.2 tls 74 1.2.10.2 tls #ifdef IMXSPI_DEBUG 75 1.2.10.2 tls int imxspi_debug = IMXSPI_DEBUG; 76 1.2.10.2 tls #define DPRINTFN(n,x) if (imxspi_debug>(n)) printf x; 77 1.2.10.2 tls #else 78 1.2.10.2 tls #define DPRINTFN(n,x) 79 1.2.10.2 tls #endif 80 1.2.10.2 tls 81 1.2.10.2 tls int 82 1.2.10.2 tls imxspi_attach_common(device_t parent, struct imxspi_softc *sc, void *aux) 83 1.2.10.2 tls { 84 1.2.10.2 tls struct imxspi_attach_args *saa = aux; 85 1.2.10.2 tls struct spibus_attach_args sba; 86 1.2.10.2 tls bus_addr_t addr = saa->saa_addr; 87 1.2.10.2 tls bus_size_t size = saa->saa_size; 88 1.2.10.2 tls 89 1.2.10.2 tls sc->sc_iot = saa->saa_iot; 90 1.2.10.2 tls sc->sc_freq = saa->saa_freq; 91 1.2.10.2 tls sc->sc_tag = saa->saa_tag; 92 1.2.10.2 tls sc->sc_enhanced = saa->saa_enhanced; 93 1.2.10.2 tls if (size <= 0) 94 1.2.10.2 tls size = SPI_SIZE; 95 1.2.10.2 tls 96 1.2.10.2 tls if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh)) { 97 1.2.10.2 tls aprint_error_dev(sc->sc_dev, "couldn't map registers\n"); 98 1.2.10.2 tls return 1; 99 1.2.10.2 tls } 100 1.2.10.2 tls 101 1.2.10.2 tls aprint_normal(": i.MX %sCSPI Controller (clock %ld Hz)\n", 102 1.2.10.2 tls ((sc->sc_enhanced) ? "e" : ""), sc->sc_freq); 103 1.2.10.2 tls 104 1.2.10.2 tls /* Initialize SPI controller */ 105 1.2.10.2 tls sc->sc_spi.sct_cookie = sc; 106 1.2.10.2 tls if (sc->sc_enhanced) 107 1.2.10.2 tls sc->sc_spi.sct_configure = imxspi_configure_enhanced; 108 1.2.10.2 tls else 109 1.2.10.2 tls sc->sc_spi.sct_configure = imxspi_configure; 110 1.2.10.2 tls sc->sc_spi.sct_transfer = imxspi_transfer; 111 1.2.10.2 tls 112 1.2.10.2 tls /* sc->sc_spi.sct_nslaves must have been initialized by machdep code */ 113 1.2.10.2 tls sc->sc_spi.sct_nslaves = saa->saa_nslaves; 114 1.2.10.2 tls if (!sc->sc_spi.sct_nslaves) 115 1.2.10.2 tls aprint_error_dev(sc->sc_dev, "no slaves!\n"); 116 1.2.10.2 tls 117 1.2.10.2 tls sba.sba_controller = &sc->sc_spi; 118 1.2.10.2 tls 119 1.2.10.2 tls /* initialize the queue */ 120 1.2.10.2 tls SIMPLEQ_INIT(&sc->sc_q); 121 1.2.10.2 tls 122 1.2.10.2 tls /* configure SPI */ 123 1.2.10.2 tls /* Setup Control Register */ 124 1.2.10.2 tls WRITE_REG(sc, CONREG, __SHIFTIN(0, IMXSPI(CON_DRCTL)) | 125 1.2.10.2 tls __SHIFTIN(8 - 1, IMXSPI(CON_BITCOUNT)) | 126 1.2.10.2 tls __SHIFTIN(0xf, IMXSPI(CON_MODE)) | IMXSPI(CON_ENABLE)); 127 1.2.10.2 tls 128 1.2.10.2 tls /* TC and RR interruption */ 129 1.2.10.2 tls WRITE_REG(sc, INTREG, (IMXSPI(INTR_TC_EN) | IMXSPI(INTR_RR_EN))); 130 1.2.10.2 tls WRITE_REG(sc, STATREG, IMXSPI(STAT_CLR)); 131 1.2.10.2 tls 132 1.2.10.2 tls WRITE_REG(sc, PERIODREG, 0x0); 133 1.2.10.2 tls 134 1.2.10.2 tls /* enable device interrupts */ 135 1.2.10.2 tls sc->sc_ih = intr_establish(saa->saa_irq, IPL_BIO, IST_LEVEL, 136 1.2.10.2 tls imxspi_intr, sc); 137 1.2.10.2 tls 138 1.2.10.2 tls /* attach slave devices */ 139 1.2.10.2 tls (void)config_found_ia(sc->sc_dev, "spibus", &sba, spibus_print); 140 1.2.10.2 tls 141 1.2.10.2 tls return 0; 142 1.2.10.2 tls } 143 1.2.10.2 tls 144 1.2.10.2 tls static int 145 1.2.10.2 tls imxspi_configure(void *arg, int slave, int mode, int speed) 146 1.2.10.2 tls { 147 1.2.10.2 tls struct imxspi_softc *sc = arg; 148 1.2.10.2 tls uint32_t div_cnt = 0; 149 1.2.10.2 tls uint32_t div; 150 1.2.10.2 tls uint32_t contrl = 0; 151 1.2.10.2 tls 152 1.2.10.2 tls div = (sc->sc_freq + (speed - 1)) / speed; 153 1.2.10.2 tls div = div - 1; 154 1.2.10.2 tls for (div_cnt = 0; div > 0; div_cnt++) 155 1.2.10.2 tls div >>= 1; 156 1.2.10.2 tls 157 1.2.10.2 tls div_cnt = div_cnt - 2; 158 1.2.10.2 tls if (div_cnt >= 7) 159 1.2.10.2 tls div_cnt = 7; 160 1.2.10.2 tls 161 1.2.10.2 tls contrl = READ_REG(sc, CONREG); 162 1.2.10.2 tls contrl &= ~CSPI_CON_DIV; 163 1.2.10.2 tls contrl |= __SHIFTIN(div_cnt, CSPI_CON_DIV); 164 1.2.10.2 tls 165 1.2.10.2 tls contrl &= ~(CSPI_CON_POL | CSPI_CON_PHA); 166 1.2.10.2 tls switch (mode) { 167 1.2.10.2 tls case SPI_MODE_0: 168 1.2.10.2 tls /* CPHA = 0, CPOL = 0 */ 169 1.2.10.2 tls break; 170 1.2.10.2 tls case SPI_MODE_1: 171 1.2.10.2 tls /* CPHA = 1, CPOL = 0 */ 172 1.2.10.2 tls contrl |= CSPI_CON_PHA; 173 1.2.10.2 tls break; 174 1.2.10.2 tls case SPI_MODE_2: 175 1.2.10.2 tls /* CPHA = 0, CPOL = 1 */ 176 1.2.10.2 tls contrl |= CSPI_CON_POL; 177 1.2.10.2 tls break; 178 1.2.10.2 tls case SPI_MODE_3: 179 1.2.10.2 tls /* CPHA = 1, CPOL = 1 */ 180 1.2.10.2 tls contrl |= CSPI_CON_POL; 181 1.2.10.2 tls contrl |= CSPI_CON_PHA; 182 1.2.10.2 tls break; 183 1.2.10.2 tls default: 184 1.2.10.2 tls return EINVAL; 185 1.2.10.2 tls } 186 1.2.10.2 tls WRITE_REG(sc, CONREG, contrl); 187 1.2.10.2 tls 188 1.2.10.2 tls DPRINTFN(3, ("%s: slave %d mode %d speed %d\n", 189 1.2.10.2 tls __func__, slave, mode, speed)); 190 1.2.10.2 tls 191 1.2.10.2 tls return 0; 192 1.2.10.2 tls } 193 1.2.10.2 tls 194 1.2.10.2 tls static int 195 1.2.10.2 tls imxspi_configure_enhanced(void *arg, int slave, int mode, int speed) 196 1.2.10.2 tls { 197 1.2.10.2 tls struct imxspi_softc *sc = arg; 198 1.2.10.2 tls uint32_t div_cnt = 0; 199 1.2.10.2 tls uint32_t div; 200 1.2.10.2 tls uint32_t contrl = 0; 201 1.2.10.2 tls uint32_t config = 0; 202 1.2.10.2 tls 203 1.2.10.2 tls div = (sc->sc_freq + (speed - 1)) / speed; 204 1.2.10.2 tls for (div_cnt = 0; div > 0; div_cnt++) 205 1.2.10.2 tls div >>= 1; 206 1.2.10.2 tls 207 1.2.10.2 tls if (div_cnt >= 15) 208 1.2.10.2 tls div_cnt = 15; 209 1.2.10.2 tls 210 1.2.10.2 tls contrl = READ_REG(sc, CONREG); 211 1.2.10.2 tls contrl |= __SHIFTIN(div_cnt, ECSPI_CON_DIV); 212 1.2.10.2 tls contrl |= __SHIFTIN(slave, ECSPI_CON_CS); 213 1.2.10.2 tls contrl |= __SHIFTIN(__BIT(slave), ECSPI_CON_MODE); 214 1.2.10.2 tls WRITE_REG(sc, CONREG, contrl); 215 1.2.10.2 tls 216 1.2.10.2 tls config = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ECSPI_CONFIGREG); 217 1.2.10.2 tls config &= ~(__SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL) | 218 1.2.10.2 tls __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA)); 219 1.2.10.2 tls switch (mode) { 220 1.2.10.2 tls case SPI_MODE_0: 221 1.2.10.2 tls /* CPHA = 0, CPOL = 0 */ 222 1.2.10.2 tls break; 223 1.2.10.2 tls case SPI_MODE_1: 224 1.2.10.2 tls /* CPHA = 1, CPOL = 0 */ 225 1.2.10.2 tls config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA); 226 1.2.10.2 tls break; 227 1.2.10.2 tls case SPI_MODE_2: 228 1.2.10.2 tls /* CPHA = 0, CPOL = 1 */ 229 1.2.10.2 tls config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL); 230 1.2.10.2 tls break; 231 1.2.10.2 tls case SPI_MODE_3: 232 1.2.10.2 tls /* CPHA = 1, CPOL = 1 */ 233 1.2.10.2 tls config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA); 234 1.2.10.2 tls config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL); 235 1.2.10.2 tls break; 236 1.2.10.2 tls default: 237 1.2.10.2 tls return EINVAL; 238 1.2.10.2 tls } 239 1.2.10.2 tls config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SSB_CTL); 240 1.2.10.2 tls bus_space_write_4(sc->sc_iot, sc->sc_ioh, ECSPI_CONFIGREG, config); 241 1.2.10.2 tls 242 1.2.10.2 tls DPRINTFN(3, ("%s: slave %d mode %d speed %d\n", 243 1.2.10.2 tls __func__, slave, mode, speed)); 244 1.2.10.2 tls 245 1.2.10.2 tls return 0; 246 1.2.10.2 tls } 247 1.2.10.2 tls 248 1.2.10.2 tls void 249 1.2.10.2 tls imxspi_send(struct imxspi_softc *sc) 250 1.2.10.2 tls { 251 1.2.10.2 tls uint32_t data; 252 1.2.10.2 tls struct spi_chunk *chunk; 253 1.2.10.2 tls 254 1.2.10.2 tls /* fill the fifo */ 255 1.2.10.2 tls while ((chunk = sc->sc_wchunk) != NULL) { 256 1.2.10.2 tls while (chunk->chunk_wresid) { 257 1.2.10.2 tls /* transmit fifo full? */ 258 1.2.10.2 tls if (READ_REG(sc, STATREG) & IMXSPI(STAT_TF)) 259 1.2.10.2 tls return; 260 1.2.10.2 tls 261 1.2.10.2 tls if (chunk->chunk_wptr) { 262 1.2.10.2 tls data = *chunk->chunk_wptr; 263 1.2.10.2 tls chunk->chunk_wptr++; 264 1.2.10.2 tls } else { 265 1.2.10.2 tls data = 0xff; 266 1.2.10.2 tls } 267 1.2.10.2 tls chunk->chunk_wresid--; 268 1.2.10.2 tls 269 1.2.10.2 tls WRITE_REG(sc, TXDATA, data); 270 1.2.10.2 tls } 271 1.2.10.2 tls /* advance to next transfer */ 272 1.2.10.2 tls sc->sc_wchunk = sc->sc_wchunk->chunk_next; 273 1.2.10.2 tls } 274 1.2.10.2 tls 275 1.2.10.2 tls if (!(READ_REG(sc, STATREG) & IMXSPI(INTR_TE_EN))) 276 1.2.10.2 tls WRITE_REG(sc, CONREG, READ_REG(sc, CONREG) | IMXSPI(CON_XCH)); 277 1.2.10.2 tls } 278 1.2.10.2 tls 279 1.2.10.2 tls void 280 1.2.10.2 tls imxspi_recv(struct imxspi_softc *sc) 281 1.2.10.2 tls { 282 1.2.10.2 tls uint32_t data; 283 1.2.10.2 tls struct spi_chunk *chunk; 284 1.2.10.2 tls 285 1.2.10.2 tls while ((chunk = sc->sc_rchunk) != NULL) { 286 1.2.10.2 tls while (chunk->chunk_rresid) { 287 1.2.10.2 tls /* rx fifo empty? */ 288 1.2.10.2 tls if ((!(READ_REG(sc, STATREG) & IMXSPI(STAT_RR)))) 289 1.2.10.2 tls return; 290 1.2.10.2 tls 291 1.2.10.2 tls /* collect rx data */ 292 1.2.10.2 tls data = READ_REG(sc, RXDATA); 293 1.2.10.2 tls if (chunk->chunk_rptr) { 294 1.2.10.2 tls *chunk->chunk_rptr = data & 0xff; 295 1.2.10.2 tls chunk->chunk_rptr++; 296 1.2.10.2 tls } 297 1.2.10.2 tls 298 1.2.10.2 tls chunk->chunk_rresid--; 299 1.2.10.2 tls } 300 1.2.10.2 tls /* advance next to next transfer */ 301 1.2.10.2 tls sc->sc_rchunk = sc->sc_rchunk->chunk_next; 302 1.2.10.2 tls } 303 1.2.10.2 tls } 304 1.2.10.2 tls 305 1.2.10.2 tls 306 1.2.10.2 tls void 307 1.2.10.2 tls imxspi_sched(struct imxspi_softc *sc) 308 1.2.10.2 tls { 309 1.2.10.2 tls struct spi_transfer *st; 310 1.2.10.2 tls uint32_t chipselect; 311 1.2.10.2 tls 312 1.2.10.2 tls while ((st = spi_transq_first(&sc->sc_q)) != NULL) { 313 1.2.10.2 tls /* remove the item */ 314 1.2.10.2 tls spi_transq_dequeue(&sc->sc_q); 315 1.2.10.2 tls 316 1.2.10.2 tls /* note that we are working on it */ 317 1.2.10.2 tls sc->sc_transfer = st; 318 1.2.10.2 tls 319 1.2.10.2 tls /* chip slect */ 320 1.2.10.2 tls if (sc->sc_tag->spi_cs_enable != NULL) 321 1.2.10.2 tls sc->sc_tag->spi_cs_enable(sc->sc_tag->cookie, 322 1.2.10.2 tls st->st_slave); 323 1.2.10.2 tls 324 1.2.10.2 tls /*chip slect*/ 325 1.2.10.2 tls chipselect = READ_REG(sc, CONREG); 326 1.2.10.2 tls chipselect &= ~IMXSPI(CON_CS); 327 1.2.10.2 tls chipselect |= __SHIFTIN(st->st_slave, IMXSPI(CON_CS)); 328 1.2.10.2 tls WRITE_REG(sc, CONREG, chipselect); 329 1.2.10.2 tls 330 1.2.10.2 tls delay(1); 331 1.2.10.2 tls 332 1.2.10.2 tls /* setup chunks */ 333 1.2.10.2 tls sc->sc_rchunk = sc->sc_wchunk = st->st_chunks; 334 1.2.10.2 tls 335 1.2.10.2 tls /* now kick the master start to get the chip running */ 336 1.2.10.2 tls imxspi_send(sc); 337 1.2.10.2 tls 338 1.2.10.2 tls sc->sc_running = TRUE; 339 1.2.10.2 tls return; 340 1.2.10.2 tls } 341 1.2.10.2 tls 342 1.2.10.2 tls DPRINTFN(2, ("%s: nothing to do anymore\n", __func__)); 343 1.2.10.2 tls sc->sc_running = FALSE; 344 1.2.10.2 tls } 345 1.2.10.2 tls 346 1.2.10.2 tls void 347 1.2.10.2 tls imxspi_done(struct imxspi_softc *sc, int err) 348 1.2.10.2 tls { 349 1.2.10.2 tls struct spi_transfer *st; 350 1.2.10.2 tls 351 1.2.10.2 tls /* called from interrupt handler */ 352 1.2.10.2 tls if ((st = sc->sc_transfer) != NULL) { 353 1.2.10.2 tls if (sc->sc_tag->spi_cs_disable != NULL) 354 1.2.10.2 tls sc->sc_tag->spi_cs_disable(sc->sc_tag->cookie, 355 1.2.10.2 tls st->st_slave); 356 1.2.10.2 tls 357 1.2.10.2 tls sc->sc_transfer = NULL; 358 1.2.10.2 tls spi_done(st, err); 359 1.2.10.2 tls } 360 1.2.10.2 tls /* make sure we clear these bits out */ 361 1.2.10.2 tls sc->sc_wchunk = sc->sc_rchunk = NULL; 362 1.2.10.2 tls imxspi_sched(sc); 363 1.2.10.2 tls } 364 1.2.10.2 tls 365 1.2.10.2 tls static int 366 1.2.10.2 tls imxspi_intr(void *arg) 367 1.2.10.2 tls { 368 1.2.10.2 tls struct imxspi_softc *sc = arg; 369 1.2.10.2 tls uint32_t intr, sr; 370 1.2.10.2 tls int err = 0; 371 1.2.10.2 tls 372 1.2.10.2 tls if ((intr = READ_REG(sc, INTREG)) == 0) { 373 1.2.10.2 tls /* interrupts are not enabled, get out */ 374 1.2.10.2 tls DPRINTFN(4, ("%s: interrupts are not enabled\n", __func__)); 375 1.2.10.2 tls return 0; 376 1.2.10.2 tls } 377 1.2.10.2 tls 378 1.2.10.2 tls sr = READ_REG(sc, STATREG); 379 1.2.10.2 tls if (!(sr & intr)) { 380 1.2.10.2 tls /* interrupt did not happen, get out */ 381 1.2.10.2 tls DPRINTFN(3, ("%s: interrupts did not happen\n", __func__)); 382 1.2.10.2 tls return 0; 383 1.2.10.2 tls } 384 1.2.10.2 tls 385 1.2.10.2 tls /* Transfer Conplete? */ 386 1.2.10.2 tls if (sr & IMXSPI(INTR_TC_EN)) { 387 1.2.10.2 tls /* complete TX */ 388 1.2.10.2 tls imxspi_send(sc); 389 1.2.10.2 tls } 390 1.2.10.2 tls 391 1.2.10.2 tls /* RXFIFO ready */ 392 1.2.10.2 tls if (sr & IMXSPI(INTR_RR_EN)) { 393 1.2.10.2 tls imxspi_recv(sc); 394 1.2.10.2 tls if (sc->sc_wchunk == NULL && sc->sc_rchunk == NULL) 395 1.2.10.2 tls imxspi_done(sc, err); 396 1.2.10.2 tls } 397 1.2.10.2 tls 398 1.2.10.2 tls /* status register clear */ 399 1.2.10.2 tls WRITE_REG(sc, STATREG, sr); 400 1.2.10.2 tls 401 1.2.10.2 tls return 1; 402 1.2.10.2 tls } 403 1.2.10.2 tls 404 1.2.10.2 tls int 405 1.2.10.2 tls imxspi_transfer(void *arg, struct spi_transfer *st) 406 1.2.10.2 tls { 407 1.2.10.2 tls struct imxspi_softc *sc = arg; 408 1.2.10.2 tls int s; 409 1.2.10.2 tls 410 1.2.10.2 tls /* make sure we select the right chip */ 411 1.2.10.2 tls s = splbio(); 412 1.2.10.2 tls spi_transq_enqueue(&sc->sc_q, st); 413 1.2.10.2 tls if (sc->sc_running == FALSE) 414 1.2.10.2 tls imxspi_sched(sc); 415 1.2.10.2 tls splx(s); 416 1.2.10.2 tls 417 1.2.10.2 tls return 0; 418 1.2.10.2 tls } 419 1.2.10.2 tls 420
Indexes created Tue Sep 30 20:09:53 GMT 2025