imxspi.c revision 1.11
1 /* $NetBSD: imxspi.c,v 1.11 2025/09/10 01:55:07 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * this module support CSPI and eCSPI. 31 * i.MX51 have 2 eCSPI and 1 CSPI modules. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: imxspi.c,v 1.11 2025/09/10 01:55:07 thorpej Exp $"); 36 37 #include "opt_imxspi.h" 38 #include "opt_fdt.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/errno.h> 45 #include <sys/proc.h> 46 #include <sys/intr.h> 47 48 #include <sys/bus.h> 49 #include <machine/cpu.h> 50 #include <machine/intr.h> 51 52 #include <arm/imx/imxspivar.h> 53 #include <arm/imx/imxspireg.h> 54 55 #ifdef FDT 56 #include <dev/fdt/fdtvar.h> 57 #endif 58 59 /* SPI service routines */ 60 static int imxspi_configure_enhanced(void *, int, int, int); 61 static int imxspi_configure(void *, int, int, int); 62 static int imxspi_transfer(void *, struct spi_transfer *); 63 64 /* internal stuff */ 65 void imxspi_done(struct imxspi_softc *, int); 66 void imxspi_send(struct imxspi_softc *); 67 void imxspi_recv(struct imxspi_softc *); 68 void imxspi_sched(struct imxspi_softc *); 69 70 #define IMXCSPI_TYPE(type, x) \ 71 ((sc->sc_type == IMX31_CSPI) ? __CONCAT(CSPI_IMX31_, x) : \ 72 (sc->sc_type == IMX35_CSPI) ? __CONCAT(CSPI_IMX35_, x) : 0) 73 #define IMXCSPI(x) __CONCAT(CSPI_, x) 74 #define IMXESPI(x) __CONCAT(ECSPI_, x) 75 #define IMXSPI(x) ((sc->sc_enhanced) ? IMXESPI(x) : IMXCSPI(x)) 76 #define IMXSPI_TYPE(x) ((sc->sc_enhanced) ? IMXESPI(x) : IMXCSPI_TYPE(sc->sc_type, x)) 77 #define READ_REG(sc, x) \ 78 bus_space_read_4(sc->sc_iot, sc->sc_ioh, IMXSPI(x)) 79 #define WRITE_REG(sc, x, v) \ 80 bus_space_write_4(sc->sc_iot, sc->sc_ioh, IMXSPI(x), (v)) 81 82 #ifdef IMXSPI_DEBUG 83 int imxspi_debug = IMXSPI_DEBUG; 84 #define DPRINTFN(n,x) if (imxspi_debug>(n)) printf x; 85 #else 86 #define DPRINTFN(n,x) 87 #endif 88 89 #ifdef FDT 90 static struct spi_controller * 91 imxspi_get_controller(device_t dev) 92 { 93 struct imxspi_softc * const sc = device_private(dev); 94 95 return &sc->sc_spi; 96 } 97 98 static const struct fdtbus_spi_controller_func imxspi_funcs = { 99 .get_controller = imxspi_get_controller 100 }; 101 #endif 102 103 int 104 imxspi_attach_common(device_t self) 105 { 106 struct imxspi_softc * const sc = device_private(self); 107 108 aprint_normal("i.MX %sCSPI Controller (clock %ld Hz)\n", 109 ((sc->sc_enhanced) ? "e" : ""), sc->sc_freq); 110 111 /* Initialize SPI controller */ 112 sc->sc_dev = self; 113 sc->sc_spi.sct_cookie = sc; 114 if (sc->sc_enhanced) 115 sc->sc_spi.sct_configure = imxspi_configure_enhanced; 116 else 117 sc->sc_spi.sct_configure = imxspi_configure; 118 sc->sc_spi.sct_transfer = imxspi_transfer; 119 120 /* sc->sc_spi.sct_nslaves must have been initialized by machdep code */ 121 sc->sc_spi.sct_nslaves = sc->sc_nslaves; 122 if (!sc->sc_spi.sct_nslaves) 123 aprint_error_dev(sc->sc_dev, "no slaves!\n"); 124 125 /* initialize the queue */ 126 SIMPLEQ_INIT(&sc->sc_q); 127 128 /* configure SPI */ 129 /* Setup Control Register */ 130 WRITE_REG(sc, CONREG, 131 __SHIFTIN(0, IMXSPI_TYPE(CON_DRCTL)) | 132 __SHIFTIN(8 - 1, IMXSPI_TYPE(CON_BITCOUNT)) | 133 __SHIFTIN(0xf, IMXSPI(CON_MODE)) | IMXSPI(CON_ENABLE)); 134 /* TC and RR interruption */ 135 WRITE_REG(sc, INTREG, (IMXSPI_TYPE(INTR_TC_EN) | IMXSPI(INTR_RR_EN))); 136 WRITE_REG(sc, STATREG, IMXSPI_TYPE(STAT_CLR)); 137 138 WRITE_REG(sc, PERIODREG, 0x0); 139 140 #ifdef FDT 141 KASSERT(sc->sc_phandle != 0); 142 143 fdtbus_register_spi_controller(self, sc->sc_phandle, &imxspi_funcs); 144 (void) fdtbus_attach_spibus(self, sc->sc_phandle, spibus_print); 145 #else 146 spibus_attach(self, &sc->sc_spi); 147 #endif 148 149 return 0; 150 } 151 152 static int 153 imxspi_configure(void *arg, int slave, int mode, int speed) 154 { 155 struct imxspi_softc *sc = arg; 156 uint32_t div_cnt = 0; 157 uint32_t div; 158 uint32_t contrl = 0; 159 160 div = (sc->sc_freq + (speed - 1)) / speed; 161 div = div - 1; 162 for (div_cnt = 0; div > 0; div_cnt++) 163 div >>= 1; 164 165 div_cnt = div_cnt - 2; 166 if (div_cnt >= 7) 167 div_cnt = 7; 168 169 contrl = READ_REG(sc, CONREG); 170 contrl &= ~CSPI_CON_DIV; 171 contrl |= __SHIFTIN(div_cnt, CSPI_CON_DIV); 172 173 contrl &= ~(CSPI_CON_POL | CSPI_CON_PHA); 174 switch (mode) { 175 case SPI_MODE_0: 176 /* CPHA = 0, CPOL = 0 */ 177 break; 178 case SPI_MODE_1: 179 /* CPHA = 1, CPOL = 0 */ 180 contrl |= CSPI_CON_PHA; 181 break; 182 case SPI_MODE_2: 183 /* CPHA = 0, CPOL = 1 */ 184 contrl |= CSPI_CON_POL; 185 break; 186 case SPI_MODE_3: 187 /* CPHA = 1, CPOL = 1 */ 188 contrl |= CSPI_CON_POL; 189 contrl |= CSPI_CON_PHA; 190 break; 191 default: 192 return EINVAL; 193 } 194 WRITE_REG(sc, CONREG, contrl); 195 196 DPRINTFN(3, ("%s: slave %d mode %d speed %d\n", 197 __func__, slave, mode, speed)); 198 199 return 0; 200 } 201 202 static int 203 imxspi_configure_enhanced(void *arg, int slave, int mode, int speed) 204 { 205 struct imxspi_softc *sc = arg; 206 uint32_t div_cnt = 0; 207 uint32_t div; 208 uint32_t contrl = 0; 209 uint32_t config = 0; 210 211 div = (sc->sc_freq + (speed - 1)) / speed; 212 for (div_cnt = 0; div > 0; div_cnt++) 213 div >>= 1; 214 215 if (div_cnt >= 15) 216 div_cnt = 15; 217 218 contrl = READ_REG(sc, CONREG); 219 contrl |= __SHIFTIN(div_cnt, ECSPI_CON_DIV); 220 contrl |= __SHIFTIN(slave, ECSPI_CON_CS); 221 contrl |= __SHIFTIN(__BIT(slave), ECSPI_CON_MODE); 222 WRITE_REG(sc, CONREG, contrl); 223 224 config = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ECSPI_CONFIGREG); 225 config &= ~(__SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL) | 226 __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_CTL) | 227 __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA)); 228 switch (mode) { 229 case SPI_MODE_0: 230 /* CPHA = 0, CPOL = 0 */ 231 break; 232 case SPI_MODE_1: 233 /* CPHA = 1, CPOL = 0 */ 234 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA); 235 break; 236 case SPI_MODE_2: 237 /* CPHA = 0, CPOL = 1 */ 238 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL); 239 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_CTL); 240 break; 241 case SPI_MODE_3: 242 /* CPHA = 1, CPOL = 1 */ 243 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA); 244 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL); 245 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_CTL); 246 break; 247 default: 248 return EINVAL; 249 } 250 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SSB_CTL); 251 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ECSPI_CONFIGREG, config); 252 253 DPRINTFN(3, ("%s: slave %d mode %d speed %d\n", 254 __func__, slave, mode, speed)); 255 256 return 0; 257 } 258 259 void 260 imxspi_send(struct imxspi_softc *sc) 261 { 262 uint32_t data; 263 struct spi_chunk *chunk; 264 265 /* fill the fifo */ 266 while ((chunk = sc->sc_wchunk) != NULL) { 267 while (chunk->chunk_wresid) { 268 /* transmit fifo full? */ 269 if (READ_REG(sc, STATREG) & IMXSPI(STAT_TF)) 270 goto out; 271 272 if (chunk->chunk_wptr) { 273 data = *chunk->chunk_wptr; 274 chunk->chunk_wptr++; 275 } else { 276 data = 0xff; 277 } 278 chunk->chunk_wresid--; 279 280 WRITE_REG(sc, TXDATA, data); 281 } 282 /* advance to next transfer */ 283 sc->sc_wchunk = sc->sc_wchunk->chunk_next; 284 } 285 out: 286 if (!(READ_REG(sc, STATREG) & IMXSPI(INTR_TE_EN))) 287 WRITE_REG(sc, CONREG, READ_REG(sc, CONREG) | IMXSPI(CON_XCH)); 288 } 289 290 void 291 imxspi_recv(struct imxspi_softc *sc) 292 { 293 uint32_t data; 294 struct spi_chunk *chunk; 295 296 while ((chunk = sc->sc_rchunk) != NULL) { 297 while (chunk->chunk_rresid) { 298 /* rx fifo empty? */ 299 if ((!(READ_REG(sc, STATREG) & IMXSPI(STAT_RR)))) 300 return; 301 302 /* collect rx data */ 303 data = READ_REG(sc, RXDATA); 304 if (chunk->chunk_rptr) { 305 *chunk->chunk_rptr = data & 0xff; 306 chunk->chunk_rptr++; 307 } 308 309 chunk->chunk_rresid--; 310 } 311 /* advance next to next transfer */ 312 sc->sc_rchunk = sc->sc_rchunk->chunk_next; 313 } 314 } 315 316 317 void 318 imxspi_sched(struct imxspi_softc *sc) 319 { 320 struct spi_transfer *st; 321 uint32_t chipselect; 322 323 while ((st = spi_transq_first(&sc->sc_q)) != NULL) { 324 /* remove the item */ 325 spi_transq_dequeue(&sc->sc_q); 326 327 /* note that we are working on it */ 328 sc->sc_transfer = st; 329 330 /* chip select */ 331 if (sc->sc_tag->spi_cs_enable != NULL) 332 sc->sc_tag->spi_cs_enable(sc->sc_tag->cookie, 333 st->st_slave); 334 335 /* chip select */ 336 chipselect = READ_REG(sc, CONREG); 337 chipselect &= ~IMXSPI_TYPE(CON_CS); 338 chipselect |= __SHIFTIN(st->st_slave, IMXSPI_TYPE(CON_CS)); 339 WRITE_REG(sc, CONREG, chipselect); 340 341 delay(1); 342 343 /* setup chunks */ 344 sc->sc_rchunk = sc->sc_wchunk = st->st_chunks; 345 346 /* now kick the master start to get the chip running */ 347 imxspi_send(sc); 348 349 sc->sc_running = TRUE; 350 return; 351 } 352 353 DPRINTFN(2, ("%s: nothing to do anymore\n", __func__)); 354 sc->sc_running = FALSE; 355 } 356 357 void 358 imxspi_done(struct imxspi_softc *sc, int err) 359 { 360 struct spi_transfer *st; 361 362 /* called from interrupt handler */ 363 if ((st = sc->sc_transfer) != NULL) { 364 if (sc->sc_tag->spi_cs_disable != NULL) 365 sc->sc_tag->spi_cs_disable(sc->sc_tag->cookie, 366 st->st_slave); 367 368 sc->sc_transfer = NULL; 369 spi_done(st, err); 370 } 371 /* make sure we clear these bits out */ 372 sc->sc_wchunk = sc->sc_rchunk = NULL; 373 imxspi_sched(sc); 374 } 375 376 int 377 imxspi_intr(void *arg) 378 { 379 struct imxspi_softc *sc = arg; 380 uint32_t intr, sr; 381 int err = 0; 382 383 if ((intr = READ_REG(sc, INTREG)) == 0) { 384 /* interrupts are not enabled, get out */ 385 DPRINTFN(4, ("%s: interrupts are not enabled\n", __func__)); 386 return 0; 387 } 388 389 sr = READ_REG(sc, STATREG); 390 if (!(sr & intr)) { 391 /* interrupt did not happen, get out */ 392 DPRINTFN(3, ("%s: interrupts did not happen\n", __func__)); 393 return 0; 394 } 395 396 /* RXFIFO ready? */ 397 if (sr & IMXSPI(INTR_RR_EN)) { 398 imxspi_recv(sc); 399 if (sc->sc_wchunk == NULL && sc->sc_rchunk == NULL) 400 imxspi_done(sc, err); 401 } 402 403 /* Transfer Complete? */ 404 if (sr & IMXSPI_TYPE(INTR_TC_EN)) 405 imxspi_send(sc); 406 407 /* status register clear */ 408 WRITE_REG(sc, STATREG, sr); 409 410 return 1; 411 } 412 413 int 414 imxspi_transfer(void *arg, struct spi_transfer *st) 415 { 416 struct imxspi_softc *sc = arg; 417 int s; 418 419 /* make sure we select the right chip */ 420 s = splbio(); 421 spi_transq_enqueue(&sc->sc_q, st); 422 if (sc->sc_running == FALSE) 423 imxspi_sched(sc); 424 splx(s); 425 426 return 0; 427 } 428 429
Indexes created Tue Sep 30 20:09:53 GMT 2025