imxspi.c revision 1.12
1 /* $NetBSD: imxspi.c,v 1.12 2025/09/10 02:21:18 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * this module support CSPI and eCSPI. 31 * i.MX51 have 2 eCSPI and 1 CSPI modules. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: imxspi.c,v 1.12 2025/09/10 02:21:18 thorpej Exp $"); 36 37 #include "opt_imxspi.h" 38 #include "opt_fdt.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/errno.h> 45 #include <sys/proc.h> 46 #include <sys/intr.h> 47 48 #include <sys/bus.h> 49 #include <machine/cpu.h> 50 #include <machine/intr.h> 51 52 #include <arm/imx/imxspivar.h> 53 #include <arm/imx/imxspireg.h> 54 55 #ifdef FDT 56 #include <dev/fdt/fdtvar.h> 57 #endif 58 59 /* SPI service routines */ 60 static int imxspi_configure_enhanced(void *, int, int, int); 61 static int imxspi_configure(void *, int, int, int); 62 static int imxspi_transfer(void *, struct spi_transfer *); 63 64 /* internal stuff */ 65 void imxspi_done(struct imxspi_softc *, int); 66 void imxspi_send(struct imxspi_softc *); 67 void imxspi_recv(struct imxspi_softc *); 68 void imxspi_sched(struct imxspi_softc *); 69 70 #define IMXCSPI_TYPE(type, x) \ 71 ((sc->sc_type == IMX31_CSPI) ? __CONCAT(CSPI_IMX31_, x) : \ 72 (sc->sc_type == IMX35_CSPI) ? __CONCAT(CSPI_IMX35_, x) : 0) 73 #define IMXCSPI(x) __CONCAT(CSPI_, x) 74 #define IMXESPI(x) __CONCAT(ECSPI_, x) 75 #define IMXSPI(x) ((sc->sc_enhanced) ? IMXESPI(x) : IMXCSPI(x)) 76 #define IMXSPI_TYPE(x) ((sc->sc_enhanced) ? IMXESPI(x) : IMXCSPI_TYPE(sc->sc_type, x)) 77 #define READ_REG(sc, x) \ 78 bus_space_read_4(sc->sc_iot, sc->sc_ioh, IMXSPI(x)) 79 #define WRITE_REG(sc, x, v) \ 80 bus_space_write_4(sc->sc_iot, sc->sc_ioh, IMXSPI(x), (v)) 81 82 #ifdef IMXSPI_DEBUG 83 int imxspi_debug = IMXSPI_DEBUG; 84 #define DPRINTFN(n,x) if (imxspi_debug>(n)) printf x; 85 #else 86 #define DPRINTFN(n,x) 87 #endif 88 89 int 90 imxspi_attach_common(device_t self) 91 { 92 struct imxspi_softc * const sc = device_private(self); 93 94 aprint_normal("i.MX %sCSPI Controller (clock %ld Hz)\n", 95 ((sc->sc_enhanced) ? "e" : ""), sc->sc_freq); 96 97 /* Initialize SPI controller */ 98 sc->sc_dev = self; 99 sc->sc_spi.sct_cookie = sc; 100 if (sc->sc_enhanced) 101 sc->sc_spi.sct_configure = imxspi_configure_enhanced; 102 else 103 sc->sc_spi.sct_configure = imxspi_configure; 104 sc->sc_spi.sct_transfer = imxspi_transfer; 105 106 /* sc->sc_spi.sct_nslaves must have been initialized by machdep code */ 107 sc->sc_spi.sct_nslaves = sc->sc_nslaves; 108 if (!sc->sc_spi.sct_nslaves) 109 aprint_error_dev(sc->sc_dev, "no slaves!\n"); 110 111 /* initialize the queue */ 112 SIMPLEQ_INIT(&sc->sc_q); 113 114 /* configure SPI */ 115 /* Setup Control Register */ 116 WRITE_REG(sc, CONREG, 117 __SHIFTIN(0, IMXSPI_TYPE(CON_DRCTL)) | 118 __SHIFTIN(8 - 1, IMXSPI_TYPE(CON_BITCOUNT)) | 119 __SHIFTIN(0xf, IMXSPI(CON_MODE)) | IMXSPI(CON_ENABLE)); 120 /* TC and RR interruption */ 121 WRITE_REG(sc, INTREG, (IMXSPI_TYPE(INTR_TC_EN) | IMXSPI(INTR_RR_EN))); 122 WRITE_REG(sc, STATREG, IMXSPI_TYPE(STAT_CLR)); 123 124 WRITE_REG(sc, PERIODREG, 0x0); 125 126 #ifdef FDT 127 KASSERT(sc->sc_phandle != 0); 128 129 fdtbus_register_spi_controller(self, sc->sc_phandle, &sc->sc_spi); 130 (void) fdtbus_attach_spibus(self, sc->sc_phandle, spibus_print); 131 #else 132 spibus_attach(self, &sc->sc_spi); 133 #endif 134 135 return 0; 136 } 137 138 static int 139 imxspi_configure(void *arg, int slave, int mode, int speed) 140 { 141 struct imxspi_softc *sc = arg; 142 uint32_t div_cnt = 0; 143 uint32_t div; 144 uint32_t contrl = 0; 145 146 div = (sc->sc_freq + (speed - 1)) / speed; 147 div = div - 1; 148 for (div_cnt = 0; div > 0; div_cnt++) 149 div >>= 1; 150 151 div_cnt = div_cnt - 2; 152 if (div_cnt >= 7) 153 div_cnt = 7; 154 155 contrl = READ_REG(sc, CONREG); 156 contrl &= ~CSPI_CON_DIV; 157 contrl |= __SHIFTIN(div_cnt, CSPI_CON_DIV); 158 159 contrl &= ~(CSPI_CON_POL | CSPI_CON_PHA); 160 switch (mode) { 161 case SPI_MODE_0: 162 /* CPHA = 0, CPOL = 0 */ 163 break; 164 case SPI_MODE_1: 165 /* CPHA = 1, CPOL = 0 */ 166 contrl |= CSPI_CON_PHA; 167 break; 168 case SPI_MODE_2: 169 /* CPHA = 0, CPOL = 1 */ 170 contrl |= CSPI_CON_POL; 171 break; 172 case SPI_MODE_3: 173 /* CPHA = 1, CPOL = 1 */ 174 contrl |= CSPI_CON_POL; 175 contrl |= CSPI_CON_PHA; 176 break; 177 default: 178 return EINVAL; 179 } 180 WRITE_REG(sc, CONREG, contrl); 181 182 DPRINTFN(3, ("%s: slave %d mode %d speed %d\n", 183 __func__, slave, mode, speed)); 184 185 return 0; 186 } 187 188 static int 189 imxspi_configure_enhanced(void *arg, int slave, int mode, int speed) 190 { 191 struct imxspi_softc *sc = arg; 192 uint32_t div_cnt = 0; 193 uint32_t div; 194 uint32_t contrl = 0; 195 uint32_t config = 0; 196 197 div = (sc->sc_freq + (speed - 1)) / speed; 198 for (div_cnt = 0; div > 0; div_cnt++) 199 div >>= 1; 200 201 if (div_cnt >= 15) 202 div_cnt = 15; 203 204 contrl = READ_REG(sc, CONREG); 205 contrl |= __SHIFTIN(div_cnt, ECSPI_CON_DIV); 206 contrl |= __SHIFTIN(slave, ECSPI_CON_CS); 207 contrl |= __SHIFTIN(__BIT(slave), ECSPI_CON_MODE); 208 WRITE_REG(sc, CONREG, contrl); 209 210 config = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ECSPI_CONFIGREG); 211 config &= ~(__SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL) | 212 __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_CTL) | 213 __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA)); 214 switch (mode) { 215 case SPI_MODE_0: 216 /* CPHA = 0, CPOL = 0 */ 217 break; 218 case SPI_MODE_1: 219 /* CPHA = 1, CPOL = 0 */ 220 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA); 221 break; 222 case SPI_MODE_2: 223 /* CPHA = 0, CPOL = 1 */ 224 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL); 225 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_CTL); 226 break; 227 case SPI_MODE_3: 228 /* CPHA = 1, CPOL = 1 */ 229 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA); 230 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL); 231 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_CTL); 232 break; 233 default: 234 return EINVAL; 235 } 236 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SSB_CTL); 237 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ECSPI_CONFIGREG, config); 238 239 DPRINTFN(3, ("%s: slave %d mode %d speed %d\n", 240 __func__, slave, mode, speed)); 241 242 return 0; 243 } 244 245 void 246 imxspi_send(struct imxspi_softc *sc) 247 { 248 uint32_t data; 249 struct spi_chunk *chunk; 250 251 /* fill the fifo */ 252 while ((chunk = sc->sc_wchunk) != NULL) { 253 while (chunk->chunk_wresid) { 254 /* transmit fifo full? */ 255 if (READ_REG(sc, STATREG) & IMXSPI(STAT_TF)) 256 goto out; 257 258 if (chunk->chunk_wptr) { 259 data = *chunk->chunk_wptr; 260 chunk->chunk_wptr++; 261 } else { 262 data = 0xff; 263 } 264 chunk->chunk_wresid--; 265 266 WRITE_REG(sc, TXDATA, data); 267 } 268 /* advance to next transfer */ 269 sc->sc_wchunk = sc->sc_wchunk->chunk_next; 270 } 271 out: 272 if (!(READ_REG(sc, STATREG) & IMXSPI(INTR_TE_EN))) 273 WRITE_REG(sc, CONREG, READ_REG(sc, CONREG) | IMXSPI(CON_XCH)); 274 } 275 276 void 277 imxspi_recv(struct imxspi_softc *sc) 278 { 279 uint32_t data; 280 struct spi_chunk *chunk; 281 282 while ((chunk = sc->sc_rchunk) != NULL) { 283 while (chunk->chunk_rresid) { 284 /* rx fifo empty? */ 285 if ((!(READ_REG(sc, STATREG) & IMXSPI(STAT_RR)))) 286 return; 287 288 /* collect rx data */ 289 data = READ_REG(sc, RXDATA); 290 if (chunk->chunk_rptr) { 291 *chunk->chunk_rptr = data & 0xff; 292 chunk->chunk_rptr++; 293 } 294 295 chunk->chunk_rresid--; 296 } 297 /* advance next to next transfer */ 298 sc->sc_rchunk = sc->sc_rchunk->chunk_next; 299 } 300 } 301 302 303 void 304 imxspi_sched(struct imxspi_softc *sc) 305 { 306 struct spi_transfer *st; 307 uint32_t chipselect; 308 309 while ((st = spi_transq_first(&sc->sc_q)) != NULL) { 310 /* remove the item */ 311 spi_transq_dequeue(&sc->sc_q); 312 313 /* note that we are working on it */ 314 sc->sc_transfer = st; 315 316 /* chip select */ 317 if (sc->sc_tag->spi_cs_enable != NULL) 318 sc->sc_tag->spi_cs_enable(sc->sc_tag->cookie, 319 st->st_slave); 320 321 /* chip select */ 322 chipselect = READ_REG(sc, CONREG); 323 chipselect &= ~IMXSPI_TYPE(CON_CS); 324 chipselect |= __SHIFTIN(st->st_slave, IMXSPI_TYPE(CON_CS)); 325 WRITE_REG(sc, CONREG, chipselect); 326 327 delay(1); 328 329 /* setup chunks */ 330 sc->sc_rchunk = sc->sc_wchunk = st->st_chunks; 331 332 /* now kick the master start to get the chip running */ 333 imxspi_send(sc); 334 335 sc->sc_running = TRUE; 336 return; 337 } 338 339 DPRINTFN(2, ("%s: nothing to do anymore\n", __func__)); 340 sc->sc_running = FALSE; 341 } 342 343 void 344 imxspi_done(struct imxspi_softc *sc, int err) 345 { 346 struct spi_transfer *st; 347 348 /* called from interrupt handler */ 349 if ((st = sc->sc_transfer) != NULL) { 350 if (sc->sc_tag->spi_cs_disable != NULL) 351 sc->sc_tag->spi_cs_disable(sc->sc_tag->cookie, 352 st->st_slave); 353 354 sc->sc_transfer = NULL; 355 spi_done(st, err); 356 } 357 /* make sure we clear these bits out */ 358 sc->sc_wchunk = sc->sc_rchunk = NULL; 359 imxspi_sched(sc); 360 } 361 362 int 363 imxspi_intr(void *arg) 364 { 365 struct imxspi_softc *sc = arg; 366 uint32_t intr, sr; 367 int err = 0; 368 369 if ((intr = READ_REG(sc, INTREG)) == 0) { 370 /* interrupts are not enabled, get out */ 371 DPRINTFN(4, ("%s: interrupts are not enabled\n", __func__)); 372 return 0; 373 } 374 375 sr = READ_REG(sc, STATREG); 376 if (!(sr & intr)) { 377 /* interrupt did not happen, get out */ 378 DPRINTFN(3, ("%s: interrupts did not happen\n", __func__)); 379 return 0; 380 } 381 382 /* RXFIFO ready? */ 383 if (sr & IMXSPI(INTR_RR_EN)) { 384 imxspi_recv(sc); 385 if (sc->sc_wchunk == NULL && sc->sc_rchunk == NULL) 386 imxspi_done(sc, err); 387 } 388 389 /* Transfer Complete? */ 390 if (sr & IMXSPI_TYPE(INTR_TC_EN)) 391 imxspi_send(sc); 392 393 /* status register clear */ 394 WRITE_REG(sc, STATREG, sr); 395 396 return 1; 397 } 398 399 int 400 imxspi_transfer(void *arg, struct spi_transfer *st) 401 { 402 struct imxspi_softc *sc = arg; 403 int s; 404 405 /* make sure we select the right chip */ 406 s = splbio(); 407 spi_transq_enqueue(&sc->sc_q, st); 408 if (sc->sc_running == FALSE) 409 imxspi_sched(sc); 410 splx(s); 411 412 return 0; 413 } 414 415
Indexes created Tue Sep 30 20:09:53 GMT 2025