imxspi.c revision 1.13
1 /* $NetBSD: imxspi.c,v 1.13 2025/09/10 02:42:28 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * this module support CSPI and eCSPI. 31 * i.MX51 have 2 eCSPI and 1 CSPI modules. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: imxspi.c,v 1.13 2025/09/10 02:42:28 thorpej Exp $"); 36 37 #include "opt_imxspi.h" 38 #include "opt_fdt.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/errno.h> 45 #include <sys/proc.h> 46 #include <sys/intr.h> 47 48 #include <sys/bus.h> 49 #include <machine/cpu.h> 50 #include <machine/intr.h> 51 52 #include <arm/imx/imxspivar.h> 53 #include <arm/imx/imxspireg.h> 54 55 #ifdef FDT 56 #include <dev/fdt/fdtvar.h> 57 #endif 58 59 /* SPI service routines */ 60 static int imxspi_configure_enhanced(void *, int, int, int); 61 static int imxspi_configure(void *, int, int, int); 62 static int imxspi_transfer(void *, struct spi_transfer *); 63 64 /* internal stuff */ 65 void imxspi_done(struct imxspi_softc *, int); 66 void imxspi_send(struct imxspi_softc *); 67 void imxspi_recv(struct imxspi_softc *); 68 void imxspi_sched(struct imxspi_softc *); 69 70 #define IMXCSPI_TYPE(type, x) \ 71 ((sc->sc_type == IMX31_CSPI) ? __CONCAT(CSPI_IMX31_, x) : \ 72 (sc->sc_type == IMX35_CSPI) ? __CONCAT(CSPI_IMX35_, x) : 0) 73 #define IMXCSPI(x) __CONCAT(CSPI_, x) 74 #define IMXESPI(x) __CONCAT(ECSPI_, x) 75 #define IMXSPI(x) ((sc->sc_enhanced) ? IMXESPI(x) : IMXCSPI(x)) 76 #define IMXSPI_TYPE(x) ((sc->sc_enhanced) ? IMXESPI(x) : IMXCSPI_TYPE(sc->sc_type, x)) 77 #define READ_REG(sc, x) \ 78 bus_space_read_4(sc->sc_iot, sc->sc_ioh, IMXSPI(x)) 79 #define WRITE_REG(sc, x, v) \ 80 bus_space_write_4(sc->sc_iot, sc->sc_ioh, IMXSPI(x), (v)) 81 82 #ifdef IMXSPI_DEBUG 83 int imxspi_debug = IMXSPI_DEBUG; 84 #define DPRINTFN(n,x) if (imxspi_debug>(n)) printf x; 85 #else 86 #define DPRINTFN(n,x) 87 #endif 88 89 int 90 imxspi_attach_common(device_t self) 91 { 92 struct imxspi_softc * const sc = device_private(self); 93 94 aprint_normal("i.MX %sCSPI Controller (clock %ld Hz)\n", 95 ((sc->sc_enhanced) ? "e" : ""), sc->sc_freq); 96 97 /* Initialize SPI controller */ 98 sc->sc_dev = self; 99 sc->sc_spi.sct_cookie = sc; 100 if (sc->sc_enhanced) 101 sc->sc_spi.sct_configure = imxspi_configure_enhanced; 102 else 103 sc->sc_spi.sct_configure = imxspi_configure; 104 sc->sc_spi.sct_transfer = imxspi_transfer; 105 106 /* sc->sc_spi.sct_nslaves must have been initialized by machdep code */ 107 sc->sc_spi.sct_nslaves = sc->sc_nslaves; 108 if (!sc->sc_spi.sct_nslaves) 109 aprint_error_dev(sc->sc_dev, "no slaves!\n"); 110 111 /* initialize the queue */ 112 SIMPLEQ_INIT(&sc->sc_q); 113 114 /* configure SPI */ 115 /* Setup Control Register */ 116 WRITE_REG(sc, CONREG, 117 __SHIFTIN(0, IMXSPI_TYPE(CON_DRCTL)) | 118 __SHIFTIN(8 - 1, IMXSPI_TYPE(CON_BITCOUNT)) | 119 __SHIFTIN(0xf, IMXSPI(CON_MODE)) | IMXSPI(CON_ENABLE)); 120 /* TC and RR interruption */ 121 WRITE_REG(sc, INTREG, (IMXSPI_TYPE(INTR_TC_EN) | IMXSPI(INTR_RR_EN))); 122 WRITE_REG(sc, STATREG, IMXSPI_TYPE(STAT_CLR)); 123 124 WRITE_REG(sc, PERIODREG, 0x0); 125 126 #ifdef FDT 127 fdtbus_register_spi_controller(self, &sc->sc_spi); 128 (void) fdtbus_attach_spibus(self, spibus_print); 129 #else 130 spibus_attach(self, &sc->sc_spi); 131 #endif 132 133 return 0; 134 } 135 136 static int 137 imxspi_configure(void *arg, int slave, int mode, int speed) 138 { 139 struct imxspi_softc *sc = arg; 140 uint32_t div_cnt = 0; 141 uint32_t div; 142 uint32_t contrl = 0; 143 144 div = (sc->sc_freq + (speed - 1)) / speed; 145 div = div - 1; 146 for (div_cnt = 0; div > 0; div_cnt++) 147 div >>= 1; 148 149 div_cnt = div_cnt - 2; 150 if (div_cnt >= 7) 151 div_cnt = 7; 152 153 contrl = READ_REG(sc, CONREG); 154 contrl &= ~CSPI_CON_DIV; 155 contrl |= __SHIFTIN(div_cnt, CSPI_CON_DIV); 156 157 contrl &= ~(CSPI_CON_POL | CSPI_CON_PHA); 158 switch (mode) { 159 case SPI_MODE_0: 160 /* CPHA = 0, CPOL = 0 */ 161 break; 162 case SPI_MODE_1: 163 /* CPHA = 1, CPOL = 0 */ 164 contrl |= CSPI_CON_PHA; 165 break; 166 case SPI_MODE_2: 167 /* CPHA = 0, CPOL = 1 */ 168 contrl |= CSPI_CON_POL; 169 break; 170 case SPI_MODE_3: 171 /* CPHA = 1, CPOL = 1 */ 172 contrl |= CSPI_CON_POL; 173 contrl |= CSPI_CON_PHA; 174 break; 175 default: 176 return EINVAL; 177 } 178 WRITE_REG(sc, CONREG, contrl); 179 180 DPRINTFN(3, ("%s: slave %d mode %d speed %d\n", 181 __func__, slave, mode, speed)); 182 183 return 0; 184 } 185 186 static int 187 imxspi_configure_enhanced(void *arg, int slave, int mode, int speed) 188 { 189 struct imxspi_softc *sc = arg; 190 uint32_t div_cnt = 0; 191 uint32_t div; 192 uint32_t contrl = 0; 193 uint32_t config = 0; 194 195 div = (sc->sc_freq + (speed - 1)) / speed; 196 for (div_cnt = 0; div > 0; div_cnt++) 197 div >>= 1; 198 199 if (div_cnt >= 15) 200 div_cnt = 15; 201 202 contrl = READ_REG(sc, CONREG); 203 contrl |= __SHIFTIN(div_cnt, ECSPI_CON_DIV); 204 contrl |= __SHIFTIN(slave, ECSPI_CON_CS); 205 contrl |= __SHIFTIN(__BIT(slave), ECSPI_CON_MODE); 206 WRITE_REG(sc, CONREG, contrl); 207 208 config = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ECSPI_CONFIGREG); 209 config &= ~(__SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL) | 210 __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_CTL) | 211 __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA)); 212 switch (mode) { 213 case SPI_MODE_0: 214 /* CPHA = 0, CPOL = 0 */ 215 break; 216 case SPI_MODE_1: 217 /* CPHA = 1, CPOL = 0 */ 218 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA); 219 break; 220 case SPI_MODE_2: 221 /* CPHA = 0, CPOL = 1 */ 222 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL); 223 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_CTL); 224 break; 225 case SPI_MODE_3: 226 /* CPHA = 1, CPOL = 1 */ 227 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA); 228 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL); 229 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_CTL); 230 break; 231 default: 232 return EINVAL; 233 } 234 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SSB_CTL); 235 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ECSPI_CONFIGREG, config); 236 237 DPRINTFN(3, ("%s: slave %d mode %d speed %d\n", 238 __func__, slave, mode, speed)); 239 240 return 0; 241 } 242 243 void 244 imxspi_send(struct imxspi_softc *sc) 245 { 246 uint32_t data; 247 struct spi_chunk *chunk; 248 249 /* fill the fifo */ 250 while ((chunk = sc->sc_wchunk) != NULL) { 251 while (chunk->chunk_wresid) { 252 /* transmit fifo full? */ 253 if (READ_REG(sc, STATREG) & IMXSPI(STAT_TF)) 254 goto out; 255 256 if (chunk->chunk_wptr) { 257 data = *chunk->chunk_wptr; 258 chunk->chunk_wptr++; 259 } else { 260 data = 0xff; 261 } 262 chunk->chunk_wresid--; 263 264 WRITE_REG(sc, TXDATA, data); 265 } 266 /* advance to next transfer */ 267 sc->sc_wchunk = sc->sc_wchunk->chunk_next; 268 } 269 out: 270 if (!(READ_REG(sc, STATREG) & IMXSPI(INTR_TE_EN))) 271 WRITE_REG(sc, CONREG, READ_REG(sc, CONREG) | IMXSPI(CON_XCH)); 272 } 273 274 void 275 imxspi_recv(struct imxspi_softc *sc) 276 { 277 uint32_t data; 278 struct spi_chunk *chunk; 279 280 while ((chunk = sc->sc_rchunk) != NULL) { 281 while (chunk->chunk_rresid) { 282 /* rx fifo empty? */ 283 if ((!(READ_REG(sc, STATREG) & IMXSPI(STAT_RR)))) 284 return; 285 286 /* collect rx data */ 287 data = READ_REG(sc, RXDATA); 288 if (chunk->chunk_rptr) { 289 *chunk->chunk_rptr = data & 0xff; 290 chunk->chunk_rptr++; 291 } 292 293 chunk->chunk_rresid--; 294 } 295 /* advance next to next transfer */ 296 sc->sc_rchunk = sc->sc_rchunk->chunk_next; 297 } 298 } 299 300 301 void 302 imxspi_sched(struct imxspi_softc *sc) 303 { 304 struct spi_transfer *st; 305 uint32_t chipselect; 306 307 while ((st = spi_transq_first(&sc->sc_q)) != NULL) { 308 /* remove the item */ 309 spi_transq_dequeue(&sc->sc_q); 310 311 /* note that we are working on it */ 312 sc->sc_transfer = st; 313 314 /* chip select */ 315 if (sc->sc_tag->spi_cs_enable != NULL) 316 sc->sc_tag->spi_cs_enable(sc->sc_tag->cookie, 317 st->st_slave); 318 319 /* chip select */ 320 chipselect = READ_REG(sc, CONREG); 321 chipselect &= ~IMXSPI_TYPE(CON_CS); 322 chipselect |= __SHIFTIN(st->st_slave, IMXSPI_TYPE(CON_CS)); 323 WRITE_REG(sc, CONREG, chipselect); 324 325 delay(1); 326 327 /* setup chunks */ 328 sc->sc_rchunk = sc->sc_wchunk = st->st_chunks; 329 330 /* now kick the master start to get the chip running */ 331 imxspi_send(sc); 332 333 sc->sc_running = TRUE; 334 return; 335 } 336 337 DPRINTFN(2, ("%s: nothing to do anymore\n", __func__)); 338 sc->sc_running = FALSE; 339 } 340 341 void 342 imxspi_done(struct imxspi_softc *sc, int err) 343 { 344 struct spi_transfer *st; 345 346 /* called from interrupt handler */ 347 if ((st = sc->sc_transfer) != NULL) { 348 if (sc->sc_tag->spi_cs_disable != NULL) 349 sc->sc_tag->spi_cs_disable(sc->sc_tag->cookie, 350 st->st_slave); 351 352 sc->sc_transfer = NULL; 353 spi_done(st, err); 354 } 355 /* make sure we clear these bits out */ 356 sc->sc_wchunk = sc->sc_rchunk = NULL; 357 imxspi_sched(sc); 358 } 359 360 int 361 imxspi_intr(void *arg) 362 { 363 struct imxspi_softc *sc = arg; 364 uint32_t intr, sr; 365 int err = 0; 366 367 if ((intr = READ_REG(sc, INTREG)) == 0) { 368 /* interrupts are not enabled, get out */ 369 DPRINTFN(4, ("%s: interrupts are not enabled\n", __func__)); 370 return 0; 371 } 372 373 sr = READ_REG(sc, STATREG); 374 if (!(sr & intr)) { 375 /* interrupt did not happen, get out */ 376 DPRINTFN(3, ("%s: interrupts did not happen\n", __func__)); 377 return 0; 378 } 379 380 /* RXFIFO ready? */ 381 if (sr & IMXSPI(INTR_RR_EN)) { 382 imxspi_recv(sc); 383 if (sc->sc_wchunk == NULL && sc->sc_rchunk == NULL) 384 imxspi_done(sc, err); 385 } 386 387 /* Transfer Complete? */ 388 if (sr & IMXSPI_TYPE(INTR_TC_EN)) 389 imxspi_send(sc); 390 391 /* status register clear */ 392 WRITE_REG(sc, STATREG, sr); 393 394 return 1; 395 } 396 397 int 398 imxspi_transfer(void *arg, struct spi_transfer *st) 399 { 400 struct imxspi_softc *sc = arg; 401 int s; 402 403 /* make sure we select the right chip */ 404 s = splbio(); 405 spi_transq_enqueue(&sc->sc_q, st); 406 if (sc->sc_running == FALSE) 407 imxspi_sched(sc); 408 splx(s); 409 410 return 0; 411 } 412 413
Indexes created Tue Sep 30 20:09:53 GMT 2025