imxspi.c revision 1.14
1 /* $NetBSD: imxspi.c,v 1.14 2025/09/10 03:16:57 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * this module support CSPI and eCSPI. 31 * i.MX51 have 2 eCSPI and 1 CSPI modules. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: imxspi.c,v 1.14 2025/09/10 03:16:57 thorpej Exp $"); 36 37 #include "opt_imxspi.h" 38 #include "opt_fdt.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/errno.h> 45 #include <sys/proc.h> 46 #include <sys/intr.h> 47 48 #include <sys/bus.h> 49 #include <machine/cpu.h> 50 #include <machine/intr.h> 51 52 #include <arm/imx/imxspivar.h> 53 #include <arm/imx/imxspireg.h> 54 55 #ifdef FDT 56 #include <dev/fdt/fdtvar.h> 57 #endif 58 59 /* SPI service routines */ 60 static int imxspi_configure_enhanced(void *, int, int, int); 61 static int imxspi_configure(void *, int, int, int); 62 static int imxspi_transfer(void *, struct spi_transfer *); 63 64 /* internal stuff */ 65 void imxspi_done(struct imxspi_softc *, int); 66 void imxspi_send(struct imxspi_softc *); 67 void imxspi_recv(struct imxspi_softc *); 68 void imxspi_sched(struct imxspi_softc *); 69 70 #define IMXCSPI_TYPE(type, x) \ 71 ((sc->sc_type == IMX31_CSPI) ? __CONCAT(CSPI_IMX31_, x) : \ 72 (sc->sc_type == IMX35_CSPI) ? __CONCAT(CSPI_IMX35_, x) : 0) 73 #define IMXCSPI(x) __CONCAT(CSPI_, x) 74 #define IMXESPI(x) __CONCAT(ECSPI_, x) 75 #define IMXSPI(x) ((sc->sc_enhanced) ? IMXESPI(x) : IMXCSPI(x)) 76 #define IMXSPI_TYPE(x) ((sc->sc_enhanced) ? IMXESPI(x) : IMXCSPI_TYPE(sc->sc_type, x)) 77 #define READ_REG(sc, x) \ 78 bus_space_read_4(sc->sc_iot, sc->sc_ioh, IMXSPI(x)) 79 #define WRITE_REG(sc, x, v) \ 80 bus_space_write_4(sc->sc_iot, sc->sc_ioh, IMXSPI(x), (v)) 81 82 #ifdef IMXSPI_DEBUG 83 int imxspi_debug = IMXSPI_DEBUG; 84 #define DPRINTFN(n,x) if (imxspi_debug>(n)) printf x; 85 #else 86 #define DPRINTFN(n,x) 87 #endif 88 89 int 90 imxspi_attach_common(device_t self) 91 { 92 struct imxspi_softc * const sc = device_private(self); 93 94 aprint_normal("i.MX %sCSPI Controller (clock %ld Hz)\n", 95 ((sc->sc_enhanced) ? "e" : ""), sc->sc_freq); 96 97 /* Initialize SPI controller */ 98 sc->sc_dev = self; 99 sc->sc_spi.sct_cookie = sc; 100 if (sc->sc_enhanced) 101 sc->sc_spi.sct_configure = imxspi_configure_enhanced; 102 else 103 sc->sc_spi.sct_configure = imxspi_configure; 104 sc->sc_spi.sct_transfer = imxspi_transfer; 105 106 /* sc->sc_spi.sct_nslaves must have been initialized by machdep code */ 107 sc->sc_spi.sct_nslaves = sc->sc_nslaves; 108 if (!sc->sc_spi.sct_nslaves) 109 aprint_error_dev(sc->sc_dev, "no slaves!\n"); 110 111 /* initialize the queue */ 112 SIMPLEQ_INIT(&sc->sc_q); 113 114 /* configure SPI */ 115 /* Setup Control Register */ 116 WRITE_REG(sc, CONREG, 117 __SHIFTIN(0, IMXSPI_TYPE(CON_DRCTL)) | 118 __SHIFTIN(8 - 1, IMXSPI_TYPE(CON_BITCOUNT)) | 119 __SHIFTIN(0xf, IMXSPI(CON_MODE)) | IMXSPI(CON_ENABLE)); 120 /* TC and RR interruption */ 121 WRITE_REG(sc, INTREG, (IMXSPI_TYPE(INTR_TC_EN) | IMXSPI(INTR_RR_EN))); 122 WRITE_REG(sc, STATREG, IMXSPI_TYPE(STAT_CLR)); 123 124 WRITE_REG(sc, PERIODREG, 0x0); 125 126 #ifdef FDT 127 (void) fdtbus_attach_spibus(self, spibus_print); 128 #else 129 spibus_attach(self, &sc->sc_spi); 130 #endif 131 132 return 0; 133 } 134 135 static int 136 imxspi_configure(void *arg, int slave, int mode, int speed) 137 { 138 struct imxspi_softc *sc = arg; 139 uint32_t div_cnt = 0; 140 uint32_t div; 141 uint32_t contrl = 0; 142 143 div = (sc->sc_freq + (speed - 1)) / speed; 144 div = div - 1; 145 for (div_cnt = 0; div > 0; div_cnt++) 146 div >>= 1; 147 148 div_cnt = div_cnt - 2; 149 if (div_cnt >= 7) 150 div_cnt = 7; 151 152 contrl = READ_REG(sc, CONREG); 153 contrl &= ~CSPI_CON_DIV; 154 contrl |= __SHIFTIN(div_cnt, CSPI_CON_DIV); 155 156 contrl &= ~(CSPI_CON_POL | CSPI_CON_PHA); 157 switch (mode) { 158 case SPI_MODE_0: 159 /* CPHA = 0, CPOL = 0 */ 160 break; 161 case SPI_MODE_1: 162 /* CPHA = 1, CPOL = 0 */ 163 contrl |= CSPI_CON_PHA; 164 break; 165 case SPI_MODE_2: 166 /* CPHA = 0, CPOL = 1 */ 167 contrl |= CSPI_CON_POL; 168 break; 169 case SPI_MODE_3: 170 /* CPHA = 1, CPOL = 1 */ 171 contrl |= CSPI_CON_POL; 172 contrl |= CSPI_CON_PHA; 173 break; 174 default: 175 return EINVAL; 176 } 177 WRITE_REG(sc, CONREG, contrl); 178 179 DPRINTFN(3, ("%s: slave %d mode %d speed %d\n", 180 __func__, slave, mode, speed)); 181 182 return 0; 183 } 184 185 static int 186 imxspi_configure_enhanced(void *arg, int slave, int mode, int speed) 187 { 188 struct imxspi_softc *sc = arg; 189 uint32_t div_cnt = 0; 190 uint32_t div; 191 uint32_t contrl = 0; 192 uint32_t config = 0; 193 194 div = (sc->sc_freq + (speed - 1)) / speed; 195 for (div_cnt = 0; div > 0; div_cnt++) 196 div >>= 1; 197 198 if (div_cnt >= 15) 199 div_cnt = 15; 200 201 contrl = READ_REG(sc, CONREG); 202 contrl |= __SHIFTIN(div_cnt, ECSPI_CON_DIV); 203 contrl |= __SHIFTIN(slave, ECSPI_CON_CS); 204 contrl |= __SHIFTIN(__BIT(slave), ECSPI_CON_MODE); 205 WRITE_REG(sc, CONREG, contrl); 206 207 config = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ECSPI_CONFIGREG); 208 config &= ~(__SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL) | 209 __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_CTL) | 210 __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA)); 211 switch (mode) { 212 case SPI_MODE_0: 213 /* CPHA = 0, CPOL = 0 */ 214 break; 215 case SPI_MODE_1: 216 /* CPHA = 1, CPOL = 0 */ 217 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA); 218 break; 219 case SPI_MODE_2: 220 /* CPHA = 0, CPOL = 1 */ 221 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL); 222 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_CTL); 223 break; 224 case SPI_MODE_3: 225 /* CPHA = 1, CPOL = 1 */ 226 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA); 227 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL); 228 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_CTL); 229 break; 230 default: 231 return EINVAL; 232 } 233 config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SSB_CTL); 234 bus_space_write_4(sc->sc_iot, sc->sc_ioh, ECSPI_CONFIGREG, config); 235 236 DPRINTFN(3, ("%s: slave %d mode %d speed %d\n", 237 __func__, slave, mode, speed)); 238 239 return 0; 240 } 241 242 void 243 imxspi_send(struct imxspi_softc *sc) 244 { 245 uint32_t data; 246 struct spi_chunk *chunk; 247 248 /* fill the fifo */ 249 while ((chunk = sc->sc_wchunk) != NULL) { 250 while (chunk->chunk_wresid) { 251 /* transmit fifo full? */ 252 if (READ_REG(sc, STATREG) & IMXSPI(STAT_TF)) 253 goto out; 254 255 if (chunk->chunk_wptr) { 256 data = *chunk->chunk_wptr; 257 chunk->chunk_wptr++; 258 } else { 259 data = 0xff; 260 } 261 chunk->chunk_wresid--; 262 263 WRITE_REG(sc, TXDATA, data); 264 } 265 /* advance to next transfer */ 266 sc->sc_wchunk = sc->sc_wchunk->chunk_next; 267 } 268 out: 269 if (!(READ_REG(sc, STATREG) & IMXSPI(INTR_TE_EN))) 270 WRITE_REG(sc, CONREG, READ_REG(sc, CONREG) | IMXSPI(CON_XCH)); 271 } 272 273 void 274 imxspi_recv(struct imxspi_softc *sc) 275 { 276 uint32_t data; 277 struct spi_chunk *chunk; 278 279 while ((chunk = sc->sc_rchunk) != NULL) { 280 while (chunk->chunk_rresid) { 281 /* rx fifo empty? */ 282 if ((!(READ_REG(sc, STATREG) & IMXSPI(STAT_RR)))) 283 return; 284 285 /* collect rx data */ 286 data = READ_REG(sc, RXDATA); 287 if (chunk->chunk_rptr) { 288 *chunk->chunk_rptr = data & 0xff; 289 chunk->chunk_rptr++; 290 } 291 292 chunk->chunk_rresid--; 293 } 294 /* advance next to next transfer */ 295 sc->sc_rchunk = sc->sc_rchunk->chunk_next; 296 } 297 } 298 299 300 void 301 imxspi_sched(struct imxspi_softc *sc) 302 { 303 struct spi_transfer *st; 304 uint32_t chipselect; 305 306 while ((st = spi_transq_first(&sc->sc_q)) != NULL) { 307 /* remove the item */ 308 spi_transq_dequeue(&sc->sc_q); 309 310 /* note that we are working on it */ 311 sc->sc_transfer = st; 312 313 /* chip select */ 314 if (sc->sc_tag->spi_cs_enable != NULL) 315 sc->sc_tag->spi_cs_enable(sc->sc_tag->cookie, 316 st->st_slave); 317 318 /* chip select */ 319 chipselect = READ_REG(sc, CONREG); 320 chipselect &= ~IMXSPI_TYPE(CON_CS); 321 chipselect |= __SHIFTIN(st->st_slave, IMXSPI_TYPE(CON_CS)); 322 WRITE_REG(sc, CONREG, chipselect); 323 324 delay(1); 325 326 /* setup chunks */ 327 sc->sc_rchunk = sc->sc_wchunk = st->st_chunks; 328 329 /* now kick the master start to get the chip running */ 330 imxspi_send(sc); 331 332 sc->sc_running = TRUE; 333 return; 334 } 335 336 DPRINTFN(2, ("%s: nothing to do anymore\n", __func__)); 337 sc->sc_running = FALSE; 338 } 339 340 void 341 imxspi_done(struct imxspi_softc *sc, int err) 342 { 343 struct spi_transfer *st; 344 345 /* called from interrupt handler */ 346 if ((st = sc->sc_transfer) != NULL) { 347 if (sc->sc_tag->spi_cs_disable != NULL) 348 sc->sc_tag->spi_cs_disable(sc->sc_tag->cookie, 349 st->st_slave); 350 351 sc->sc_transfer = NULL; 352 spi_done(st, err); 353 } 354 /* make sure we clear these bits out */ 355 sc->sc_wchunk = sc->sc_rchunk = NULL; 356 imxspi_sched(sc); 357 } 358 359 int 360 imxspi_intr(void *arg) 361 { 362 struct imxspi_softc *sc = arg; 363 uint32_t intr, sr; 364 int err = 0; 365 366 if ((intr = READ_REG(sc, INTREG)) == 0) { 367 /* interrupts are not enabled, get out */ 368 DPRINTFN(4, ("%s: interrupts are not enabled\n", __func__)); 369 return 0; 370 } 371 372 sr = READ_REG(sc, STATREG); 373 if (!(sr & intr)) { 374 /* interrupt did not happen, get out */ 375 DPRINTFN(3, ("%s: interrupts did not happen\n", __func__)); 376 return 0; 377 } 378 379 /* RXFIFO ready? */ 380 if (sr & IMXSPI(INTR_RR_EN)) { 381 imxspi_recv(sc); 382 if (sc->sc_wchunk == NULL && sc->sc_rchunk == NULL) 383 imxspi_done(sc, err); 384 } 385 386 /* Transfer Complete? */ 387 if (sr & IMXSPI_TYPE(INTR_TC_EN)) 388 imxspi_send(sc); 389 390 /* status register clear */ 391 WRITE_REG(sc, STATREG, sr); 392 393 return 1; 394 } 395 396 int 397 imxspi_transfer(void *arg, struct spi_transfer *st) 398 { 399 struct imxspi_softc *sc = arg; 400 int s; 401 402 /* make sure we select the right chip */ 403 s = splbio(); 404 spi_transq_enqueue(&sc->sc_q, st); 405 if (sc->sc_running == FALSE) 406 imxspi_sched(sc); 407 splx(s); 408 409 return 0; 410 } 411 412
Indexes created Tue Sep 30 20:09:53 GMT 2025