imxspivar.h revision 1.1.10.2
1 1.1.10.2 tls /* $NetBSD: imxspivar.h,v 1.1.10.2 2014/08/20 00:02:46 tls Exp $ */ 2 1.1.10.2 tls 3 1.1.10.2 tls /* 4 1.1.10.2 tls * Copyright (c) 2014 Genetec Corporation. All rights reserved. 5 1.1.10.2 tls * Written by Hashimoto Kenichi for Genetec Corporation. 6 1.1.10.2 tls * 7 1.1.10.2 tls * Redistribution and use in source and binary forms, with or without 8 1.1.10.2 tls * modification, are permitted provided that the following conditions 9 1.1.10.2 tls * are met: 10 1.1.10.2 tls * 1. Redistributions of source code must retain the above copyright 11 1.1.10.2 tls * notice, this list of conditions and the following disclaimer. 12 1.1.10.2 tls * 2. Redistributions in binary form must reproduce the above copyright 13 1.1.10.2 tls * notice, this list of conditions and the following disclaimer in the 14 1.1.10.2 tls * documentation and/or other materials provided with the distribution. 15 1.1.10.2 tls * 16 1.1.10.2 tls * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 17 1.1.10.2 tls * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 1.1.10.2 tls * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 1.1.10.2 tls * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 20 1.1.10.2 tls * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 1.1.10.2 tls * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 1.1.10.2 tls * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 1.1.10.2 tls * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 1.1.10.2 tls * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 1.1.10.2 tls * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 1.1.10.2 tls * POSSIBILITY OF SUCH DAMAGE. 27 1.1.10.2 tls */ 28 1.1.10.2 tls 29 1.1.10.2 tls #ifndef _ARM_IMX_IMXSPIVAR_H_ 30 1.1.10.2 tls #define _ARM_IMX_IMXSPIVAR_H_ 31 1.1.10.2 tls 32 1.1.10.2 tls #include <dev/spi/spivar.h> 33 1.1.10.2 tls 34 1.1.10.2 tls typedef struct spi_chipset_tag { 35 1.1.10.2 tls void *cookie; 36 1.1.10.2 tls 37 1.1.10.2 tls int (*spi_cs_enable)(void *, int); 38 1.1.10.2 tls int (*spi_cs_disable)(void *, int); 39 1.1.10.2 tls } *spi_chipset_tag_t; 40 1.1.10.2 tls 41 1.1.10.2 tls struct imxspi_attach_args { 42 1.1.10.2 tls bus_space_tag_t saa_iot; 43 1.1.10.2 tls bus_addr_t saa_addr; 44 1.1.10.2 tls bus_size_t saa_size; 45 1.1.10.2 tls int saa_irq; 46 1.1.10.2 tls 47 1.1.10.2 tls spi_chipset_tag_t saa_tag; 48 1.1.10.2 tls int saa_nslaves; 49 1.1.10.2 tls unsigned long saa_freq; 50 1.1.10.2 tls 51 1.1.10.2 tls int saa_enhanced; 52 1.1.10.2 tls }; 53 1.1.10.2 tls 54 1.1.10.2 tls struct imxspi_softc { 55 1.1.10.2 tls device_t sc_dev; 56 1.1.10.2 tls bus_space_tag_t sc_iot; 57 1.1.10.2 tls bus_space_handle_t sc_ioh; 58 1.1.10.2 tls spi_chipset_tag_t sc_tag; 59 1.1.10.2 tls 60 1.1.10.2 tls struct spi_controller sc_spi; 61 1.1.10.2 tls unsigned long sc_freq; 62 1.1.10.2 tls struct spi_chunk *sc_wchunk; 63 1.1.10.2 tls struct spi_chunk *sc_rchunk; 64 1.1.10.2 tls void *sc_ih; 65 1.1.10.2 tls struct spi_transfer *sc_transfer; 66 1.1.10.2 tls bool sc_running; 67 1.1.10.2 tls SIMPLEQ_HEAD(,spi_transfer) sc_q; 68 1.1.10.2 tls 69 1.1.10.2 tls int sc_enhanced; 70 1.1.10.2 tls }; 71 1.1.10.2 tls 72 1.1.10.2 tls int imxspi_attach_common(device_t, struct imxspi_softc *, void *); 73 1.1.10.2 tls 74 1.1.10.2 tls /* 75 1.1.10.2 tls * defined in machine dependent code 76 1.1.10.2 tls */ 77 1.1.10.2 tls int imxspi_match(device_t, cfdata_t, void *); 78 1.1.10.2 tls void imxspi_attach(device_t, device_t, void *); 79 1.1.10.2 tls 80 1.1.10.2 tls #endif /* _ARM_IMX_IMXSPIVAR_H_ */ 81
Indexes created Wed Oct 22 06:10:02 GMT 2025