imxuart.c revision 1.13
1 /* $NetBSD: imxuart.c,v 1.13 2014/07/25 08:10:32 dholland Exp $ */ 2 3 /* 4 * Copyright (c) 2009, 2010 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* 31 * derived from sys/dev/ic/com.c 32 */ 33 34 /*- 35 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to The NetBSD Foundation 39 * by Charles M. Hannum. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 51 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 52 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 53 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 60 * POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Copyright (c) 1991 The Regents of the University of California. 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 3. Neither the name of the University nor the names of its contributors 76 * may be used to endorse or promote products derived from this software 77 * without specific prior written permission. 78 * 79 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 80 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 82 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 85 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 86 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 87 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 88 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 89 * SUCH DAMAGE. 90 * 91 * @(#)com.c 7.5 (Berkeley) 5/16/91 92 */ 93 94 /* 95 * driver for UART in i.MX SoC. 96 */ 97 98 #include <sys/cdefs.h> 99 __KERNEL_RCSID(0, "$NetBSD: imxuart.c,v 1.13 2014/07/25 08:10:32 dholland Exp $"); 100 101 #include "opt_imxuart.h" 102 #include "opt_ddb.h" 103 #include "opt_kgdb.h" 104 #include "opt_lockdebug.h" 105 #include "opt_multiprocessor.h" 106 #include "opt_ntp.h" 107 #include "opt_imxuart.h" 108 #include "opt_imx.h" 109 110 #include "rnd.h" 111 #ifdef RND_COM 112 #include <sys/rnd.h> 113 #endif 114 115 #ifndef IMXUART_TOLERANCE 116 #define IMXUART_TOLERANCE 30 /* baud rate tolerance, in 0.1% units */ 117 #endif 118 119 #ifndef IMXUART_FREQDIV 120 #define IMXUART_FREQDIV 2 /* XXX */ 121 #endif 122 123 #ifndef IMXUART_FREQ 124 #define IMXUART_FREQ (56900000) 125 #endif 126 127 /* 128 * Override cnmagic(9) macro before including <sys/systm.h>. 129 * We need to know if cn_check_magic triggered debugger, so set a flag. 130 * Callers of cn_check_magic must declare int cn_trapped = 0; 131 * XXX: this is *ugly*! 132 */ 133 #define cn_trap() \ 134 do { \ 135 console_debugger(); \ 136 cn_trapped = 1; \ 137 } while (/* CONSTCOND */ 0) 138 139 #include <sys/param.h> 140 #include <sys/systm.h> 141 #include <sys/ioctl.h> 142 #include <sys/select.h> 143 #include <sys/poll.h> 144 #include <sys/tty.h> 145 #include <sys/proc.h> 146 #include <sys/conf.h> 147 #include <sys/file.h> 148 #include <sys/uio.h> 149 #include <sys/kernel.h> 150 #include <sys/syslog.h> 151 #include <sys/device.h> 152 #include <sys/malloc.h> 153 #include <sys/timepps.h> 154 #include <sys/vnode.h> 155 #include <sys/kauth.h> 156 #include <sys/intr.h> 157 158 #include <sys/bus.h> 159 160 #include <arm/imx/imxuartreg.h> 161 #include <arm/imx/imxuartvar.h> 162 #include <dev/cons.h> 163 164 #ifndef IMXUART_RING_SIZE 165 #define IMXUART_RING_SIZE 2048 166 #endif 167 168 typedef struct imxuart_softc { 169 device_t sc_dev; 170 171 struct imxuart_regs { 172 bus_space_tag_t ur_iot; 173 bus_space_handle_t ur_ioh; 174 bus_addr_t ur_iobase; 175 #if 0 176 bus_size_t ur_nports; 177 bus_size_t ur_map[16]; 178 #endif 179 } sc_regs; 180 181 #define sc_bt sc_regs.ur_iot 182 #define sc_bh sc_regs.ur_ioh 183 184 uint32_t sc_intrspec_enb; 185 uint32_t sc_ucr2_d; /* target value for UCR2 */ 186 uint32_t sc_ucr[4]; /* cached value of UCRn */ 187 #define sc_ucr1 sc_ucr[0] 188 #define sc_ucr2 sc_ucr[1] 189 #define sc_ucr3 sc_ucr[2] 190 #define sc_ucr4 sc_ucr[3] 191 192 uint sc_init_cnt; 193 194 bus_addr_t sc_addr; 195 bus_size_t sc_size; 196 int sc_intr; 197 198 u_char sc_hwflags; 199 /* Hardware flag masks */ 200 #define IMXUART_HW_FLOW __BIT(0) 201 #define IMXUART_HW_DEV_OK __BIT(1) 202 #define IMXUART_HW_CONSOLE __BIT(2) 203 #define IMXUART_HW_KGDB __BIT(3) 204 205 206 bool enabled; 207 208 u_char sc_swflags; 209 210 u_char sc_rx_flags; 211 #define IMXUART_RX_TTY_BLOCKED __BIT(0) 212 #define IMXUART_RX_TTY_OVERFLOWED __BIT(1) 213 #define IMXUART_RX_IBUF_BLOCKED __BIT(2) 214 #define IMXUART_RX_IBUF_OVERFLOWED __BIT(3) 215 #define IMXUART_RX_ANY_BLOCK \ 216 (IMXUART_RX_TTY_BLOCKED|IMXUART_RX_TTY_OVERFLOWED| \ 217 IMXUART_RX_IBUF_BLOCKED|IMXUART_RX_IBUF_OVERFLOWED) 218 219 bool sc_tx_busy, sc_tx_done, sc_tx_stopped; 220 bool sc_rx_ready,sc_st_check; 221 u_short sc_txfifo_len, sc_txfifo_thresh; 222 223 uint16_t *sc_rbuf; 224 u_int sc_rbuf_size; 225 u_int sc_rbuf_in; 226 u_int sc_rbuf_out; 227 #define IMXUART_RBUF_AVAIL(sc) \ 228 ((sc->sc_rbuf_out <= sc->sc_rbuf_in) ? \ 229 (sc->sc_rbuf_in - sc->sc_rbuf_out) : \ 230 (sc->sc_rbuf_size - (sc->sc_rbuf_out - sc->sc_rbuf_in))) 231 232 #define IMXUART_RBUF_SPACE(sc) \ 233 ((sc->sc_rbuf_in <= sc->sc_rbuf_out ? \ 234 sc->sc_rbuf_size - (sc->sc_rbuf_out - sc->sc_rbuf_in) : \ 235 sc->sc_rbuf_in - sc->sc_rbuf_out) - 1) 236 /* increment ringbuffer pointer */ 237 #define IMXUART_RBUF_INC(sc,v,i) (((v) + (i))&((sc->sc_rbuf_size)-1)) 238 u_int sc_r_lowat; 239 u_int sc_r_hiwat; 240 241 /* output chunk */ 242 u_char *sc_tba; 243 u_int sc_tbc; 244 u_int sc_heldtbc; 245 /* pending parameter changes */ 246 u_char sc_pending; 247 #define IMXUART_PEND_PARAM __BIT(0) 248 #define IMXUART_PEND_SPEED __BIT(1) 249 250 251 struct callout sc_diag_callout; 252 kmutex_t sc_lock; 253 void *sc_ih; /* interrupt handler */ 254 void *sc_si; /* soft interrupt */ 255 struct tty *sc_tty; 256 257 /* power management hooks */ 258 int (*enable)(struct imxuart_softc *); 259 void (*disable)(struct imxuart_softc *); 260 261 struct { 262 ulong err; 263 ulong brk; 264 ulong prerr; 265 ulong frmerr; 266 ulong ovrrun; 267 } sc_errors; 268 269 struct imxuart_baudrate_ratio { 270 uint16_t numerator; /* UBIR */ 271 uint16_t modulator; /* UBMR */ 272 } sc_ratio; 273 274 } imxuart_softc_t; 275 276 277 int imxuspeed(long, struct imxuart_baudrate_ratio *); 278 int imxuparam(struct tty *, struct termios *); 279 void imxustart(struct tty *); 280 int imxuhwiflow(struct tty *, int); 281 282 void imxuart_shutdown(struct imxuart_softc *); 283 void imxuart_loadchannelregs(struct imxuart_softc *); 284 void imxuart_hwiflow(struct imxuart_softc *); 285 void imxuart_break(struct imxuart_softc *, bool); 286 void imxuart_modem(struct imxuart_softc *, int); 287 void tiocm_to_imxu(struct imxuart_softc *, u_long, int); 288 int imxuart_to_tiocm(struct imxuart_softc *); 289 void imxuart_iflush(struct imxuart_softc *); 290 int imxuintr(void *); 291 292 int imxuart_common_getc(dev_t, struct imxuart_regs *); 293 void imxuart_common_putc(dev_t, struct imxuart_regs *, int); 294 295 296 int imxuart_init(struct imxuart_regs *, int, tcflag_t); 297 298 int imxucngetc(dev_t); 299 void imxucnputc(dev_t, int); 300 void imxucnpollc(dev_t, int); 301 302 static void imxuintr_read(struct imxuart_softc *); 303 static void imxuintr_send(struct imxuart_softc *); 304 305 static void imxuart_enable_debugport(struct imxuart_softc *); 306 static void imxuart_disable_all_interrupts(struct imxuart_softc *); 307 static void imxuart_control_rxint(struct imxuart_softc *, bool); 308 static void imxuart_control_txint(struct imxuart_softc *, bool); 309 static u_int imxuart_txfifo_space(struct imxuart_softc *sc); 310 311 static uint32_t cflag_to_ucr2(tcflag_t, uint32_t); 312 313 CFATTACH_DECL_NEW(imxuart, sizeof(struct imxuart_softc), 314 imxuart_match, imxuart_attach, NULL, NULL); 315 316 317 #define integrate static inline 318 void imxusoft(void *); 319 integrate void imxuart_rxsoft(struct imxuart_softc *, struct tty *); 320 integrate void imxuart_txsoft(struct imxuart_softc *, struct tty *); 321 integrate void imxuart_stsoft(struct imxuart_softc *, struct tty *); 322 integrate void imxuart_schedrx(struct imxuart_softc *); 323 void imxudiag(void *); 324 static void imxuart_load_speed(struct imxuart_softc *); 325 static void imxuart_load_params(struct imxuart_softc *); 326 integrate void imxuart_load_pendings(struct imxuart_softc *); 327 328 329 extern struct cfdriver imxuart_cd; 330 331 dev_type_open(imxuopen); 332 dev_type_close(imxuclose); 333 dev_type_read(imxuread); 334 dev_type_write(imxuwrite); 335 dev_type_ioctl(imxuioctl); 336 dev_type_stop(imxustop); 337 dev_type_tty(imxutty); 338 dev_type_poll(imxupoll); 339 340 const struct cdevsw imxcom_cdevsw = { 341 .d_open = imxuopen, 342 .d_close = imxuclose, 343 .d_read = imxuread, 344 .d_write = imxuwrite, 345 .d_ioctl = imxuioctl, 346 .d_stop = imxustop, 347 .d_tty = imxutty, 348 .d_poll = imxupoll, 349 .d_mmap = nommap, 350 .d_kqfilter = ttykqfilter, 351 .d_discard = nodiscard, 352 .d_flag = D_TTY 353 }; 354 355 /* 356 * Make this an option variable one can patch. 357 * But be warned: this must be a power of 2! 358 */ 359 u_int imxuart_rbuf_size = IMXUART_RING_SIZE; 360 361 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 362 u_int imxuart_rbuf_hiwat = (IMXUART_RING_SIZE * 1) / 4; 363 u_int imxuart_rbuf_lowat = (IMXUART_RING_SIZE * 3) / 4; 364 365 static struct imxuart_regs imxuconsregs; 366 static int imxuconsattached; 367 static int imxuconsrate; 368 static tcflag_t imxuconscflag; 369 static struct cnm_state imxuart_cnm_state; 370 371 u_int imxuart_freq = IMXUART_FREQ; 372 u_int imxuart_freqdiv = IMXUART_FREQDIV; 373 374 #ifdef KGDB 375 #include <sys/kgdb.h> 376 377 static struct imxuart_regs imxu_kgdb_regs; 378 static int imxu_kgdb_attached; 379 380 int imxuart_kgdb_getc(void *); 381 void imxuart_kgdb_putc(void *, int); 382 #endif /* KGDB */ 383 384 #define IMXUART_UNIT_MASK 0x7ffff 385 #define IMXUART_DIALOUT_MASK 0x80000 386 387 #define IMXUART_UNIT(x) (minor(x) & IMXUART_UNIT_MASK) 388 #define IMXUART_DIALOUT(x) (minor(x) & IMXUART_DIALOUT_MASK) 389 390 #define IMXUART_ISALIVE(sc) ((sc)->enabled != 0 && \ 391 device_is_active((sc)->sc_dev)) 392 393 #define BR BUS_SPACE_BARRIER_READ 394 #define BW BUS_SPACE_BARRIER_WRITE 395 #define IMXUART_BARRIER(r, f) \ 396 bus_space_barrier((r)->ur_iot, (r)->ur_ioh, 0, IMX_UART_SIZE, (f)) 397 398 399 void 400 imxuart_attach_common(device_t parent, device_t self, 401 bus_space_tag_t iot, paddr_t iobase, size_t size, int intr, int flags) 402 { 403 imxuart_softc_t *sc = device_private(self); 404 struct imxuart_regs *regsp = &sc->sc_regs; 405 struct tty *tp; 406 bus_space_handle_t ioh; 407 408 aprint_naive("\n"); 409 aprint_normal("\n"); 410 411 sc->sc_dev = self; 412 413 if (size <= 0) 414 size = IMX_UART_SIZE; 415 416 sc->sc_intr = intr; 417 regsp->ur_iot = iot; 418 regsp->ur_iobase = iobase; 419 420 if (bus_space_map(iot, regsp->ur_iobase, size, 0, &ioh)) { 421 return; 422 } 423 regsp->ur_ioh = ioh; 424 425 callout_init(&sc->sc_diag_callout, 0); 426 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 427 428 bus_space_read_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 4); 429 sc->sc_ucr2_d = sc->sc_ucr2; 430 431 /* Disable interrupts before configuring the device. */ 432 imxuart_disable_all_interrupts(sc); 433 434 if (regsp->ur_iobase == imxuconsregs.ur_iobase) { 435 imxuconsattached = 1; 436 437 /* Make sure the console is always "hardwired". */ 438 #if 0 439 delay(10000); /* wait for output to finish */ 440 #endif 441 SET(sc->sc_hwflags, IMXUART_HW_CONSOLE); 442 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 443 } 444 445 446 tp = tty_alloc(); 447 tp->t_oproc = imxustart; 448 tp->t_param = imxuparam; 449 tp->t_hwiflow = imxuhwiflow; 450 451 sc->sc_tty = tp; 452 sc->sc_rbuf = malloc(sizeof (*sc->sc_rbuf) * imxuart_rbuf_size, 453 M_DEVBUF, M_NOWAIT); 454 sc->sc_rbuf_size = imxuart_rbuf_size; 455 sc->sc_rbuf_in = sc->sc_rbuf_out = 0; 456 if (sc->sc_rbuf == NULL) { 457 aprint_error_dev(sc->sc_dev, 458 "unable to allocate ring buffer\n"); 459 return; 460 } 461 462 sc->sc_txfifo_len = 32; 463 sc->sc_txfifo_thresh = 16; /* when USR1.TRDY, fifo has space 464 * for this many characters */ 465 466 tty_attach(tp); 467 468 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 469 int maj; 470 471 /* locate the major number */ 472 maj = cdevsw_lookup_major(&imxcom_cdevsw); 473 474 if (maj != NODEVMAJOR) { 475 tp->t_dev = cn_tab->cn_dev = makedev(maj, 476 device_unit(sc->sc_dev)); 477 478 aprint_normal_dev(sc->sc_dev, "console\n"); 479 } 480 } 481 482 sc->sc_ih = intr_establish(sc->sc_intr, IPL_SERIAL, IST_LEVEL, 483 imxuintr, sc); 484 if (sc->sc_ih == NULL) 485 aprint_error_dev(sc->sc_dev, "intr_establish failed\n"); 486 487 #ifdef KGDB 488 /* 489 * Allow kgdb to "take over" this port. If this is 490 * not the console and is the kgdb device, it has 491 * exclusive use. If it's the console _and_ the 492 * kgdb device, it doesn't. 493 */ 494 if (regsp->ur_iobase == imxu_kgdb_regs.ur_iobase) { 495 if (!ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 496 imxu_kgdb_attached = 1; 497 498 SET(sc->sc_hwflags, IMXUART_HW_KGDB); 499 } 500 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 501 } 502 #endif 503 504 sc->sc_si = softint_establish(SOFTINT_SERIAL, imxusoft, sc); 505 506 #ifdef RND_COM 507 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 508 RND_TYPE_TTY, 0); 509 #endif 510 511 /* if there are no enable/disable functions, assume the device 512 is always enabled */ 513 if (!sc->enable) 514 sc->enabled = 1; 515 516 imxuart_enable_debugport(sc); 517 518 SET(sc->sc_hwflags, IMXUART_HW_DEV_OK); 519 520 //shutdownhook_establish(imxuart_shutdownhook, sc); 521 522 523 #if 0 524 { 525 uint32_t reg; 526 reg = bus_space_read_4(iot, ioh, IMX_UCR1); 527 reg |= IMX_UCR1_TXDMAEN | IMX_UCR1_RXDMAEN; 528 bus_space_write_4(iot, ioh, IMX_UCR1, reg); 529 } 530 #endif 531 } 532 533 /* 534 * baudrate = RefFreq / (16 * (UMBR + 1)/(UBIR + 1)) 535 * 536 * (UBIR + 1) / (UBMR + 1) = (16 * BaurdRate) / RefFreq 537 */ 538 539 static long 540 gcd(long m, long n) 541 { 542 543 if (m < n) 544 return gcd(n, m); 545 546 if (n <= 0) 547 return m; 548 return gcd(n, m % n); 549 } 550 551 552 int 553 imxuspeed(long speed, struct imxuart_baudrate_ratio *ratio) 554 { 555 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 556 long b = 16 * speed; 557 long f = imxuart_freq / imxuart_freqdiv; 558 long d; 559 int err = 0; 560 561 /* reduce b/f */ 562 while ((f > (1<<16) || b > (1<<16)) && (d = gcd(f, b)) > 1) { 563 f /= d; 564 b /= d; 565 } 566 567 568 while (f > (1<<16) || b > (1<<16)) { 569 f /= 2; 570 b /= 2; 571 } 572 if (f <= 0 || b <= 0) 573 return -1; 574 575 #ifdef DIAGNOSTIC 576 err = divrnd(((uint64_t)imxuart_freq) * 1000 / imxuart_freqdiv, 577 (uint64_t)speed * 16 * f / b) - 1000; 578 if (err < 0) 579 err = -err; 580 #endif 581 582 ratio->numerator = b-1; 583 ratio->modulator = f-1; 584 585 if (err > IMXUART_TOLERANCE) 586 return -1; 587 588 return 0; 589 #undef divrnd 590 } 591 592 #ifdef IMXUART_DEBUG 593 int imxuart_debug = 0; 594 595 void imxustatus(struct imxuart_softc *, const char *); 596 void 597 imxustatus(struct imxuart_softc *sc, const char *str) 598 { 599 struct tty *tp = sc->sc_tty; 600 601 aprint_normal_dev(sc->sc_dev, 602 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 603 str, 604 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 605 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 606 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 607 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 608 sc->sc_tx_stopped ? '+' : '-'); 609 610 aprint_normal_dev(sc->sc_dev, 611 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 612 str, 613 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 614 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 615 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 616 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 617 sc->sc_rx_flags); 618 } 619 #endif 620 621 #if 0 622 int 623 imxuart_detach(device_t self, int flags) 624 { 625 struct imxuart_softc *sc = device_private(self); 626 int maj, mn; 627 628 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) 629 return EBUSY; 630 631 /* locate the major number */ 632 maj = cdevsw_lookup_major(&imxcom_cdevsw); 633 634 /* Nuke the vnodes for any open instances. */ 635 mn = device_unit(self); 636 vdevgone(maj, mn, mn, VCHR); 637 638 mn |= IMXUART_DIALOUT_MASK; 639 vdevgone(maj, mn, mn, VCHR); 640 641 if (sc->sc_rbuf == NULL) { 642 /* 643 * Ring buffer allocation failed in the imxuart_attach_subr, 644 * only the tty is allocated, and nothing else. 645 */ 646 tty_free(sc->sc_tty); 647 return 0; 648 } 649 650 /* Free the receive buffer. */ 651 free(sc->sc_rbuf, M_DEVBUF); 652 653 /* Detach and free the tty. */ 654 tty_detach(sc->sc_tty); 655 tty_free(sc->sc_tty); 656 657 /* Unhook the soft interrupt handler. */ 658 softint_disestablish(sc->sc_si); 659 660 #ifdef RND_COM 661 /* Unhook the entropy source. */ 662 rnd_detach_source(&sc->rnd_source); 663 #endif 664 callout_destroy(&sc->sc_diag_callout); 665 666 /* Destroy the lock. */ 667 mutex_destroy(&sc->sc_lock); 668 669 return (0); 670 } 671 #endif 672 673 #ifdef notyet 674 int 675 imxuart_activate(device_t self, enum devact act) 676 { 677 struct imxuart_softc *sc = device_private(self); 678 int rv = 0; 679 680 switch (act) { 681 case DVACT_ACTIVATE: 682 rv = EOPNOTSUPP; 683 break; 684 685 case DVACT_DEACTIVATE: 686 if (sc->sc_hwflags & (IMXUART_HW_CONSOLE|IMXUART_HW_KGDB)) { 687 rv = EBUSY; 688 break; 689 } 690 691 if (sc->disable != NULL && sc->enabled != 0) { 692 (*sc->disable)(sc); 693 sc->enabled = 0; 694 } 695 break; 696 } 697 698 return (rv); 699 } 700 #endif 701 702 void 703 imxuart_shutdown(struct imxuart_softc *sc) 704 { 705 struct tty *tp = sc->sc_tty; 706 707 mutex_spin_enter(&sc->sc_lock); 708 709 /* If we were asserting flow control, then deassert it. */ 710 SET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED); 711 imxuart_hwiflow(sc); 712 713 /* Clear any break condition set with TIOCSBRK. */ 714 imxuart_break(sc, false); 715 716 /* 717 * Hang up if necessary. Wait a bit, so the other side has time to 718 * notice even if we immediately open the port again. 719 * Avoid tsleeping above splhigh(). 720 */ 721 if (ISSET(tp->t_cflag, HUPCL)) { 722 imxuart_modem(sc, 0); 723 mutex_spin_exit(&sc->sc_lock); 724 /* XXX will only timeout */ 725 (void) kpause(ttclos, false, hz, NULL); 726 mutex_spin_enter(&sc->sc_lock); 727 } 728 729 /* Turn off interrupts. */ 730 imxuart_disable_all_interrupts(sc); 731 /* re-enable recv interrupt for console or kgdb port */ 732 imxuart_enable_debugport(sc); 733 734 mutex_spin_exit(&sc->sc_lock); 735 736 #ifdef notyet 737 if (sc->disable) { 738 #ifdef DIAGNOSTIC 739 if (!sc->enabled) 740 panic("imxuart_shutdown: not enabled?"); 741 #endif 742 (*sc->disable)(sc); 743 sc->enabled = 0; 744 } 745 #endif 746 } 747 748 int 749 imxuopen(dev_t dev, int flag, int mode, struct lwp *l) 750 { 751 struct imxuart_softc *sc; 752 struct tty *tp; 753 int s; 754 int error; 755 756 sc = device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 757 if (sc == NULL || !ISSET(sc->sc_hwflags, IMXUART_HW_DEV_OK) || 758 sc->sc_rbuf == NULL) 759 return (ENXIO); 760 761 if (!device_is_active(sc->sc_dev)) 762 return (ENXIO); 763 764 #ifdef KGDB 765 /* 766 * If this is the kgdb port, no other use is permitted. 767 */ 768 if (ISSET(sc->sc_hwflags, IMXUART_HW_KGDB)) 769 return (EBUSY); 770 #endif 771 772 tp = sc->sc_tty; 773 774 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 775 return (EBUSY); 776 777 s = spltty(); 778 779 /* 780 * Do the following iff this is a first open. 781 */ 782 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 783 struct termios t; 784 785 tp->t_dev = dev; 786 787 788 #ifdef notyet 789 if (sc->enable) { 790 if ((*sc->enable)(sc)) { 791 splx(s); 792 aprint_error_dev(sc->sc_dev, 793 "device enable failed\n"); 794 return (EIO); 795 } 796 sc->enabled = 1; 797 } 798 #endif 799 800 mutex_spin_enter(&sc->sc_lock); 801 802 imxuart_disable_all_interrupts(sc); 803 804 /* Fetch the current modem control status, needed later. */ 805 806 #ifdef IMXUART_PPS 807 /* Clear PPS capture state on first open. */ 808 mutex_spin_enter(&timecounter_lock); 809 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 810 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 811 pps_init(&sc->sc_pps_state); 812 mutex_spin_exit(&timecounter_lock); 813 #endif 814 815 mutex_spin_exit(&sc->sc_lock); 816 817 /* 818 * Initialize the termios status to the defaults. Add in the 819 * sticky bits from TIOCSFLAGS. 820 */ 821 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 822 t.c_ospeed = imxuconsrate; 823 t.c_cflag = imxuconscflag; 824 } else { 825 t.c_ospeed = TTYDEF_SPEED; 826 t.c_cflag = TTYDEF_CFLAG; 827 } 828 t.c_ispeed = t.c_ospeed; 829 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 830 SET(t.c_cflag, CLOCAL); 831 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 832 SET(t.c_cflag, CRTSCTS); 833 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 834 SET(t.c_cflag, MDMBUF); 835 /* Make sure imxuparam() will do something. */ 836 tp->t_ospeed = 0; 837 (void) imxuparam(tp, &t); 838 tp->t_iflag = TTYDEF_IFLAG; 839 tp->t_oflag = TTYDEF_OFLAG; 840 tp->t_lflag = TTYDEF_LFLAG; 841 ttychars(tp); 842 ttsetwater(tp); 843 844 mutex_spin_enter(&sc->sc_lock); 845 846 /* 847 * Turn on DTR. We must always do this, even if carrier is not 848 * present, because otherwise we'd have to use TIOCSDTR 849 * immediately after setting CLOCAL, which applications do not 850 * expect. We always assert DTR while the device is open 851 * unless explicitly requested to deassert it. 852 */ 853 imxuart_modem(sc, 1); 854 855 /* Clear the input ring, and unblock. */ 856 sc->sc_rbuf_in = sc->sc_rbuf_out = 0; 857 imxuart_iflush(sc); 858 CLR(sc->sc_rx_flags, IMXUART_RX_ANY_BLOCK); 859 imxuart_hwiflow(sc); 860 861 /* Turn on interrupts. */ 862 imxuart_control_rxint(sc, true); 863 864 #ifdef IMXUART_DEBUG 865 if (imxuart_debug) 866 imxustatus(sc, "imxuopen "); 867 #endif 868 869 mutex_spin_exit(&sc->sc_lock); 870 } 871 872 splx(s); 873 874 #if 0 875 error = ttyopen(tp, IMXUART_DIALOUT(dev), ISSET(flag, O_NONBLOCK)); 876 #else 877 error = ttyopen(tp, 1, ISSET(flag, O_NONBLOCK)); 878 #endif 879 if (error) 880 goto bad; 881 882 error = (*tp->t_linesw->l_open)(dev, tp); 883 if (error) 884 goto bad; 885 886 return (0); 887 888 bad: 889 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 890 /* 891 * We failed to open the device, and nobody else had it opened. 892 * Clean up the state as appropriate. 893 */ 894 imxuart_shutdown(sc); 895 } 896 897 return (error); 898 } 899 900 int 901 imxuclose(dev_t dev, int flag, int mode, struct lwp *l) 902 { 903 struct imxuart_softc *sc = 904 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 905 struct tty *tp = sc->sc_tty; 906 907 /* XXX This is for cons.c. */ 908 if (!ISSET(tp->t_state, TS_ISOPEN)) 909 return (0); 910 911 (*tp->t_linesw->l_close)(tp, flag); 912 ttyclose(tp); 913 914 if (IMXUART_ISALIVE(sc) == 0) 915 return (0); 916 917 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 918 /* 919 * Although we got a last close, the device may still be in 920 * use; e.g. if this was the dialout node, and there are still 921 * processes waiting for carrier on the non-dialout node. 922 */ 923 imxuart_shutdown(sc); 924 } 925 926 return (0); 927 } 928 929 int 930 imxuread(dev_t dev, struct uio *uio, int flag) 931 { 932 struct imxuart_softc *sc = 933 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 934 struct tty *tp = sc->sc_tty; 935 936 if (IMXUART_ISALIVE(sc) == 0) 937 return (EIO); 938 939 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 940 } 941 942 int 943 imxuwrite(dev_t dev, struct uio *uio, int flag) 944 { 945 struct imxuart_softc *sc = 946 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 947 struct tty *tp = sc->sc_tty; 948 949 if (IMXUART_ISALIVE(sc) == 0) 950 return (EIO); 951 952 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 953 } 954 955 int 956 imxupoll(dev_t dev, int events, struct lwp *l) 957 { 958 struct imxuart_softc *sc = 959 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 960 struct tty *tp = sc->sc_tty; 961 962 if (IMXUART_ISALIVE(sc) == 0) 963 return (POLLHUP); 964 965 return ((*tp->t_linesw->l_poll)(tp, events, l)); 966 } 967 968 struct tty * 969 imxutty(dev_t dev) 970 { 971 struct imxuart_softc *sc = 972 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 973 struct tty *tp = sc->sc_tty; 974 975 return (tp); 976 } 977 978 int 979 imxuioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 980 { 981 struct imxuart_softc *sc; 982 struct tty *tp; 983 int error; 984 985 sc = device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 986 if (sc == NULL) 987 return ENXIO; 988 if (IMXUART_ISALIVE(sc) == 0) 989 return (EIO); 990 991 tp = sc->sc_tty; 992 993 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 994 if (error != EPASSTHROUGH) 995 return (error); 996 997 error = ttioctl(tp, cmd, data, flag, l); 998 if (error != EPASSTHROUGH) 999 return (error); 1000 1001 error = 0; 1002 switch (cmd) { 1003 case TIOCSFLAGS: 1004 error = kauth_authorize_device_tty(l->l_cred, 1005 KAUTH_DEVICE_TTY_PRIVSET, tp); 1006 break; 1007 default: 1008 /* nothing */ 1009 break; 1010 } 1011 if (error) { 1012 return error; 1013 } 1014 1015 mutex_spin_enter(&sc->sc_lock); 1016 1017 switch (cmd) { 1018 case TIOCSBRK: 1019 imxuart_break(sc, true); 1020 break; 1021 1022 case TIOCCBRK: 1023 imxuart_break(sc, false); 1024 break; 1025 1026 case TIOCSDTR: 1027 imxuart_modem(sc, 1); 1028 break; 1029 1030 case TIOCCDTR: 1031 imxuart_modem(sc, 0); 1032 break; 1033 1034 case TIOCGFLAGS: 1035 *(int *)data = sc->sc_swflags; 1036 break; 1037 1038 case TIOCSFLAGS: 1039 sc->sc_swflags = *(int *)data; 1040 break; 1041 1042 case TIOCMSET: 1043 case TIOCMBIS: 1044 case TIOCMBIC: 1045 tiocm_to_imxu(sc, cmd, *(int *)data); 1046 break; 1047 1048 case TIOCMGET: 1049 *(int *)data = imxuart_to_tiocm(sc); 1050 break; 1051 1052 #ifdef notyet 1053 case PPS_IOC_CREATE: 1054 case PPS_IOC_DESTROY: 1055 case PPS_IOC_GETPARAMS: 1056 case PPS_IOC_SETPARAMS: 1057 case PPS_IOC_GETCAP: 1058 case PPS_IOC_FETCH: 1059 #ifdef PPS_SYNC 1060 case PPS_IOC_KCBIND: 1061 #endif 1062 mutex_spin_enter(&timecounter_lock); 1063 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1064 mutex_spin_exit(&timecounter_lock); 1065 break; 1066 1067 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1068 mutex_spin_enter(&timecounter_lock); 1069 #ifndef PPS_TRAILING_EDGE 1070 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1071 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1072 #else 1073 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1074 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1075 #endif 1076 mutex_spin_exit(&timecounter_lock); 1077 break; 1078 #endif 1079 1080 default: 1081 error = EPASSTHROUGH; 1082 break; 1083 } 1084 1085 mutex_spin_exit(&sc->sc_lock); 1086 1087 #ifdef IMXUART_DEBUG 1088 if (imxuart_debug) 1089 imxustatus(sc, "imxuioctl "); 1090 #endif 1091 1092 return (error); 1093 } 1094 1095 integrate void 1096 imxuart_schedrx(struct imxuart_softc *sc) 1097 { 1098 sc->sc_rx_ready = 1; 1099 1100 /* Wake up the poller. */ 1101 softint_schedule(sc->sc_si); 1102 } 1103 1104 void 1105 imxuart_break(struct imxuart_softc *sc, bool onoff) 1106 { 1107 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1108 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1109 1110 if (onoff) 1111 SET(sc->sc_ucr1, IMX_UCR1_SNDBRK); 1112 else 1113 CLR(sc->sc_ucr1, IMX_UCR1_SNDBRK); 1114 1115 bus_space_write_4(iot, ioh, IMX_UCR1, sc->sc_ucr1); 1116 } 1117 1118 void 1119 imxuart_modem(struct imxuart_softc *sc, int onoff) 1120 { 1121 #ifdef notyet 1122 if (sc->sc_mcr_dtr == 0) 1123 return; 1124 1125 if (onoff) 1126 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1127 else 1128 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1129 1130 if (!sc->sc_heldchange) { 1131 if (sc->sc_tx_busy) { 1132 sc->sc_heldtbc = sc->sc_tbc; 1133 sc->sc_tbc = 0; 1134 sc->sc_heldchange = 1; 1135 } else 1136 imxuart_loadchannelregs(sc); 1137 } 1138 #endif 1139 } 1140 1141 /* 1142 * RTS output is controlled by UCR2.CTS bit. 1143 * DTR output is controlled by UCR3.DSR bit. 1144 * (i.MX reference manual uses names in DCE mode) 1145 * 1146 * note: if UCR2.CTSC == 1 for automatic HW flow control, UCR2.CTS is ignored. 1147 */ 1148 void 1149 tiocm_to_imxu(struct imxuart_softc *sc, u_long how, int ttybits) 1150 { 1151 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1152 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1153 1154 uint32_t ucr2 = sc->sc_ucr2_d; 1155 uint32_t ucr3 = sc->sc_ucr3; 1156 1157 uint32_t ucr2_mask = 0; 1158 uint32_t ucr3_mask = 0; 1159 1160 1161 if (ISSET(ttybits, TIOCM_DTR)) 1162 ucr3_mask = IMX_UCR3_DSR; 1163 if (ISSET(ttybits, TIOCM_RTS)) 1164 ucr2_mask = IMX_UCR2_CTS; 1165 1166 switch (how) { 1167 case TIOCMBIC: 1168 CLR(ucr2, ucr2_mask); 1169 CLR(ucr3, ucr3_mask); 1170 break; 1171 1172 case TIOCMBIS: 1173 SET(ucr2, ucr2_mask); 1174 SET(ucr3, ucr3_mask); 1175 break; 1176 1177 case TIOCMSET: 1178 CLR(ucr2, ucr2_mask); 1179 CLR(ucr3, ucr3_mask); 1180 SET(ucr2, ucr2_mask); 1181 SET(ucr3, ucr3_mask); 1182 break; 1183 } 1184 1185 if (ucr3 != sc->sc_ucr3) { 1186 bus_space_write_4(iot, ioh, IMX_UCR3, ucr3); 1187 sc->sc_ucr3 = ucr3; 1188 } 1189 1190 if (ucr2 == sc->sc_ucr2_d) 1191 return; 1192 1193 sc->sc_ucr2_d = ucr2; 1194 /* update CTS bit only */ 1195 ucr2 = (sc->sc_ucr2 & ~IMX_UCR2_CTS) | 1196 (ucr2 & IMX_UCR2_CTS); 1197 1198 bus_space_write_4(iot, ioh, IMX_UCR2, ucr2); 1199 sc->sc_ucr2 = ucr2; 1200 } 1201 1202 int 1203 imxuart_to_tiocm(struct imxuart_softc *sc) 1204 { 1205 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1206 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1207 int ttybits = 0; 1208 uint32_t usr[2]; 1209 1210 if (ISSET(sc->sc_ucr3, IMX_UCR3_DSR)) 1211 SET(ttybits, TIOCM_DTR); 1212 if (ISSET(sc->sc_ucr2, IMX_UCR2_CTS)) 1213 SET(ttybits, TIOCM_RTS); 1214 1215 bus_space_read_region_4(iot, ioh, IMX_USR1, usr, 2); 1216 1217 if (ISSET(usr[0], IMX_USR1_RTSS)) 1218 SET(ttybits, TIOCM_CTS); 1219 1220 if (ISSET(usr[1], IMX_USR2_DCDIN)) 1221 SET(ttybits, TIOCM_CD); 1222 1223 #if 0 1224 /* XXXbsh: I couldn't find the way to read ipp_uart_dsr_dte_i signal, 1225 although there are bits in UART registers to detect delta of DSR. 1226 */ 1227 if (ISSET(imxubits, MSR_DSR)) 1228 SET(ttybits, TIOCM_DSR); 1229 #endif 1230 1231 if (ISSET(usr[1], IMX_USR2_RIIN)) 1232 SET(ttybits, TIOCM_RI); 1233 1234 1235 #ifdef notyet 1236 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1237 SET(ttybits, TIOCM_LE); 1238 #endif 1239 1240 return (ttybits); 1241 } 1242 1243 static uint32_t 1244 cflag_to_ucr2(tcflag_t cflag, uint32_t oldval) 1245 { 1246 uint32_t val = oldval; 1247 1248 CLR(val,IMX_UCR2_WS|IMX_UCR2_PREN|IMX_UCR2_PROE|IMX_UCR2_STPB); 1249 1250 switch (cflag & CSIZE) { 1251 case CS5: 1252 case CS6: 1253 /* not suppreted. use 7-bits */ 1254 case CS7: 1255 break; 1256 case CS8: 1257 SET(val, IMX_UCR2_WS); 1258 break; 1259 } 1260 1261 1262 if (ISSET(cflag, PARENB)) { 1263 SET(val, IMX_UCR2_PREN); 1264 1265 /* odd parity */ 1266 if (!ISSET(cflag, PARODD)) 1267 SET(val, IMX_UCR2_PROE); 1268 } 1269 1270 if (ISSET(cflag, CSTOPB)) 1271 SET(val, IMX_UCR2_STPB); 1272 1273 val |= IMX_UCR2_TXEN| IMX_UCR2_RXEN|IMX_UCR2_SRST; 1274 1275 return val; 1276 } 1277 1278 int 1279 imxuparam(struct tty *tp, struct termios *t) 1280 { 1281 struct imxuart_softc *sc = 1282 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1283 struct imxuart_baudrate_ratio ratio; 1284 uint32_t ucr2; 1285 bool change_speed = tp->t_ospeed != t->c_ospeed; 1286 1287 if (IMXUART_ISALIVE(sc) == 0) 1288 return (EIO); 1289 1290 /* Check requested parameters. */ 1291 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1292 return (EINVAL); 1293 1294 /* 1295 * For the console, always force CLOCAL and !HUPCL, so that the port 1296 * is always active. 1297 */ 1298 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1299 ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 1300 SET(t->c_cflag, CLOCAL); 1301 CLR(t->c_cflag, HUPCL); 1302 } 1303 1304 /* 1305 * If there were no changes, don't do anything. This avoids dropping 1306 * input and improves performance when all we did was frob things like 1307 * VMIN and VTIME. 1308 */ 1309 if ( !change_speed && tp->t_cflag == t->c_cflag) 1310 return (0); 1311 1312 if (change_speed) { 1313 /* calculate baudrate modulator value */ 1314 if (imxuspeed(t->c_ospeed, &ratio) < 0) 1315 return (EINVAL); 1316 sc->sc_ratio = ratio; 1317 } 1318 1319 ucr2 = cflag_to_ucr2(t->c_cflag, sc->sc_ucr2_d); 1320 1321 mutex_spin_enter(&sc->sc_lock); 1322 1323 #if 0 /* flow control stuff. not yet */ 1324 /* 1325 * If we're not in a mode that assumes a connection is present, then 1326 * ignore carrier changes. 1327 */ 1328 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1329 sc->sc_msr_dcd = 0; 1330 else 1331 sc->sc_msr_dcd = MSR_DCD; 1332 /* 1333 * Set the flow control pins depending on the current flow control 1334 * mode. 1335 */ 1336 if (ISSET(t->c_cflag, CRTSCTS)) { 1337 sc->sc_mcr_dtr = MCR_DTR; 1338 sc->sc_mcr_rts = MCR_RTS; 1339 sc->sc_msr_cts = MSR_CTS; 1340 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1341 } else if (ISSET(t->c_cflag, MDMBUF)) { 1342 /* 1343 * For DTR/DCD flow control, make sure we don't toggle DTR for 1344 * carrier detection. 1345 */ 1346 sc->sc_mcr_dtr = 0; 1347 sc->sc_mcr_rts = MCR_DTR; 1348 sc->sc_msr_cts = MSR_DCD; 1349 sc->sc_efr = 0; 1350 } else { 1351 /* 1352 * If no flow control, then always set RTS. This will make 1353 * the other side happy if it mistakenly thinks we're doing 1354 * RTS/CTS flow control. 1355 */ 1356 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1357 sc->sc_mcr_rts = 0; 1358 sc->sc_msr_cts = 0; 1359 sc->sc_efr = 0; 1360 if (ISSET(sc->sc_mcr, MCR_DTR)) 1361 SET(sc->sc_mcr, MCR_RTS); 1362 else 1363 CLR(sc->sc_mcr, MCR_RTS); 1364 } 1365 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1366 #endif 1367 1368 /* And copy to tty. */ 1369 tp->t_ispeed = t->c_ospeed; 1370 tp->t_ospeed = t->c_ospeed; 1371 tp->t_cflag = t->c_cflag; 1372 1373 if (!change_speed && ucr2 == sc->sc_ucr2_d) { 1374 /* noop */ 1375 } 1376 else if (!sc->sc_pending && !sc->sc_tx_busy) { 1377 if (ucr2 != sc->sc_ucr2_d) { 1378 sc->sc_ucr2_d = ucr2; 1379 imxuart_load_params(sc); 1380 } 1381 if (change_speed) 1382 imxuart_load_speed(sc); 1383 } 1384 else { 1385 if (!sc->sc_pending) { 1386 sc->sc_heldtbc = sc->sc_tbc; 1387 sc->sc_tbc = 0; 1388 } 1389 sc->sc_pending |= 1390 (ucr2 == sc->sc_ucr2_d ? 0 : IMXUART_PEND_PARAM) | 1391 (change_speed ? 0 : IMXUART_PEND_SPEED); 1392 sc->sc_ucr2_d = ucr2; 1393 } 1394 1395 if (!ISSET(t->c_cflag, CHWFLOW)) { 1396 /* Disable the high water mark. */ 1397 sc->sc_r_hiwat = 0; 1398 sc->sc_r_lowat = 0; 1399 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED)) { 1400 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED); 1401 imxuart_schedrx(sc); 1402 } 1403 if (ISSET(sc->sc_rx_flags, 1404 IMXUART_RX_TTY_BLOCKED|IMXUART_RX_IBUF_BLOCKED)) { 1405 CLR(sc->sc_rx_flags, 1406 IMXUART_RX_TTY_BLOCKED|IMXUART_RX_IBUF_BLOCKED); 1407 imxuart_hwiflow(sc); 1408 } 1409 } else { 1410 sc->sc_r_hiwat = imxuart_rbuf_hiwat; 1411 sc->sc_r_lowat = imxuart_rbuf_lowat; 1412 } 1413 1414 mutex_spin_exit(&sc->sc_lock); 1415 1416 #if 0 1417 /* 1418 * Update the tty layer's idea of the carrier bit, in case we changed 1419 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1420 * explicit request. 1421 */ 1422 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1423 #else 1424 /* XXX: always report that we have DCD */ 1425 (void) (*tp->t_linesw->l_modem)(tp, 1); 1426 #endif 1427 1428 #ifdef IMXUART_DEBUG 1429 if (imxuart_debug) 1430 imxustatus(sc, "imxuparam "); 1431 #endif 1432 1433 if (!ISSET(t->c_cflag, CHWFLOW)) { 1434 if (sc->sc_tx_stopped) { 1435 sc->sc_tx_stopped = 0; 1436 imxustart(tp); 1437 } 1438 } 1439 1440 return (0); 1441 } 1442 1443 void 1444 imxuart_iflush(struct imxuart_softc *sc) 1445 { 1446 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1447 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1448 #ifdef DIAGNOSTIC 1449 uint32_t reg = 0xffff; 1450 #endif 1451 int timo; 1452 1453 timo = 50000; 1454 /* flush any pending I/O */ 1455 while (ISSET(bus_space_read_4(iot, ioh, IMX_USR2), IMX_USR2_RDR) 1456 && --timo) 1457 #ifdef DIAGNOSTIC 1458 reg = 1459 #else 1460 (void) 1461 #endif 1462 bus_space_read_4(iot, ioh, IMX_URXD); 1463 #ifdef DIAGNOSTIC 1464 if (!timo) 1465 aprint_error_dev(sc->sc_dev, "imxuart_iflush timeout %02x\n", reg); 1466 #endif 1467 } 1468 1469 int 1470 imxuhwiflow(struct tty *tp, int block) 1471 { 1472 struct imxuart_softc *sc = 1473 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1474 1475 if (IMXUART_ISALIVE(sc) == 0) 1476 return (0); 1477 1478 #ifdef notyet 1479 if (sc->sc_mcr_rts == 0) 1480 return (0); 1481 #endif 1482 1483 mutex_spin_enter(&sc->sc_lock); 1484 1485 if (block) { 1486 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) { 1487 SET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED); 1488 imxuart_hwiflow(sc); 1489 } 1490 } else { 1491 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED)) { 1492 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED); 1493 imxuart_schedrx(sc); 1494 } 1495 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) { 1496 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED); 1497 imxuart_hwiflow(sc); 1498 } 1499 } 1500 1501 mutex_spin_exit(&sc->sc_lock); 1502 return (1); 1503 } 1504 1505 /* 1506 * (un)block input via hw flowcontrol 1507 */ 1508 void 1509 imxuart_hwiflow(struct imxuart_softc *sc) 1510 { 1511 #ifdef notyet 1512 struct imxuart_regs *regsp= &sc->sc_regs; 1513 1514 if (sc->sc_mcr_rts == 0) 1515 return; 1516 1517 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1518 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1519 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1520 } else { 1521 SET(sc->sc_mcr, sc->sc_mcr_rts); 1522 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1523 } 1524 UR_WRITE_1(regsp, IMXUART_REG_MCR, sc->sc_mcr_active); 1525 #endif 1526 } 1527 1528 1529 void 1530 imxustart(struct tty *tp) 1531 { 1532 struct imxuart_softc *sc = 1533 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1534 int s; 1535 u_char *tba; 1536 int tbc; 1537 u_int n; 1538 u_int space; 1539 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1540 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1541 1542 if (IMXUART_ISALIVE(sc) == 0) 1543 return; 1544 1545 s = spltty(); 1546 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1547 goto out; 1548 if (sc->sc_tx_stopped) 1549 goto out; 1550 if (!ttypull(tp)) 1551 goto out; 1552 1553 /* Grab the first contiguous region of buffer space. */ 1554 tba = tp->t_outq.c_cf; 1555 tbc = ndqb(&tp->t_outq, 0); 1556 1557 mutex_spin_enter(&sc->sc_lock); 1558 1559 sc->sc_tba = tba; 1560 sc->sc_tbc = tbc; 1561 1562 SET(tp->t_state, TS_BUSY); 1563 sc->sc_tx_busy = 1; 1564 1565 space = imxuart_txfifo_space(sc); 1566 n = MIN(sc->sc_tbc, space); 1567 1568 bus_space_write_multi_1(iot, ioh, IMX_UTXD, sc->sc_tba, n); 1569 sc->sc_tbc -= n; 1570 sc->sc_tba += n; 1571 1572 /* Enable transmit completion interrupts */ 1573 imxuart_control_txint(sc, true); 1574 1575 mutex_spin_exit(&sc->sc_lock); 1576 out: 1577 splx(s); 1578 return; 1579 } 1580 1581 /* 1582 * Stop output on a line. 1583 */ 1584 void 1585 imxustop(struct tty *tp, int flag) 1586 { 1587 struct imxuart_softc *sc = 1588 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1589 1590 mutex_spin_enter(&sc->sc_lock); 1591 if (ISSET(tp->t_state, TS_BUSY)) { 1592 /* Stop transmitting at the next chunk. */ 1593 sc->sc_tbc = 0; 1594 sc->sc_heldtbc = 0; 1595 if (!ISSET(tp->t_state, TS_TTSTOP)) 1596 SET(tp->t_state, TS_FLUSH); 1597 } 1598 mutex_spin_exit(&sc->sc_lock); 1599 } 1600 1601 void 1602 imxudiag(void *arg) 1603 { 1604 #ifdef notyet 1605 struct imxuart_softc *sc = arg; 1606 int overflows, floods; 1607 1608 mutex_spin_enter(&sc->sc_lock); 1609 overflows = sc->sc_overflows; 1610 sc->sc_overflows = 0; 1611 floods = sc->sc_floods; 1612 sc->sc_floods = 0; 1613 sc->sc_errors = 0; 1614 mutex_spin_exit(&sc->sc_lock); 1615 1616 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1617 device_xname(sc->sc_dev), 1618 overflows, overflows == 1 ? "" : "s", 1619 floods, floods == 1 ? "" : "s"); 1620 #endif 1621 } 1622 1623 integrate void 1624 imxuart_rxsoft(struct imxuart_softc *sc, struct tty *tp) 1625 { 1626 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1627 u_int cc, scc, outp; 1628 uint16_t data; 1629 u_int code; 1630 1631 scc = cc = IMXUART_RBUF_AVAIL(sc); 1632 1633 #if 0 1634 if (cc == imxuart_rbuf_size-1) { 1635 sc->sc_floods++; 1636 if (sc->sc_errors++ == 0) 1637 callout_reset(&sc->sc_diag_callout, 60 * hz, 1638 imxudiag, sc); 1639 } 1640 #endif 1641 1642 /* If not yet open, drop the entire buffer content here */ 1643 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1644 sc->sc_rbuf_out = sc->sc_rbuf_in; 1645 cc = 0; 1646 } 1647 1648 outp = sc->sc_rbuf_out; 1649 1650 #define ERRBITS (IMX_URXD_PRERR|IMX_URXD_BRK|IMX_URXD_FRMERR|IMX_URXD_OVRRUN) 1651 1652 while (cc) { 1653 data = sc->sc_rbuf[outp]; 1654 code = data & IMX_URXD_RX_DATA; 1655 if (ISSET(data, ERRBITS)) { 1656 if (sc->sc_errors.err == 0) 1657 callout_reset(&sc->sc_diag_callout, 1658 60 * hz, imxudiag, sc); 1659 if (ISSET(data, IMX_URXD_OVRRUN)) 1660 sc->sc_errors.ovrrun++; 1661 if (ISSET(data, IMX_URXD_BRK)) { 1662 sc->sc_errors.brk++; 1663 SET(code, TTY_FE); 1664 } 1665 if (ISSET(data, IMX_URXD_FRMERR)) { 1666 sc->sc_errors.frmerr++; 1667 SET(code, TTY_FE); 1668 } 1669 if (ISSET(data, IMX_URXD_PRERR)) { 1670 sc->sc_errors.prerr++; 1671 SET(code, TTY_PE); 1672 } 1673 } 1674 if ((*rint)(code, tp) == -1) { 1675 /* 1676 * The line discipline's buffer is out of space. 1677 */ 1678 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) { 1679 /* 1680 * We're either not using flow control, or the 1681 * line discipline didn't tell us to block for 1682 * some reason. Either way, we have no way to 1683 * know when there's more space available, so 1684 * just drop the rest of the data. 1685 */ 1686 sc->sc_rbuf_out = sc->sc_rbuf_in; 1687 cc = 0; 1688 } else { 1689 /* 1690 * Don't schedule any more receive processing 1691 * until the line discipline tells us there's 1692 * space available (through imxuhwiflow()). 1693 * Leave the rest of the data in the input 1694 * buffer. 1695 */ 1696 SET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED); 1697 } 1698 break; 1699 } 1700 outp = IMXUART_RBUF_INC(sc, outp, 1); 1701 cc--; 1702 } 1703 1704 if (cc != scc) { 1705 sc->sc_rbuf_out = outp; 1706 mutex_spin_enter(&sc->sc_lock); 1707 1708 cc = IMXUART_RBUF_SPACE(sc); 1709 1710 /* Buffers should be ok again, release possible block. */ 1711 if (cc >= sc->sc_r_lowat) { 1712 if (ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_OVERFLOWED)) { 1713 CLR(sc->sc_rx_flags, IMXUART_RX_IBUF_OVERFLOWED); 1714 imxuart_control_rxint(sc, true); 1715 } 1716 if (ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED)) { 1717 CLR(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED); 1718 imxuart_hwiflow(sc); 1719 } 1720 } 1721 mutex_spin_exit(&sc->sc_lock); 1722 } 1723 } 1724 1725 integrate void 1726 imxuart_txsoft(struct imxuart_softc *sc, struct tty *tp) 1727 { 1728 1729 CLR(tp->t_state, TS_BUSY); 1730 if (ISSET(tp->t_state, TS_FLUSH)) 1731 CLR(tp->t_state, TS_FLUSH); 1732 else 1733 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1734 (*tp->t_linesw->l_start)(tp); 1735 } 1736 1737 integrate void 1738 imxuart_stsoft(struct imxuart_softc *sc, struct tty *tp) 1739 { 1740 #ifdef notyet 1741 u_char msr, delta; 1742 1743 mutex_spin_enter(&sc->sc_lock); 1744 msr = sc->sc_msr; 1745 delta = sc->sc_msr_delta; 1746 sc->sc_msr_delta = 0; 1747 mutex_spin_exit(&sc->sc_lock); 1748 1749 if (ISSET(delta, sc->sc_msr_dcd)) { 1750 /* 1751 * Inform the tty layer that carrier detect changed. 1752 */ 1753 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1754 } 1755 1756 if (ISSET(delta, sc->sc_msr_cts)) { 1757 /* Block or unblock output according to flow control. */ 1758 if (ISSET(msr, sc->sc_msr_cts)) { 1759 sc->sc_tx_stopped = 0; 1760 (*tp->t_linesw->l_start)(tp); 1761 } else { 1762 sc->sc_tx_stopped = 1; 1763 } 1764 } 1765 1766 #endif 1767 #ifdef IMXUART_DEBUG 1768 if (imxuart_debug) 1769 imxustatus(sc, "imxuart_stsoft"); 1770 #endif 1771 } 1772 1773 void 1774 imxusoft(void *arg) 1775 { 1776 struct imxuart_softc *sc = arg; 1777 struct tty *tp; 1778 1779 if (IMXUART_ISALIVE(sc) == 0) 1780 return; 1781 1782 tp = sc->sc_tty; 1783 1784 if (sc->sc_rx_ready) { 1785 sc->sc_rx_ready = 0; 1786 imxuart_rxsoft(sc, tp); 1787 } 1788 1789 if (sc->sc_st_check) { 1790 sc->sc_st_check = 0; 1791 imxuart_stsoft(sc, tp); 1792 } 1793 1794 if (sc->sc_tx_done) { 1795 sc->sc_tx_done = 0; 1796 imxuart_txsoft(sc, tp); 1797 } 1798 } 1799 1800 int 1801 imxuintr(void *arg) 1802 { 1803 struct imxuart_softc *sc = arg; 1804 uint32_t usr1, usr2; 1805 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1806 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1807 1808 1809 if (IMXUART_ISALIVE(sc) == 0) 1810 return (0); 1811 1812 mutex_spin_enter(&sc->sc_lock); 1813 1814 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1815 1816 1817 do { 1818 bus_space_write_4(iot, ioh, IMX_USR2, 1819 usr2 & (IMX_USR2_BRCD|IMX_USR2_ORE)); 1820 if (usr2 & IMX_USR2_BRCD) { 1821 /* Break signal detected */ 1822 int cn_trapped = 0; 1823 1824 cn_check_magic(sc->sc_tty->t_dev, 1825 CNC_BREAK, imxuart_cnm_state); 1826 if (cn_trapped) 1827 continue; 1828 #if defined(KGDB) && !defined(DDB) 1829 if (ISSET(sc->sc_hwflags, IMXUART_HW_KGDB)) { 1830 kgdb_connect(1); 1831 continue; 1832 } 1833 #endif 1834 } 1835 1836 if (usr2 & IMX_USR2_RDR) 1837 imxuintr_read(sc); 1838 1839 #ifdef IMXUART_PPS 1840 { 1841 u_char msr, delta; 1842 1843 msr = CSR_READ_1(regsp, IMXUART_REG_MSR); 1844 delta = msr ^ sc->sc_msr; 1845 sc->sc_msr = msr; 1846 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 1847 (delta & MSR_DCD)) { 1848 mutex_spin_enter(&timecounter_lock); 1849 pps_capture(&sc->sc_pps_state); 1850 pps_event(&sc->sc_pps_state, 1851 (msr & MSR_DCD) ? 1852 PPS_CAPTUREASSERT : 1853 PPS_CAPTURECLEAR); 1854 mutex_spin_exit(&timecounter_lock); 1855 } 1856 } 1857 #endif 1858 1859 #ifdef notyet 1860 /* 1861 * Process normal status changes 1862 */ 1863 if (ISSET(delta, sc->sc_msr_mask)) { 1864 SET(sc->sc_msr_delta, delta); 1865 1866 /* 1867 * Stop output immediately if we lose the output 1868 * flow control signal or carrier detect. 1869 */ 1870 if (ISSET(~msr, sc->sc_msr_mask)) { 1871 sc->sc_tbc = 0; 1872 sc->sc_heldtbc = 0; 1873 #ifdef IMXUART_DEBUG 1874 if (imxuart_debug) 1875 imxustatus(sc, "imxuintr "); 1876 #endif 1877 } 1878 1879 sc->sc_st_check = 1; 1880 } 1881 #endif 1882 1883 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1884 } while (usr2 & (IMX_USR2_RDR|IMX_USR2_BRCD)); 1885 1886 usr1 = bus_space_read_4(iot, ioh, IMX_USR1); 1887 if (usr1 & IMX_USR1_TRDY) 1888 imxuintr_send(sc); 1889 1890 mutex_spin_exit(&sc->sc_lock); 1891 1892 /* Wake up the poller. */ 1893 softint_schedule(sc->sc_si); 1894 1895 #ifdef RND_COM 1896 rnd_add_uint32(&sc->rnd_source, iir | lsr); 1897 #endif 1898 1899 return (1); 1900 } 1901 1902 1903 /* 1904 * called when there is least one character in rxfifo 1905 * 1906 */ 1907 1908 static void 1909 imxuintr_read(struct imxuart_softc *sc) 1910 { 1911 int cc; 1912 uint16_t rd; 1913 uint32_t usr2; 1914 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1915 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1916 1917 cc = IMXUART_RBUF_SPACE(sc); 1918 1919 /* clear aging timer interrupt */ 1920 bus_space_write_4(iot, ioh, IMX_USR1, IMX_USR1_AGTIM); 1921 1922 while (cc > 0) { 1923 int cn_trapped = 0; 1924 1925 1926 sc->sc_rbuf[sc->sc_rbuf_in] = rd = 1927 bus_space_read_4(iot, ioh, IMX_URXD); 1928 1929 cn_check_magic(sc->sc_tty->t_dev, 1930 rd & 0xff, imxuart_cnm_state); 1931 1932 if (!cn_trapped) { 1933 sc->sc_rbuf_in = IMXUART_RBUF_INC(sc, sc->sc_rbuf_in, 1); 1934 cc--; 1935 } 1936 1937 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1938 if (!(usr2 & IMX_USR2_RDR)) 1939 break; 1940 } 1941 1942 /* 1943 * Current string of incoming characters ended because 1944 * no more data was available or we ran out of space. 1945 * Schedule a receive event if any data was received. 1946 * If we're out of space, turn off receive interrupts. 1947 */ 1948 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED)) 1949 sc->sc_rx_ready = 1; 1950 /* 1951 * See if we are in danger of overflowing a buffer. If 1952 * so, use hardware flow control to ease the pressure. 1953 */ 1954 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED) && 1955 cc < sc->sc_r_hiwat) { 1956 sc->sc_rx_flags |= IMXUART_RX_IBUF_BLOCKED; 1957 imxuart_hwiflow(sc); 1958 } 1959 1960 /* 1961 * If we're out of space, disable receive interrupts 1962 * until the queue has drained a bit. 1963 */ 1964 if (!cc) { 1965 sc->sc_rx_flags |= IMXUART_RX_IBUF_OVERFLOWED; 1966 imxuart_control_rxint(sc, false); 1967 } 1968 } 1969 1970 1971 1972 /* 1973 * find how many chars we can put into tx-fifo 1974 */ 1975 static u_int 1976 imxuart_txfifo_space(struct imxuart_softc *sc) 1977 { 1978 uint32_t usr1, usr2; 1979 u_int cc; 1980 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1981 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1982 1983 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1984 if (usr2 & IMX_USR2_TXFE) 1985 cc = sc->sc_txfifo_len; 1986 else { 1987 usr1 = bus_space_read_4(iot, ioh, IMX_USR1); 1988 if (usr1 & IMX_USR1_TRDY) 1989 cc = sc->sc_txfifo_thresh; 1990 else 1991 cc = 0; 1992 } 1993 1994 return cc; 1995 } 1996 1997 void 1998 imxuintr_send(struct imxuart_softc *sc) 1999 { 2000 uint32_t usr2; 2001 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2002 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2003 int cc = 0; 2004 2005 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 2006 2007 if (sc->sc_pending) { 2008 if (usr2 & IMX_USR2_TXFE) { 2009 imxuart_load_pendings(sc); 2010 sc->sc_tbc = sc->sc_heldtbc; 2011 sc->sc_heldtbc = 0; 2012 } 2013 else { 2014 /* wait for TX fifo empty */ 2015 imxuart_control_txint(sc, true); 2016 return; 2017 } 2018 } 2019 2020 cc = imxuart_txfifo_space(sc); 2021 cc = MIN(cc, sc->sc_tbc); 2022 2023 if (cc > 0) { 2024 bus_space_write_multi_1(iot, ioh, IMX_UTXD, sc->sc_tba, cc); 2025 sc->sc_tbc -= cc; 2026 sc->sc_tba += cc; 2027 } 2028 2029 if (sc->sc_tbc > 0) 2030 imxuart_control_txint(sc, true); 2031 else { 2032 /* no more chars to send. 2033 we don't need tx interrupt any more. */ 2034 imxuart_control_txint(sc, false); 2035 if (sc->sc_tx_busy) { 2036 sc->sc_tx_busy = 0; 2037 sc->sc_tx_done = 1; 2038 } 2039 } 2040 } 2041 2042 static void 2043 imxuart_disable_all_interrupts(struct imxuart_softc *sc) 2044 { 2045 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2046 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2047 2048 sc->sc_ucr1 &= ~IMXUART_INTRS_UCR1; 2049 sc->sc_ucr2 &= ~IMXUART_INTRS_UCR2; 2050 sc->sc_ucr3 &= ~IMXUART_INTRS_UCR3; 2051 sc->sc_ucr4 &= ~IMXUART_INTRS_UCR4; 2052 2053 2054 bus_space_write_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 4); 2055 } 2056 2057 static void 2058 imxuart_control_rxint(struct imxuart_softc *sc, bool enable) 2059 { 2060 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2061 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2062 uint32_t ucr1, ucr2; 2063 2064 ucr1 = sc->sc_ucr1; 2065 ucr2 = sc->sc_ucr2; 2066 2067 if (enable) { 2068 ucr1 |= IMX_UCR1_RRDYEN; 2069 ucr2 |= IMX_UCR2_ATEN; 2070 } 2071 else { 2072 ucr1 &= ~IMX_UCR1_RRDYEN; 2073 ucr2 &= ~IMX_UCR2_ATEN; 2074 } 2075 2076 if (ucr1 != sc->sc_ucr1 || ucr2 != sc->sc_ucr2) { 2077 sc->sc_ucr1 = ucr1; 2078 sc->sc_ucr2 = ucr2; 2079 bus_space_write_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 2); 2080 } 2081 } 2082 2083 static void 2084 imxuart_control_txint(struct imxuart_softc *sc, bool enable) 2085 { 2086 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2087 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2088 uint32_t ucr1; 2089 uint32_t mask; 2090 2091 /* if parameter change is pending, get interrupt when Tx fifo 2092 is completely empty. otherwise, get interrupt when txfifo 2093 has less characters than threshold */ 2094 mask = sc->sc_pending ? IMX_UCR1_TXMPTYEN : IMX_UCR1_TRDYEN; 2095 2096 ucr1 = sc->sc_ucr1; 2097 2098 CLR(ucr1, IMX_UCR1_TXMPTYEN|IMX_UCR1_TRDYEN); 2099 if (enable) 2100 SET(ucr1, mask); 2101 2102 if (ucr1 != sc->sc_ucr1) { 2103 bus_space_write_4(iot, ioh, IMX_UCR1, ucr1); 2104 sc->sc_ucr1 = ucr1; 2105 } 2106 } 2107 2108 2109 static void 2110 imxuart_load_params(struct imxuart_softc *sc) 2111 { 2112 uint32_t ucr2; 2113 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2114 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2115 2116 ucr2 = (sc->sc_ucr2_d & ~IMX_UCR2_ATEN) | 2117 (sc->sc_ucr2 & IMX_UCR2_ATEN); 2118 2119 bus_space_write_4(iot, ioh, IMX_UCR2, ucr2); 2120 sc->sc_ucr2 = ucr2; 2121 } 2122 2123 static void 2124 imxuart_load_speed(struct imxuart_softc *sc) 2125 { 2126 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2127 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2128 int n, rfdiv, ufcr; 2129 2130 #ifdef notyet 2131 /* 2132 * Set the FIFO threshold based on the receive speed. 2133 * 2134 * * If it's a low speed, it's probably a mouse or some other 2135 * interactive device, so set the threshold low. 2136 * * If it's a high speed, trim the trigger level down to prevent 2137 * overflows. 2138 * * Otherwise set it a bit higher. 2139 */ 2140 if (t->c_ospeed <= 1200) 2141 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 2142 else if (t->c_ospeed <= 38400) 2143 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 2144 else 2145 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 2146 #endif 2147 2148 n = 32 - sc->sc_txfifo_thresh; 2149 n = MAX(2, n); 2150 2151 rfdiv = IMX_UFCR_DIVIDER_TO_RFDIV(imxuart_freqdiv); 2152 2153 ufcr = (n << IMX_UFCR_TXTL_SHIFT) | 2154 (rfdiv << IMX_UFCR_RFDIV_SHIFT) | 2155 (16 << IMX_UFCR_RXTL_SHIFT); 2156 2157 /* keep DCE/DTE bit */ 2158 ufcr |= bus_space_read_4(iot, ioh, IMX_UFCR) & IMX_UFCR_DCEDTE; 2159 2160 bus_space_write_4(iot, ioh, IMX_UFCR, ufcr); 2161 2162 /* UBIR must updated before UBMR */ 2163 bus_space_write_4(iot, ioh, 2164 IMX_UBIR, sc->sc_ratio.numerator); 2165 bus_space_write_4(iot, ioh, 2166 IMX_UBMR, sc->sc_ratio.modulator); 2167 2168 2169 } 2170 2171 2172 static void 2173 imxuart_load_pendings(struct imxuart_softc *sc) 2174 { 2175 if (sc->sc_pending & IMXUART_PEND_PARAM) 2176 imxuart_load_params(sc); 2177 if (sc->sc_pending & IMXUART_PEND_SPEED) 2178 imxuart_load_speed(sc); 2179 sc->sc_pending = 0; 2180 } 2181 2182 #if defined(IMXUARTCONSOLE) || defined(KGDB) 2183 2184 /* 2185 * The following functions are polled getc and putc routines, shared 2186 * by the console and kgdb glue. 2187 * 2188 * The read-ahead code is so that you can detect pending in-band 2189 * cn_magic in polled mode while doing output rather than having to 2190 * wait until the kernel decides it needs input. 2191 */ 2192 2193 #define READAHEAD_RING_LEN 16 2194 static int imxuart_readahead[READAHEAD_RING_LEN]; 2195 static int imxuart_readahead_in = 0; 2196 static int imxuart_readahead_out = 0; 2197 #define READAHEAD_IS_EMPTY() (imxuart_readahead_in==imxuart_readahead_out) 2198 #define READAHEAD_IS_FULL() \ 2199 (((imxuart_readahead_in+1) & (READAHEAD_RING_LEN-1)) ==imxuart_readahead_out) 2200 2201 int 2202 imxuart_common_getc(dev_t dev, struct imxuart_regs *regsp) 2203 { 2204 int s = splserial(); 2205 u_char c; 2206 bus_space_tag_t iot = regsp->ur_iot; 2207 bus_space_handle_t ioh = regsp->ur_ioh; 2208 uint32_t usr2; 2209 2210 /* got a character from reading things earlier */ 2211 if (imxuart_readahead_in != imxuart_readahead_out) { 2212 2213 c = imxuart_readahead[imxuart_readahead_out]; 2214 imxuart_readahead_out = (imxuart_readahead_out + 1) & 2215 (READAHEAD_RING_LEN-1); 2216 splx(s); 2217 return (c); 2218 } 2219 2220 /* block until a character becomes available */ 2221 while (!((usr2 = bus_space_read_4(iot, ioh, IMX_USR2)) & IMX_USR2_RDR)) 2222 ; 2223 2224 c = 0xff & bus_space_read_4(iot, ioh, IMX_URXD); 2225 2226 { 2227 int __attribute__((__unused__))cn_trapped = 0; /* unused */ 2228 #ifdef DDB 2229 extern int db_active; 2230 if (!db_active) 2231 #endif 2232 cn_check_magic(dev, c, imxuart_cnm_state); 2233 } 2234 splx(s); 2235 return (c); 2236 } 2237 2238 void 2239 imxuart_common_putc(dev_t dev, struct imxuart_regs *regsp, int c) 2240 { 2241 int s = splserial(); 2242 int cin, timo; 2243 bus_space_tag_t iot = regsp->ur_iot; 2244 bus_space_handle_t ioh = regsp->ur_ioh; 2245 uint32_t usr2; 2246 2247 if (!READAHEAD_IS_FULL() && 2248 ((usr2 = bus_space_read_4(iot, ioh, IMX_USR2)) & IMX_USR2_RDR)) { 2249 2250 int __attribute__((__unused__))cn_trapped = 0; 2251 cin = bus_space_read_4(iot, ioh, IMX_URXD); 2252 cn_check_magic(dev, cin & 0xff, imxuart_cnm_state); 2253 imxuart_readahead_in = (imxuart_readahead_in + 1) & 2254 (READAHEAD_RING_LEN-1); 2255 } 2256 2257 /* wait for any pending transmission to finish */ 2258 timo = 150000; 2259 do { 2260 if (bus_space_read_4(iot, ioh, IMX_USR1) & IMX_USR1_TRDY) { 2261 bus_space_write_4(iot, ioh, IMX_UTXD, c); 2262 break; 2263 } 2264 } while(--timo > 0); 2265 2266 IMXUART_BARRIER(regsp, BR | BW); 2267 2268 splx(s); 2269 } 2270 2271 /* 2272 * Initialize UART for use as console or KGDB line. 2273 */ 2274 int 2275 imxuart_init(struct imxuart_regs *regsp, int rate, tcflag_t cflag) 2276 { 2277 struct imxuart_baudrate_ratio ratio; 2278 int rfdiv = IMX_UFCR_DIVIDER_TO_RFDIV(imxuart_freqdiv); 2279 uint32_t ufcr; 2280 2281 if (bus_space_map(regsp->ur_iot, regsp->ur_iobase, IMX_UART_SIZE, 0, 2282 ®sp->ur_ioh)) 2283 return ENOMEM; /* ??? */ 2284 2285 if (imxuspeed(rate, &ratio) < 0) 2286 return EINVAL; 2287 2288 /* UBIR must updated before UBMR */ 2289 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, 2290 IMX_UBIR, ratio.numerator); 2291 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, 2292 IMX_UBMR, ratio.modulator); 2293 2294 2295 /* XXX: DTREN, DPEC */ 2296 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR3, 2297 IMX_UCR3_DSR|IMX_UCR3_RXDMUXSEL); 2298 2299 ufcr = (8 << IMX_UFCR_TXTL_SHIFT) | (rfdiv << IMX_UFCR_RFDIV_SHIFT) | 2300 (1 << IMX_UFCR_RXTL_SHIFT); 2301 /* XXX: keep DCE/DTE bit */ 2302 ufcr |= bus_space_read_4(regsp->ur_iot, regsp->ur_ioh, IMX_UFCR) & 2303 IMX_UFCR_DCEDTE; 2304 2305 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UFCR, ufcr); 2306 2307 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_ONEMS, 2308 imxuart_freq / imxuart_freqdiv / 1000); 2309 2310 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR2, 2311 IMX_UCR2_IRTS| 2312 IMX_UCR2_CTSC| 2313 IMX_UCR2_WS|IMX_UCR2_TXEN| 2314 IMX_UCR2_RXEN|IMX_UCR2_SRST); 2315 /* clear status registers */ 2316 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_USR1, 0xffff); 2317 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_USR2, 0xffff); 2318 2319 2320 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR1, 2321 IMX_UCR1_UARTEN); 2322 2323 return (0); 2324 } 2325 2326 2327 #endif 2328 2329 2330 #ifdef IMXUARTCONSOLE 2331 /* 2332 * Following are all routines needed for UART to act as console 2333 */ 2334 struct consdev imxucons = { 2335 NULL, NULL, imxucngetc, imxucnputc, imxucnpollc, NULL, NULL, NULL, 2336 NODEV, CN_NORMAL 2337 }; 2338 2339 2340 int 2341 imxuart_cons_attach(bus_space_tag_t iot, paddr_t iobase, u_int rate, 2342 tcflag_t cflag) 2343 { 2344 struct imxuart_regs regs; 2345 int res; 2346 2347 regs.ur_iot = iot; 2348 regs.ur_iobase = iobase; 2349 2350 res = imxuart_init(®s, rate, cflag); 2351 if (res) 2352 return (res); 2353 2354 cn_tab = &imxucons; 2355 cn_init_magic(&imxuart_cnm_state); 2356 cn_set_magic("\047\001"); /* default magic is BREAK */ 2357 2358 imxuconsrate = rate; 2359 imxuconscflag = cflag; 2360 2361 imxuconsregs = regs; 2362 2363 return 0; 2364 } 2365 2366 int 2367 imxucngetc(dev_t dev) 2368 { 2369 return (imxuart_common_getc(dev, &imxuconsregs)); 2370 } 2371 2372 /* 2373 * Console kernel output character routine. 2374 */ 2375 void 2376 imxucnputc(dev_t dev, int c) 2377 { 2378 imxuart_common_putc(dev, &imxuconsregs, c); 2379 } 2380 2381 void 2382 imxucnpollc(dev_t dev, int on) 2383 { 2384 2385 imxuart_readahead_in = 0; 2386 imxuart_readahead_out = 0; 2387 } 2388 2389 #endif /* IMXUARTCONSOLE */ 2390 2391 #ifdef KGDB 2392 int 2393 imxuart_kgdb_attach(bus_space_tag_t iot, paddr_t iobase, u_int rate, 2394 tcflag_t cflag) 2395 { 2396 int res; 2397 2398 if (iot == imxuconsregs.ur_iot && 2399 iobase == imxuconsregs.ur_iobase) { 2400 #if !defined(DDB) 2401 return (EBUSY); /* cannot share with console */ 2402 #else 2403 imxu_kgdb_regs.ur_iot = iot; 2404 imxu_kgdb_regs.ur_ioh = imxuconsregs.ur_ioh; 2405 imxu_kgdb_regs.ur_iobase = iobase; 2406 #endif 2407 } else { 2408 imxu_kgdb_regs.ur_iot = iot; 2409 imxu_kgdb_regs.ur_iobase = iobase; 2410 2411 res = imxuart_init(&imxu_kgdb_regs, rate, cflag); 2412 if (res) 2413 return (res); 2414 2415 /* 2416 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2417 * expects this to be initialized 2418 */ 2419 cn_init_magic(&imxuart_cnm_state); 2420 cn_set_magic("\047\001"); 2421 } 2422 2423 kgdb_attach(imxuart_kgdb_getc, imxuart_kgdb_putc, &imxu_kgdb_regs); 2424 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2425 2426 return (0); 2427 } 2428 2429 /* ARGSUSED */ 2430 int 2431 imxuart_kgdb_getc(void *arg) 2432 { 2433 struct imxuart_regs *regs = arg; 2434 2435 return (imxuart_common_getc(NODEV, regs)); 2436 } 2437 2438 /* ARGSUSED */ 2439 void 2440 imxuart_kgdb_putc(void *arg, int c) 2441 { 2442 struct imxuart_regs *regs = arg; 2443 2444 imxuart_common_putc(NODEV, regs, c); 2445 } 2446 #endif /* KGDB */ 2447 2448 /* helper function to identify the imxu ports used by 2449 console or KGDB (and not yet autoconf attached) */ 2450 int 2451 imxuart_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2452 { 2453 bus_space_handle_t help; 2454 2455 if (!imxuconsattached && 2456 iot == imxuconsregs.ur_iot && iobase == imxuconsregs.ur_iobase) 2457 help = imxuconsregs.ur_ioh; 2458 #ifdef KGDB 2459 else if (!imxu_kgdb_attached && 2460 iot == imxu_kgdb_regs.ur_iot && iobase == imxu_kgdb_regs.ur_iobase) 2461 help = imxu_kgdb_regs.ur_ioh; 2462 #endif 2463 else 2464 return (0); 2465 2466 if (ioh) 2467 *ioh = help; 2468 return (1); 2469 } 2470 2471 #ifdef notyet 2472 2473 bool 2474 imxuart_cleanup(device_t self, int how) 2475 { 2476 /* 2477 * this routine exists to serve as a shutdown hook for systems that 2478 * have firmware which doesn't interact properly with a imxuart device in 2479 * FIFO mode. 2480 */ 2481 struct imxuart_softc *sc = device_private(self); 2482 2483 if (ISSET(sc->sc_hwflags, IMXUART_HW_FIFO)) 2484 UR_WRITE_1(&sc->sc_regs, IMXUART_REG_FIFO, 0); 2485 2486 return true; 2487 } 2488 #endif 2489 2490 #ifdef notyet 2491 bool 2492 imxuart_suspend(device_t self PMF_FN_ARGS) 2493 { 2494 struct imxuart_softc *sc = device_private(self); 2495 2496 UR_WRITE_1(&sc->sc_regs, IMXUART_REG_IER, 0); 2497 (void)CSR_READ_1(&sc->sc_regs, IMXUART_REG_IIR); 2498 2499 return true; 2500 } 2501 #endif 2502 2503 #ifdef notyet 2504 bool 2505 imxuart_resume(device_t self PMF_FN_ARGS) 2506 { 2507 struct imxuart_softc *sc = device_private(self); 2508 2509 mutex_spin_enter(&sc->sc_lock); 2510 imxuart_loadchannelregs(sc); 2511 mutex_spin_exit(&sc->sc_lock); 2512 2513 return true; 2514 } 2515 #endif 2516 2517 static void 2518 imxuart_enable_debugport(struct imxuart_softc *sc) 2519 { 2520 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2521 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2522 2523 if (sc->sc_hwflags & (IMXUART_HW_CONSOLE|IMXUART_HW_KGDB)) { 2524 2525 /* Turn on line break interrupt, set carrier. */ 2526 2527 sc->sc_ucr3 |= IMX_UCR3_DSR; 2528 bus_space_write_4(iot, ioh, IMX_UCR3, sc->sc_ucr3); 2529 2530 sc->sc_ucr4 |= IMX_UCR4_BKEN; 2531 bus_space_write_4(iot, ioh, IMX_UCR4, sc->sc_ucr4); 2532 2533 sc->sc_ucr2 |= IMX_UCR2_TXEN|IMX_UCR2_RXEN| 2534 IMX_UCR2_CTS; 2535 bus_space_write_4(iot, ioh, IMX_UCR2, sc->sc_ucr2); 2536 2537 sc->sc_ucr1 |= IMX_UCR1_UARTEN; 2538 bus_space_write_4(iot, ioh, IMX_UCR1, sc->sc_ucr1); 2539 } 2540 } 2541 2542 2543 void 2544 imxuart_set_frequency(u_int freq, u_int div) 2545 { 2546 imxuart_freq = freq; 2547 imxuart_freqdiv = div; 2548 } 2549
Indexes created Tue Sep 30 07:10:03 GMT 2025