imxuart.c revision 1.15
1 /* $NetBSD: imxuart.c,v 1.15 2014/09/25 05:05:28 ryo Exp $ */ 2 3 /* 4 * Copyright (c) 2009, 2010 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* 31 * derived from sys/dev/ic/com.c 32 */ 33 34 /*- 35 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to The NetBSD Foundation 39 * by Charles M. Hannum. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 51 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 52 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 53 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 60 * POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Copyright (c) 1991 The Regents of the University of California. 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 3. Neither the name of the University nor the names of its contributors 76 * may be used to endorse or promote products derived from this software 77 * without specific prior written permission. 78 * 79 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 80 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 82 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 85 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 86 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 87 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 88 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 89 * SUCH DAMAGE. 90 * 91 * @(#)com.c 7.5 (Berkeley) 5/16/91 92 */ 93 94 /* 95 * driver for UART in i.MX SoC. 96 */ 97 98 #include <sys/cdefs.h> 99 __KERNEL_RCSID(0, "$NetBSD: imxuart.c,v 1.15 2014/09/25 05:05:28 ryo Exp $"); 100 101 #include "opt_imxuart.h" 102 #include "opt_ddb.h" 103 #include "opt_ddbparam.h" 104 #include "opt_kgdb.h" 105 #include "opt_lockdebug.h" 106 #include "opt_multiprocessor.h" 107 #include "opt_ntp.h" 108 #include "opt_imxuart.h" 109 #include "opt_imx.h" 110 111 #include "rnd.h" 112 #ifdef RND_COM 113 #include <sys/rnd.h> 114 #endif 115 116 #ifndef IMXUART_TOLERANCE 117 #define IMXUART_TOLERANCE 30 /* baud rate tolerance, in 0.1% units */ 118 #endif 119 120 #ifndef IMXUART_FREQDIV 121 #define IMXUART_FREQDIV 2 /* XXX */ 122 #endif 123 124 #ifndef IMXUART_FREQ 125 #define IMXUART_FREQ (56900000) 126 #endif 127 128 /* 129 * Override cnmagic(9) macro before including <sys/systm.h>. 130 * We need to know if cn_check_magic triggered debugger, so set a flag. 131 * Callers of cn_check_magic must declare int cn_trapped = 0; 132 * XXX: this is *ugly*! 133 */ 134 #define cn_trap() \ 135 do { \ 136 console_debugger(); \ 137 cn_trapped = 1; \ 138 } while (/* CONSTCOND */ 0) 139 140 #include <sys/param.h> 141 #include <sys/systm.h> 142 #include <sys/ioctl.h> 143 #include <sys/select.h> 144 #include <sys/poll.h> 145 #include <sys/tty.h> 146 #include <sys/proc.h> 147 #include <sys/conf.h> 148 #include <sys/file.h> 149 #include <sys/uio.h> 150 #include <sys/kernel.h> 151 #include <sys/syslog.h> 152 #include <sys/device.h> 153 #include <sys/malloc.h> 154 #include <sys/timepps.h> 155 #include <sys/vnode.h> 156 #include <sys/kauth.h> 157 #include <sys/intr.h> 158 159 #include <sys/bus.h> 160 161 #include <arm/imx/imxuartreg.h> 162 #include <arm/imx/imxuartvar.h> 163 #include <dev/cons.h> 164 165 #ifndef IMXUART_RING_SIZE 166 #define IMXUART_RING_SIZE 2048 167 #endif 168 169 typedef struct imxuart_softc { 170 device_t sc_dev; 171 172 struct imxuart_regs { 173 bus_space_tag_t ur_iot; 174 bus_space_handle_t ur_ioh; 175 bus_addr_t ur_iobase; 176 #if 0 177 bus_size_t ur_nports; 178 bus_size_t ur_map[16]; 179 #endif 180 } sc_regs; 181 182 #define sc_bt sc_regs.ur_iot 183 #define sc_bh sc_regs.ur_ioh 184 185 uint32_t sc_intrspec_enb; 186 uint32_t sc_ucr2_d; /* target value for UCR2 */ 187 uint32_t sc_ucr[4]; /* cached value of UCRn */ 188 #define sc_ucr1 sc_ucr[0] 189 #define sc_ucr2 sc_ucr[1] 190 #define sc_ucr3 sc_ucr[2] 191 #define sc_ucr4 sc_ucr[3] 192 193 uint sc_init_cnt; 194 195 bus_addr_t sc_addr; 196 bus_size_t sc_size; 197 int sc_intr; 198 199 u_char sc_hwflags; 200 /* Hardware flag masks */ 201 #define IMXUART_HW_FLOW __BIT(0) 202 #define IMXUART_HW_DEV_OK __BIT(1) 203 #define IMXUART_HW_CONSOLE __BIT(2) 204 #define IMXUART_HW_KGDB __BIT(3) 205 206 207 bool enabled; 208 209 u_char sc_swflags; 210 211 u_char sc_rx_flags; 212 #define IMXUART_RX_TTY_BLOCKED __BIT(0) 213 #define IMXUART_RX_TTY_OVERFLOWED __BIT(1) 214 #define IMXUART_RX_IBUF_BLOCKED __BIT(2) 215 #define IMXUART_RX_IBUF_OVERFLOWED __BIT(3) 216 #define IMXUART_RX_ANY_BLOCK \ 217 (IMXUART_RX_TTY_BLOCKED|IMXUART_RX_TTY_OVERFLOWED| \ 218 IMXUART_RX_IBUF_BLOCKED|IMXUART_RX_IBUF_OVERFLOWED) 219 220 bool sc_tx_busy, sc_tx_done, sc_tx_stopped; 221 bool sc_rx_ready,sc_st_check; 222 u_short sc_txfifo_len, sc_txfifo_thresh; 223 224 uint16_t *sc_rbuf; 225 u_int sc_rbuf_size; 226 u_int sc_rbuf_in; 227 u_int sc_rbuf_out; 228 #define IMXUART_RBUF_AVAIL(sc) \ 229 ((sc->sc_rbuf_out <= sc->sc_rbuf_in) ? \ 230 (sc->sc_rbuf_in - sc->sc_rbuf_out) : \ 231 (sc->sc_rbuf_size - (sc->sc_rbuf_out - sc->sc_rbuf_in))) 232 233 #define IMXUART_RBUF_SPACE(sc) \ 234 ((sc->sc_rbuf_in <= sc->sc_rbuf_out ? \ 235 sc->sc_rbuf_size - (sc->sc_rbuf_out - sc->sc_rbuf_in) : \ 236 sc->sc_rbuf_in - sc->sc_rbuf_out) - 1) 237 /* increment ringbuffer pointer */ 238 #define IMXUART_RBUF_INC(sc,v,i) (((v) + (i))&((sc->sc_rbuf_size)-1)) 239 u_int sc_r_lowat; 240 u_int sc_r_hiwat; 241 242 /* output chunk */ 243 u_char *sc_tba; 244 u_int sc_tbc; 245 u_int sc_heldtbc; 246 /* pending parameter changes */ 247 u_char sc_pending; 248 #define IMXUART_PEND_PARAM __BIT(0) 249 #define IMXUART_PEND_SPEED __BIT(1) 250 251 252 struct callout sc_diag_callout; 253 kmutex_t sc_lock; 254 void *sc_ih; /* interrupt handler */ 255 void *sc_si; /* soft interrupt */ 256 struct tty *sc_tty; 257 258 /* power management hooks */ 259 int (*enable)(struct imxuart_softc *); 260 void (*disable)(struct imxuart_softc *); 261 262 struct { 263 ulong err; 264 ulong brk; 265 ulong prerr; 266 ulong frmerr; 267 ulong ovrrun; 268 } sc_errors; 269 270 struct imxuart_baudrate_ratio { 271 uint16_t numerator; /* UBIR */ 272 uint16_t modulator; /* UBMR */ 273 } sc_ratio; 274 275 } imxuart_softc_t; 276 277 278 int imxuspeed(long, struct imxuart_baudrate_ratio *); 279 int imxuparam(struct tty *, struct termios *); 280 void imxustart(struct tty *); 281 int imxuhwiflow(struct tty *, int); 282 283 void imxuart_shutdown(struct imxuart_softc *); 284 void imxuart_loadchannelregs(struct imxuart_softc *); 285 void imxuart_hwiflow(struct imxuart_softc *); 286 void imxuart_break(struct imxuart_softc *, bool); 287 void imxuart_modem(struct imxuart_softc *, int); 288 void tiocm_to_imxu(struct imxuart_softc *, u_long, int); 289 int imxuart_to_tiocm(struct imxuart_softc *); 290 void imxuart_iflush(struct imxuart_softc *); 291 int imxuintr(void *); 292 293 int imxuart_common_getc(dev_t, struct imxuart_regs *); 294 void imxuart_common_putc(dev_t, struct imxuart_regs *, int); 295 296 297 int imxuart_init(struct imxuart_regs *, int, tcflag_t); 298 299 int imxucngetc(dev_t); 300 void imxucnputc(dev_t, int); 301 void imxucnpollc(dev_t, int); 302 303 static void imxuintr_read(struct imxuart_softc *); 304 static void imxuintr_send(struct imxuart_softc *); 305 306 static void imxuart_enable_debugport(struct imxuart_softc *); 307 static void imxuart_disable_all_interrupts(struct imxuart_softc *); 308 static void imxuart_control_rxint(struct imxuart_softc *, bool); 309 static void imxuart_control_txint(struct imxuart_softc *, bool); 310 static u_int imxuart_txfifo_space(struct imxuart_softc *sc); 311 312 static uint32_t cflag_to_ucr2(tcflag_t, uint32_t); 313 314 CFATTACH_DECL_NEW(imxuart, sizeof(struct imxuart_softc), 315 imxuart_match, imxuart_attach, NULL, NULL); 316 317 318 #define integrate static inline 319 void imxusoft(void *); 320 integrate void imxuart_rxsoft(struct imxuart_softc *, struct tty *); 321 integrate void imxuart_txsoft(struct imxuart_softc *, struct tty *); 322 integrate void imxuart_stsoft(struct imxuart_softc *, struct tty *); 323 integrate void imxuart_schedrx(struct imxuart_softc *); 324 void imxudiag(void *); 325 static void imxuart_load_speed(struct imxuart_softc *); 326 static void imxuart_load_params(struct imxuart_softc *); 327 integrate void imxuart_load_pendings(struct imxuart_softc *); 328 329 330 extern struct cfdriver imxuart_cd; 331 332 dev_type_open(imxuopen); 333 dev_type_close(imxuclose); 334 dev_type_read(imxuread); 335 dev_type_write(imxuwrite); 336 dev_type_ioctl(imxuioctl); 337 dev_type_stop(imxustop); 338 dev_type_tty(imxutty); 339 dev_type_poll(imxupoll); 340 341 const struct cdevsw imxcom_cdevsw = { 342 .d_open = imxuopen, 343 .d_close = imxuclose, 344 .d_read = imxuread, 345 .d_write = imxuwrite, 346 .d_ioctl = imxuioctl, 347 .d_stop = imxustop, 348 .d_tty = imxutty, 349 .d_poll = imxupoll, 350 .d_mmap = nommap, 351 .d_kqfilter = ttykqfilter, 352 .d_discard = nodiscard, 353 .d_flag = D_TTY 354 }; 355 356 /* 357 * Make this an option variable one can patch. 358 * But be warned: this must be a power of 2! 359 */ 360 u_int imxuart_rbuf_size = IMXUART_RING_SIZE; 361 362 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 363 u_int imxuart_rbuf_hiwat = (IMXUART_RING_SIZE * 1) / 4; 364 u_int imxuart_rbuf_lowat = (IMXUART_RING_SIZE * 3) / 4; 365 366 static struct imxuart_regs imxuconsregs; 367 static int imxuconsattached; 368 static int imxuconsrate; 369 static tcflag_t imxuconscflag; 370 static struct cnm_state imxuart_cnm_state; 371 372 u_int imxuart_freq = IMXUART_FREQ; 373 u_int imxuart_freqdiv = IMXUART_FREQDIV; 374 375 #ifdef KGDB 376 #include <sys/kgdb.h> 377 378 static struct imxuart_regs imxu_kgdb_regs; 379 static int imxu_kgdb_attached; 380 381 int imxuart_kgdb_getc(void *); 382 void imxuart_kgdb_putc(void *, int); 383 #endif /* KGDB */ 384 385 #define IMXUART_UNIT_MASK 0x7ffff 386 #define IMXUART_DIALOUT_MASK 0x80000 387 388 #define IMXUART_UNIT(x) (minor(x) & IMXUART_UNIT_MASK) 389 #define IMXUART_DIALOUT(x) (minor(x) & IMXUART_DIALOUT_MASK) 390 391 #define IMXUART_ISALIVE(sc) ((sc)->enabled != 0 && \ 392 device_is_active((sc)->sc_dev)) 393 394 #define BR BUS_SPACE_BARRIER_READ 395 #define BW BUS_SPACE_BARRIER_WRITE 396 #define IMXUART_BARRIER(r, f) \ 397 bus_space_barrier((r)->ur_iot, (r)->ur_ioh, 0, IMX_UART_SIZE, (f)) 398 399 400 void 401 imxuart_attach_common(device_t parent, device_t self, 402 bus_space_tag_t iot, paddr_t iobase, size_t size, int intr, int flags) 403 { 404 imxuart_softc_t *sc = device_private(self); 405 struct imxuart_regs *regsp = &sc->sc_regs; 406 struct tty *tp; 407 bus_space_handle_t ioh; 408 409 aprint_naive("\n"); 410 aprint_normal("\n"); 411 412 sc->sc_dev = self; 413 414 if (size <= 0) 415 size = IMX_UART_SIZE; 416 417 sc->sc_intr = intr; 418 regsp->ur_iot = iot; 419 regsp->ur_iobase = iobase; 420 421 if (bus_space_map(iot, regsp->ur_iobase, size, 0, &ioh)) { 422 return; 423 } 424 regsp->ur_ioh = ioh; 425 426 callout_init(&sc->sc_diag_callout, 0); 427 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 428 429 bus_space_read_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 4); 430 sc->sc_ucr2_d = sc->sc_ucr2; 431 432 /* Disable interrupts before configuring the device. */ 433 imxuart_disable_all_interrupts(sc); 434 435 if (regsp->ur_iobase == imxuconsregs.ur_iobase) { 436 imxuconsattached = 1; 437 438 /* Make sure the console is always "hardwired". */ 439 #if 0 440 delay(10000); /* wait for output to finish */ 441 #endif 442 SET(sc->sc_hwflags, IMXUART_HW_CONSOLE); 443 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 444 } 445 446 447 tp = tty_alloc(); 448 tp->t_oproc = imxustart; 449 tp->t_param = imxuparam; 450 tp->t_hwiflow = imxuhwiflow; 451 452 sc->sc_tty = tp; 453 sc->sc_rbuf = malloc(sizeof (*sc->sc_rbuf) * imxuart_rbuf_size, 454 M_DEVBUF, M_NOWAIT); 455 sc->sc_rbuf_size = imxuart_rbuf_size; 456 sc->sc_rbuf_in = sc->sc_rbuf_out = 0; 457 if (sc->sc_rbuf == NULL) { 458 aprint_error_dev(sc->sc_dev, 459 "unable to allocate ring buffer\n"); 460 return; 461 } 462 463 sc->sc_txfifo_len = 32; 464 sc->sc_txfifo_thresh = 16; /* when USR1.TRDY, fifo has space 465 * for this many characters */ 466 467 tty_attach(tp); 468 469 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 470 int maj; 471 472 /* locate the major number */ 473 maj = cdevsw_lookup_major(&imxcom_cdevsw); 474 475 if (maj != NODEVMAJOR) { 476 tp->t_dev = cn_tab->cn_dev = makedev(maj, 477 device_unit(sc->sc_dev)); 478 479 aprint_normal_dev(sc->sc_dev, "console\n"); 480 } 481 } 482 483 sc->sc_ih = intr_establish(sc->sc_intr, IPL_SERIAL, IST_LEVEL, 484 imxuintr, sc); 485 if (sc->sc_ih == NULL) 486 aprint_error_dev(sc->sc_dev, "intr_establish failed\n"); 487 488 #ifdef KGDB 489 /* 490 * Allow kgdb to "take over" this port. If this is 491 * not the console and is the kgdb device, it has 492 * exclusive use. If it's the console _and_ the 493 * kgdb device, it doesn't. 494 */ 495 if (regsp->ur_iobase == imxu_kgdb_regs.ur_iobase) { 496 if (!ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 497 imxu_kgdb_attached = 1; 498 499 SET(sc->sc_hwflags, IMXUART_HW_KGDB); 500 } 501 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 502 } 503 #endif 504 505 sc->sc_si = softint_establish(SOFTINT_SERIAL, imxusoft, sc); 506 507 #ifdef RND_COM 508 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 509 RND_TYPE_TTY, RND_FLAG_COLLECT_TIME | 510 RND_FLAG_ESTIMATE_TIME); 511 #endif 512 513 /* if there are no enable/disable functions, assume the device 514 is always enabled */ 515 if (!sc->enable) 516 sc->enabled = 1; 517 518 imxuart_enable_debugport(sc); 519 520 SET(sc->sc_hwflags, IMXUART_HW_DEV_OK); 521 522 //shutdownhook_establish(imxuart_shutdownhook, sc); 523 524 525 #if 0 526 { 527 uint32_t reg; 528 reg = bus_space_read_4(iot, ioh, IMX_UCR1); 529 reg |= IMX_UCR1_TXDMAEN | IMX_UCR1_RXDMAEN; 530 bus_space_write_4(iot, ioh, IMX_UCR1, reg); 531 } 532 #endif 533 } 534 535 /* 536 * baudrate = RefFreq / (16 * (UMBR + 1)/(UBIR + 1)) 537 * 538 * (UBIR + 1) / (UBMR + 1) = (16 * BaurdRate) / RefFreq 539 */ 540 541 static long 542 gcd(long m, long n) 543 { 544 545 if (m < n) 546 return gcd(n, m); 547 548 if (n <= 0) 549 return m; 550 return gcd(n, m % n); 551 } 552 553 554 int 555 imxuspeed(long speed, struct imxuart_baudrate_ratio *ratio) 556 { 557 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 558 long b = 16 * speed; 559 long f = imxuart_freq / imxuart_freqdiv; 560 long d; 561 int err = 0; 562 563 /* reduce b/f */ 564 while ((f > (1<<16) || b > (1<<16)) && (d = gcd(f, b)) > 1) { 565 f /= d; 566 b /= d; 567 } 568 569 570 while (f > (1<<16) || b > (1<<16)) { 571 f /= 2; 572 b /= 2; 573 } 574 if (f <= 0 || b <= 0) 575 return -1; 576 577 #ifdef DIAGNOSTIC 578 err = divrnd(((uint64_t)imxuart_freq) * 1000 / imxuart_freqdiv, 579 (uint64_t)speed * 16 * f / b) - 1000; 580 if (err < 0) 581 err = -err; 582 #endif 583 584 ratio->numerator = b-1; 585 ratio->modulator = f-1; 586 587 if (err > IMXUART_TOLERANCE) 588 return -1; 589 590 return 0; 591 #undef divrnd 592 } 593 594 #ifdef IMXUART_DEBUG 595 int imxuart_debug = 0; 596 597 void imxustatus(struct imxuart_softc *, const char *); 598 void 599 imxustatus(struct imxuart_softc *sc, const char *str) 600 { 601 struct tty *tp = sc->sc_tty; 602 603 aprint_normal_dev(sc->sc_dev, 604 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 605 str, 606 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 607 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 608 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 609 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 610 sc->sc_tx_stopped ? '+' : '-'); 611 612 aprint_normal_dev(sc->sc_dev, 613 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 614 str, 615 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 616 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 617 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 618 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 619 sc->sc_rx_flags); 620 } 621 #endif 622 623 #if 0 624 int 625 imxuart_detach(device_t self, int flags) 626 { 627 struct imxuart_softc *sc = device_private(self); 628 int maj, mn; 629 630 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) 631 return EBUSY; 632 633 /* locate the major number */ 634 maj = cdevsw_lookup_major(&imxcom_cdevsw); 635 636 /* Nuke the vnodes for any open instances. */ 637 mn = device_unit(self); 638 vdevgone(maj, mn, mn, VCHR); 639 640 mn |= IMXUART_DIALOUT_MASK; 641 vdevgone(maj, mn, mn, VCHR); 642 643 if (sc->sc_rbuf == NULL) { 644 /* 645 * Ring buffer allocation failed in the imxuart_attach_subr, 646 * only the tty is allocated, and nothing else. 647 */ 648 tty_free(sc->sc_tty); 649 return 0; 650 } 651 652 /* Free the receive buffer. */ 653 free(sc->sc_rbuf, M_DEVBUF); 654 655 /* Detach and free the tty. */ 656 tty_detach(sc->sc_tty); 657 tty_free(sc->sc_tty); 658 659 /* Unhook the soft interrupt handler. */ 660 softint_disestablish(sc->sc_si); 661 662 #ifdef RND_COM 663 /* Unhook the entropy source. */ 664 rnd_detach_source(&sc->rnd_source); 665 #endif 666 callout_destroy(&sc->sc_diag_callout); 667 668 /* Destroy the lock. */ 669 mutex_destroy(&sc->sc_lock); 670 671 return (0); 672 } 673 #endif 674 675 #ifdef notyet 676 int 677 imxuart_activate(device_t self, enum devact act) 678 { 679 struct imxuart_softc *sc = device_private(self); 680 int rv = 0; 681 682 switch (act) { 683 case DVACT_ACTIVATE: 684 rv = EOPNOTSUPP; 685 break; 686 687 case DVACT_DEACTIVATE: 688 if (sc->sc_hwflags & (IMXUART_HW_CONSOLE|IMXUART_HW_KGDB)) { 689 rv = EBUSY; 690 break; 691 } 692 693 if (sc->disable != NULL && sc->enabled != 0) { 694 (*sc->disable)(sc); 695 sc->enabled = 0; 696 } 697 break; 698 } 699 700 return (rv); 701 } 702 #endif 703 704 void 705 imxuart_shutdown(struct imxuart_softc *sc) 706 { 707 struct tty *tp = sc->sc_tty; 708 709 mutex_spin_enter(&sc->sc_lock); 710 711 /* If we were asserting flow control, then deassert it. */ 712 SET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED); 713 imxuart_hwiflow(sc); 714 715 /* Clear any break condition set with TIOCSBRK. */ 716 imxuart_break(sc, false); 717 718 /* 719 * Hang up if necessary. Wait a bit, so the other side has time to 720 * notice even if we immediately open the port again. 721 * Avoid tsleeping above splhigh(). 722 */ 723 if (ISSET(tp->t_cflag, HUPCL)) { 724 imxuart_modem(sc, 0); 725 mutex_spin_exit(&sc->sc_lock); 726 /* XXX will only timeout */ 727 (void) kpause(ttclos, false, hz, NULL); 728 mutex_spin_enter(&sc->sc_lock); 729 } 730 731 /* Turn off interrupts. */ 732 imxuart_disable_all_interrupts(sc); 733 /* re-enable recv interrupt for console or kgdb port */ 734 imxuart_enable_debugport(sc); 735 736 mutex_spin_exit(&sc->sc_lock); 737 738 #ifdef notyet 739 if (sc->disable) { 740 #ifdef DIAGNOSTIC 741 if (!sc->enabled) 742 panic("imxuart_shutdown: not enabled?"); 743 #endif 744 (*sc->disable)(sc); 745 sc->enabled = 0; 746 } 747 #endif 748 } 749 750 int 751 imxuopen(dev_t dev, int flag, int mode, struct lwp *l) 752 { 753 struct imxuart_softc *sc; 754 struct tty *tp; 755 int s; 756 int error; 757 758 sc = device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 759 if (sc == NULL || !ISSET(sc->sc_hwflags, IMXUART_HW_DEV_OK) || 760 sc->sc_rbuf == NULL) 761 return (ENXIO); 762 763 if (!device_is_active(sc->sc_dev)) 764 return (ENXIO); 765 766 #ifdef KGDB 767 /* 768 * If this is the kgdb port, no other use is permitted. 769 */ 770 if (ISSET(sc->sc_hwflags, IMXUART_HW_KGDB)) 771 return (EBUSY); 772 #endif 773 774 tp = sc->sc_tty; 775 776 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 777 return (EBUSY); 778 779 s = spltty(); 780 781 /* 782 * Do the following iff this is a first open. 783 */ 784 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 785 struct termios t; 786 787 tp->t_dev = dev; 788 789 790 #ifdef notyet 791 if (sc->enable) { 792 if ((*sc->enable)(sc)) { 793 splx(s); 794 aprint_error_dev(sc->sc_dev, 795 "device enable failed\n"); 796 return (EIO); 797 } 798 sc->enabled = 1; 799 } 800 #endif 801 802 mutex_spin_enter(&sc->sc_lock); 803 804 imxuart_disable_all_interrupts(sc); 805 806 /* Fetch the current modem control status, needed later. */ 807 808 #ifdef IMXUART_PPS 809 /* Clear PPS capture state on first open. */ 810 mutex_spin_enter(&timecounter_lock); 811 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 812 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 813 pps_init(&sc->sc_pps_state); 814 mutex_spin_exit(&timecounter_lock); 815 #endif 816 817 mutex_spin_exit(&sc->sc_lock); 818 819 /* 820 * Initialize the termios status to the defaults. Add in the 821 * sticky bits from TIOCSFLAGS. 822 */ 823 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 824 t.c_ospeed = imxuconsrate; 825 t.c_cflag = imxuconscflag; 826 } else { 827 t.c_ospeed = TTYDEF_SPEED; 828 t.c_cflag = TTYDEF_CFLAG; 829 } 830 t.c_ispeed = t.c_ospeed; 831 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 832 SET(t.c_cflag, CLOCAL); 833 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 834 SET(t.c_cflag, CRTSCTS); 835 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 836 SET(t.c_cflag, MDMBUF); 837 /* Make sure imxuparam() will do something. */ 838 tp->t_ospeed = 0; 839 (void) imxuparam(tp, &t); 840 tp->t_iflag = TTYDEF_IFLAG; 841 tp->t_oflag = TTYDEF_OFLAG; 842 tp->t_lflag = TTYDEF_LFLAG; 843 ttychars(tp); 844 ttsetwater(tp); 845 846 mutex_spin_enter(&sc->sc_lock); 847 848 /* 849 * Turn on DTR. We must always do this, even if carrier is not 850 * present, because otherwise we'd have to use TIOCSDTR 851 * immediately after setting CLOCAL, which applications do not 852 * expect. We always assert DTR while the device is open 853 * unless explicitly requested to deassert it. 854 */ 855 imxuart_modem(sc, 1); 856 857 /* Clear the input ring, and unblock. */ 858 sc->sc_rbuf_in = sc->sc_rbuf_out = 0; 859 imxuart_iflush(sc); 860 CLR(sc->sc_rx_flags, IMXUART_RX_ANY_BLOCK); 861 imxuart_hwiflow(sc); 862 863 /* Turn on interrupts. */ 864 imxuart_control_rxint(sc, true); 865 866 #ifdef IMXUART_DEBUG 867 if (imxuart_debug) 868 imxustatus(sc, "imxuopen "); 869 #endif 870 871 mutex_spin_exit(&sc->sc_lock); 872 } 873 874 splx(s); 875 876 #if 0 877 error = ttyopen(tp, IMXUART_DIALOUT(dev), ISSET(flag, O_NONBLOCK)); 878 #else 879 error = ttyopen(tp, 1, ISSET(flag, O_NONBLOCK)); 880 #endif 881 if (error) 882 goto bad; 883 884 error = (*tp->t_linesw->l_open)(dev, tp); 885 if (error) 886 goto bad; 887 888 return (0); 889 890 bad: 891 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 892 /* 893 * We failed to open the device, and nobody else had it opened. 894 * Clean up the state as appropriate. 895 */ 896 imxuart_shutdown(sc); 897 } 898 899 return (error); 900 } 901 902 int 903 imxuclose(dev_t dev, int flag, int mode, struct lwp *l) 904 { 905 struct imxuart_softc *sc = 906 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 907 struct tty *tp = sc->sc_tty; 908 909 /* XXX This is for cons.c. */ 910 if (!ISSET(tp->t_state, TS_ISOPEN)) 911 return (0); 912 913 (*tp->t_linesw->l_close)(tp, flag); 914 ttyclose(tp); 915 916 if (IMXUART_ISALIVE(sc) == 0) 917 return (0); 918 919 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 920 /* 921 * Although we got a last close, the device may still be in 922 * use; e.g. if this was the dialout node, and there are still 923 * processes waiting for carrier on the non-dialout node. 924 */ 925 imxuart_shutdown(sc); 926 } 927 928 return (0); 929 } 930 931 int 932 imxuread(dev_t dev, struct uio *uio, int flag) 933 { 934 struct imxuart_softc *sc = 935 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 936 struct tty *tp = sc->sc_tty; 937 938 if (IMXUART_ISALIVE(sc) == 0) 939 return (EIO); 940 941 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 942 } 943 944 int 945 imxuwrite(dev_t dev, struct uio *uio, int flag) 946 { 947 struct imxuart_softc *sc = 948 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 949 struct tty *tp = sc->sc_tty; 950 951 if (IMXUART_ISALIVE(sc) == 0) 952 return (EIO); 953 954 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 955 } 956 957 int 958 imxupoll(dev_t dev, int events, struct lwp *l) 959 { 960 struct imxuart_softc *sc = 961 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 962 struct tty *tp = sc->sc_tty; 963 964 if (IMXUART_ISALIVE(sc) == 0) 965 return (POLLHUP); 966 967 return ((*tp->t_linesw->l_poll)(tp, events, l)); 968 } 969 970 struct tty * 971 imxutty(dev_t dev) 972 { 973 struct imxuart_softc *sc = 974 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 975 struct tty *tp = sc->sc_tty; 976 977 return (tp); 978 } 979 980 int 981 imxuioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 982 { 983 struct imxuart_softc *sc; 984 struct tty *tp; 985 int error; 986 987 sc = device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 988 if (sc == NULL) 989 return ENXIO; 990 if (IMXUART_ISALIVE(sc) == 0) 991 return (EIO); 992 993 tp = sc->sc_tty; 994 995 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 996 if (error != EPASSTHROUGH) 997 return (error); 998 999 error = ttioctl(tp, cmd, data, flag, l); 1000 if (error != EPASSTHROUGH) 1001 return (error); 1002 1003 error = 0; 1004 switch (cmd) { 1005 case TIOCSFLAGS: 1006 error = kauth_authorize_device_tty(l->l_cred, 1007 KAUTH_DEVICE_TTY_PRIVSET, tp); 1008 break; 1009 default: 1010 /* nothing */ 1011 break; 1012 } 1013 if (error) { 1014 return error; 1015 } 1016 1017 mutex_spin_enter(&sc->sc_lock); 1018 1019 switch (cmd) { 1020 case TIOCSBRK: 1021 imxuart_break(sc, true); 1022 break; 1023 1024 case TIOCCBRK: 1025 imxuart_break(sc, false); 1026 break; 1027 1028 case TIOCSDTR: 1029 imxuart_modem(sc, 1); 1030 break; 1031 1032 case TIOCCDTR: 1033 imxuart_modem(sc, 0); 1034 break; 1035 1036 case TIOCGFLAGS: 1037 *(int *)data = sc->sc_swflags; 1038 break; 1039 1040 case TIOCSFLAGS: 1041 sc->sc_swflags = *(int *)data; 1042 break; 1043 1044 case TIOCMSET: 1045 case TIOCMBIS: 1046 case TIOCMBIC: 1047 tiocm_to_imxu(sc, cmd, *(int *)data); 1048 break; 1049 1050 case TIOCMGET: 1051 *(int *)data = imxuart_to_tiocm(sc); 1052 break; 1053 1054 #ifdef notyet 1055 case PPS_IOC_CREATE: 1056 case PPS_IOC_DESTROY: 1057 case PPS_IOC_GETPARAMS: 1058 case PPS_IOC_SETPARAMS: 1059 case PPS_IOC_GETCAP: 1060 case PPS_IOC_FETCH: 1061 #ifdef PPS_SYNC 1062 case PPS_IOC_KCBIND: 1063 #endif 1064 mutex_spin_enter(&timecounter_lock); 1065 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1066 mutex_spin_exit(&timecounter_lock); 1067 break; 1068 1069 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1070 mutex_spin_enter(&timecounter_lock); 1071 #ifndef PPS_TRAILING_EDGE 1072 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1073 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1074 #else 1075 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1076 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1077 #endif 1078 mutex_spin_exit(&timecounter_lock); 1079 break; 1080 #endif 1081 1082 default: 1083 error = EPASSTHROUGH; 1084 break; 1085 } 1086 1087 mutex_spin_exit(&sc->sc_lock); 1088 1089 #ifdef IMXUART_DEBUG 1090 if (imxuart_debug) 1091 imxustatus(sc, "imxuioctl "); 1092 #endif 1093 1094 return (error); 1095 } 1096 1097 integrate void 1098 imxuart_schedrx(struct imxuart_softc *sc) 1099 { 1100 sc->sc_rx_ready = 1; 1101 1102 /* Wake up the poller. */ 1103 softint_schedule(sc->sc_si); 1104 } 1105 1106 void 1107 imxuart_break(struct imxuart_softc *sc, bool onoff) 1108 { 1109 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1110 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1111 1112 if (onoff) 1113 SET(sc->sc_ucr1, IMX_UCR1_SNDBRK); 1114 else 1115 CLR(sc->sc_ucr1, IMX_UCR1_SNDBRK); 1116 1117 bus_space_write_4(iot, ioh, IMX_UCR1, sc->sc_ucr1); 1118 } 1119 1120 void 1121 imxuart_modem(struct imxuart_softc *sc, int onoff) 1122 { 1123 #ifdef notyet 1124 if (sc->sc_mcr_dtr == 0) 1125 return; 1126 1127 if (onoff) 1128 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1129 else 1130 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1131 1132 if (!sc->sc_heldchange) { 1133 if (sc->sc_tx_busy) { 1134 sc->sc_heldtbc = sc->sc_tbc; 1135 sc->sc_tbc = 0; 1136 sc->sc_heldchange = 1; 1137 } else 1138 imxuart_loadchannelregs(sc); 1139 } 1140 #endif 1141 } 1142 1143 /* 1144 * RTS output is controlled by UCR2.CTS bit. 1145 * DTR output is controlled by UCR3.DSR bit. 1146 * (i.MX reference manual uses names in DCE mode) 1147 * 1148 * note: if UCR2.CTSC == 1 for automatic HW flow control, UCR2.CTS is ignored. 1149 */ 1150 void 1151 tiocm_to_imxu(struct imxuart_softc *sc, u_long how, int ttybits) 1152 { 1153 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1154 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1155 1156 uint32_t ucr2 = sc->sc_ucr2_d; 1157 uint32_t ucr3 = sc->sc_ucr3; 1158 1159 uint32_t ucr2_mask = 0; 1160 uint32_t ucr3_mask = 0; 1161 1162 1163 if (ISSET(ttybits, TIOCM_DTR)) 1164 ucr3_mask = IMX_UCR3_DSR; 1165 if (ISSET(ttybits, TIOCM_RTS)) 1166 ucr2_mask = IMX_UCR2_CTS; 1167 1168 switch (how) { 1169 case TIOCMBIC: 1170 CLR(ucr2, ucr2_mask); 1171 CLR(ucr3, ucr3_mask); 1172 break; 1173 1174 case TIOCMBIS: 1175 SET(ucr2, ucr2_mask); 1176 SET(ucr3, ucr3_mask); 1177 break; 1178 1179 case TIOCMSET: 1180 CLR(ucr2, ucr2_mask); 1181 CLR(ucr3, ucr3_mask); 1182 SET(ucr2, ucr2_mask); 1183 SET(ucr3, ucr3_mask); 1184 break; 1185 } 1186 1187 if (ucr3 != sc->sc_ucr3) { 1188 bus_space_write_4(iot, ioh, IMX_UCR3, ucr3); 1189 sc->sc_ucr3 = ucr3; 1190 } 1191 1192 if (ucr2 == sc->sc_ucr2_d) 1193 return; 1194 1195 sc->sc_ucr2_d = ucr2; 1196 /* update CTS bit only */ 1197 ucr2 = (sc->sc_ucr2 & ~IMX_UCR2_CTS) | 1198 (ucr2 & IMX_UCR2_CTS); 1199 1200 bus_space_write_4(iot, ioh, IMX_UCR2, ucr2); 1201 sc->sc_ucr2 = ucr2; 1202 } 1203 1204 int 1205 imxuart_to_tiocm(struct imxuart_softc *sc) 1206 { 1207 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1208 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1209 int ttybits = 0; 1210 uint32_t usr[2]; 1211 1212 if (ISSET(sc->sc_ucr3, IMX_UCR3_DSR)) 1213 SET(ttybits, TIOCM_DTR); 1214 if (ISSET(sc->sc_ucr2, IMX_UCR2_CTS)) 1215 SET(ttybits, TIOCM_RTS); 1216 1217 bus_space_read_region_4(iot, ioh, IMX_USR1, usr, 2); 1218 1219 if (ISSET(usr[0], IMX_USR1_RTSS)) 1220 SET(ttybits, TIOCM_CTS); 1221 1222 if (ISSET(usr[1], IMX_USR2_DCDIN)) 1223 SET(ttybits, TIOCM_CD); 1224 1225 #if 0 1226 /* XXXbsh: I couldn't find the way to read ipp_uart_dsr_dte_i signal, 1227 although there are bits in UART registers to detect delta of DSR. 1228 */ 1229 if (ISSET(imxubits, MSR_DSR)) 1230 SET(ttybits, TIOCM_DSR); 1231 #endif 1232 1233 if (ISSET(usr[1], IMX_USR2_RIIN)) 1234 SET(ttybits, TIOCM_RI); 1235 1236 1237 #ifdef notyet 1238 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1239 SET(ttybits, TIOCM_LE); 1240 #endif 1241 1242 return (ttybits); 1243 } 1244 1245 static uint32_t 1246 cflag_to_ucr2(tcflag_t cflag, uint32_t oldval) 1247 { 1248 uint32_t val = oldval; 1249 1250 CLR(val,IMX_UCR2_WS|IMX_UCR2_PREN|IMX_UCR2_PROE|IMX_UCR2_STPB); 1251 1252 switch (cflag & CSIZE) { 1253 case CS5: 1254 case CS6: 1255 /* not suppreted. use 7-bits */ 1256 case CS7: 1257 break; 1258 case CS8: 1259 SET(val, IMX_UCR2_WS); 1260 break; 1261 } 1262 1263 1264 if (ISSET(cflag, PARENB)) { 1265 SET(val, IMX_UCR2_PREN); 1266 1267 /* odd parity */ 1268 if (!ISSET(cflag, PARODD)) 1269 SET(val, IMX_UCR2_PROE); 1270 } 1271 1272 if (ISSET(cflag, CSTOPB)) 1273 SET(val, IMX_UCR2_STPB); 1274 1275 val |= IMX_UCR2_TXEN| IMX_UCR2_RXEN|IMX_UCR2_SRST; 1276 1277 return val; 1278 } 1279 1280 int 1281 imxuparam(struct tty *tp, struct termios *t) 1282 { 1283 struct imxuart_softc *sc = 1284 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1285 struct imxuart_baudrate_ratio ratio; 1286 uint32_t ucr2; 1287 bool change_speed = tp->t_ospeed != t->c_ospeed; 1288 1289 if (IMXUART_ISALIVE(sc) == 0) 1290 return (EIO); 1291 1292 /* Check requested parameters. */ 1293 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1294 return (EINVAL); 1295 1296 /* 1297 * For the console, always force CLOCAL and !HUPCL, so that the port 1298 * is always active. 1299 */ 1300 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1301 ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 1302 SET(t->c_cflag, CLOCAL); 1303 CLR(t->c_cflag, HUPCL); 1304 } 1305 1306 /* 1307 * If there were no changes, don't do anything. This avoids dropping 1308 * input and improves performance when all we did was frob things like 1309 * VMIN and VTIME. 1310 */ 1311 if ( !change_speed && tp->t_cflag == t->c_cflag) 1312 return (0); 1313 1314 if (change_speed) { 1315 /* calculate baudrate modulator value */ 1316 if (imxuspeed(t->c_ospeed, &ratio) < 0) 1317 return (EINVAL); 1318 sc->sc_ratio = ratio; 1319 } 1320 1321 ucr2 = cflag_to_ucr2(t->c_cflag, sc->sc_ucr2_d); 1322 1323 mutex_spin_enter(&sc->sc_lock); 1324 1325 #if 0 /* flow control stuff. not yet */ 1326 /* 1327 * If we're not in a mode that assumes a connection is present, then 1328 * ignore carrier changes. 1329 */ 1330 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1331 sc->sc_msr_dcd = 0; 1332 else 1333 sc->sc_msr_dcd = MSR_DCD; 1334 /* 1335 * Set the flow control pins depending on the current flow control 1336 * mode. 1337 */ 1338 if (ISSET(t->c_cflag, CRTSCTS)) { 1339 sc->sc_mcr_dtr = MCR_DTR; 1340 sc->sc_mcr_rts = MCR_RTS; 1341 sc->sc_msr_cts = MSR_CTS; 1342 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1343 } else if (ISSET(t->c_cflag, MDMBUF)) { 1344 /* 1345 * For DTR/DCD flow control, make sure we don't toggle DTR for 1346 * carrier detection. 1347 */ 1348 sc->sc_mcr_dtr = 0; 1349 sc->sc_mcr_rts = MCR_DTR; 1350 sc->sc_msr_cts = MSR_DCD; 1351 sc->sc_efr = 0; 1352 } else { 1353 /* 1354 * If no flow control, then always set RTS. This will make 1355 * the other side happy if it mistakenly thinks we're doing 1356 * RTS/CTS flow control. 1357 */ 1358 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1359 sc->sc_mcr_rts = 0; 1360 sc->sc_msr_cts = 0; 1361 sc->sc_efr = 0; 1362 if (ISSET(sc->sc_mcr, MCR_DTR)) 1363 SET(sc->sc_mcr, MCR_RTS); 1364 else 1365 CLR(sc->sc_mcr, MCR_RTS); 1366 } 1367 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1368 #endif 1369 1370 /* And copy to tty. */ 1371 tp->t_ispeed = t->c_ospeed; 1372 tp->t_ospeed = t->c_ospeed; 1373 tp->t_cflag = t->c_cflag; 1374 1375 if (!change_speed && ucr2 == sc->sc_ucr2_d) { 1376 /* noop */ 1377 } 1378 else if (!sc->sc_pending && !sc->sc_tx_busy) { 1379 if (ucr2 != sc->sc_ucr2_d) { 1380 sc->sc_ucr2_d = ucr2; 1381 imxuart_load_params(sc); 1382 } 1383 if (change_speed) 1384 imxuart_load_speed(sc); 1385 } 1386 else { 1387 if (!sc->sc_pending) { 1388 sc->sc_heldtbc = sc->sc_tbc; 1389 sc->sc_tbc = 0; 1390 } 1391 sc->sc_pending |= 1392 (ucr2 == sc->sc_ucr2_d ? 0 : IMXUART_PEND_PARAM) | 1393 (change_speed ? 0 : IMXUART_PEND_SPEED); 1394 sc->sc_ucr2_d = ucr2; 1395 } 1396 1397 if (!ISSET(t->c_cflag, CHWFLOW)) { 1398 /* Disable the high water mark. */ 1399 sc->sc_r_hiwat = 0; 1400 sc->sc_r_lowat = 0; 1401 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED)) { 1402 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED); 1403 imxuart_schedrx(sc); 1404 } 1405 if (ISSET(sc->sc_rx_flags, 1406 IMXUART_RX_TTY_BLOCKED|IMXUART_RX_IBUF_BLOCKED)) { 1407 CLR(sc->sc_rx_flags, 1408 IMXUART_RX_TTY_BLOCKED|IMXUART_RX_IBUF_BLOCKED); 1409 imxuart_hwiflow(sc); 1410 } 1411 } else { 1412 sc->sc_r_hiwat = imxuart_rbuf_hiwat; 1413 sc->sc_r_lowat = imxuart_rbuf_lowat; 1414 } 1415 1416 mutex_spin_exit(&sc->sc_lock); 1417 1418 #if 0 1419 /* 1420 * Update the tty layer's idea of the carrier bit, in case we changed 1421 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1422 * explicit request. 1423 */ 1424 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1425 #else 1426 /* XXX: always report that we have DCD */ 1427 (void) (*tp->t_linesw->l_modem)(tp, 1); 1428 #endif 1429 1430 #ifdef IMXUART_DEBUG 1431 if (imxuart_debug) 1432 imxustatus(sc, "imxuparam "); 1433 #endif 1434 1435 if (!ISSET(t->c_cflag, CHWFLOW)) { 1436 if (sc->sc_tx_stopped) { 1437 sc->sc_tx_stopped = 0; 1438 imxustart(tp); 1439 } 1440 } 1441 1442 return (0); 1443 } 1444 1445 void 1446 imxuart_iflush(struct imxuart_softc *sc) 1447 { 1448 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1449 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1450 #ifdef DIAGNOSTIC 1451 uint32_t reg = 0xffff; 1452 #endif 1453 int timo; 1454 1455 timo = 50000; 1456 /* flush any pending I/O */ 1457 while (ISSET(bus_space_read_4(iot, ioh, IMX_USR2), IMX_USR2_RDR) 1458 && --timo) 1459 #ifdef DIAGNOSTIC 1460 reg = 1461 #else 1462 (void) 1463 #endif 1464 bus_space_read_4(iot, ioh, IMX_URXD); 1465 #ifdef DIAGNOSTIC 1466 if (!timo) 1467 aprint_error_dev(sc->sc_dev, "imxuart_iflush timeout %02x\n", reg); 1468 #endif 1469 } 1470 1471 int 1472 imxuhwiflow(struct tty *tp, int block) 1473 { 1474 struct imxuart_softc *sc = 1475 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1476 1477 if (IMXUART_ISALIVE(sc) == 0) 1478 return (0); 1479 1480 #ifdef notyet 1481 if (sc->sc_mcr_rts == 0) 1482 return (0); 1483 #endif 1484 1485 mutex_spin_enter(&sc->sc_lock); 1486 1487 if (block) { 1488 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) { 1489 SET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED); 1490 imxuart_hwiflow(sc); 1491 } 1492 } else { 1493 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED)) { 1494 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED); 1495 imxuart_schedrx(sc); 1496 } 1497 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) { 1498 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED); 1499 imxuart_hwiflow(sc); 1500 } 1501 } 1502 1503 mutex_spin_exit(&sc->sc_lock); 1504 return (1); 1505 } 1506 1507 /* 1508 * (un)block input via hw flowcontrol 1509 */ 1510 void 1511 imxuart_hwiflow(struct imxuart_softc *sc) 1512 { 1513 #ifdef notyet 1514 struct imxuart_regs *regsp= &sc->sc_regs; 1515 1516 if (sc->sc_mcr_rts == 0) 1517 return; 1518 1519 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1520 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1521 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1522 } else { 1523 SET(sc->sc_mcr, sc->sc_mcr_rts); 1524 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1525 } 1526 UR_WRITE_1(regsp, IMXUART_REG_MCR, sc->sc_mcr_active); 1527 #endif 1528 } 1529 1530 1531 void 1532 imxustart(struct tty *tp) 1533 { 1534 struct imxuart_softc *sc = 1535 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1536 int s; 1537 u_char *tba; 1538 int tbc; 1539 u_int n; 1540 u_int space; 1541 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1542 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1543 1544 if (IMXUART_ISALIVE(sc) == 0) 1545 return; 1546 1547 s = spltty(); 1548 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1549 goto out; 1550 if (sc->sc_tx_stopped) 1551 goto out; 1552 if (!ttypull(tp)) 1553 goto out; 1554 1555 /* Grab the first contiguous region of buffer space. */ 1556 tba = tp->t_outq.c_cf; 1557 tbc = ndqb(&tp->t_outq, 0); 1558 1559 mutex_spin_enter(&sc->sc_lock); 1560 1561 sc->sc_tba = tba; 1562 sc->sc_tbc = tbc; 1563 1564 SET(tp->t_state, TS_BUSY); 1565 sc->sc_tx_busy = 1; 1566 1567 space = imxuart_txfifo_space(sc); 1568 n = MIN(sc->sc_tbc, space); 1569 1570 bus_space_write_multi_1(iot, ioh, IMX_UTXD, sc->sc_tba, n); 1571 sc->sc_tbc -= n; 1572 sc->sc_tba += n; 1573 1574 /* Enable transmit completion interrupts */ 1575 imxuart_control_txint(sc, true); 1576 1577 mutex_spin_exit(&sc->sc_lock); 1578 out: 1579 splx(s); 1580 return; 1581 } 1582 1583 /* 1584 * Stop output on a line. 1585 */ 1586 void 1587 imxustop(struct tty *tp, int flag) 1588 { 1589 struct imxuart_softc *sc = 1590 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1591 1592 mutex_spin_enter(&sc->sc_lock); 1593 if (ISSET(tp->t_state, TS_BUSY)) { 1594 /* Stop transmitting at the next chunk. */ 1595 sc->sc_tbc = 0; 1596 sc->sc_heldtbc = 0; 1597 if (!ISSET(tp->t_state, TS_TTSTOP)) 1598 SET(tp->t_state, TS_FLUSH); 1599 } 1600 mutex_spin_exit(&sc->sc_lock); 1601 } 1602 1603 void 1604 imxudiag(void *arg) 1605 { 1606 #ifdef notyet 1607 struct imxuart_softc *sc = arg; 1608 int overflows, floods; 1609 1610 mutex_spin_enter(&sc->sc_lock); 1611 overflows = sc->sc_overflows; 1612 sc->sc_overflows = 0; 1613 floods = sc->sc_floods; 1614 sc->sc_floods = 0; 1615 sc->sc_errors = 0; 1616 mutex_spin_exit(&sc->sc_lock); 1617 1618 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1619 device_xname(sc->sc_dev), 1620 overflows, overflows == 1 ? "" : "s", 1621 floods, floods == 1 ? "" : "s"); 1622 #endif 1623 } 1624 1625 integrate void 1626 imxuart_rxsoft(struct imxuart_softc *sc, struct tty *tp) 1627 { 1628 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1629 u_int cc, scc, outp; 1630 uint16_t data; 1631 u_int code; 1632 1633 scc = cc = IMXUART_RBUF_AVAIL(sc); 1634 1635 #if 0 1636 if (cc == imxuart_rbuf_size-1) { 1637 sc->sc_floods++; 1638 if (sc->sc_errors++ == 0) 1639 callout_reset(&sc->sc_diag_callout, 60 * hz, 1640 imxudiag, sc); 1641 } 1642 #endif 1643 1644 /* If not yet open, drop the entire buffer content here */ 1645 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1646 sc->sc_rbuf_out = sc->sc_rbuf_in; 1647 cc = 0; 1648 } 1649 1650 outp = sc->sc_rbuf_out; 1651 1652 #define ERRBITS (IMX_URXD_PRERR|IMX_URXD_BRK|IMX_URXD_FRMERR|IMX_URXD_OVRRUN) 1653 1654 while (cc) { 1655 data = sc->sc_rbuf[outp]; 1656 code = data & IMX_URXD_RX_DATA; 1657 if (ISSET(data, ERRBITS)) { 1658 if (sc->sc_errors.err == 0) 1659 callout_reset(&sc->sc_diag_callout, 1660 60 * hz, imxudiag, sc); 1661 if (ISSET(data, IMX_URXD_OVRRUN)) 1662 sc->sc_errors.ovrrun++; 1663 if (ISSET(data, IMX_URXD_BRK)) { 1664 sc->sc_errors.brk++; 1665 SET(code, TTY_FE); 1666 } 1667 if (ISSET(data, IMX_URXD_FRMERR)) { 1668 sc->sc_errors.frmerr++; 1669 SET(code, TTY_FE); 1670 } 1671 if (ISSET(data, IMX_URXD_PRERR)) { 1672 sc->sc_errors.prerr++; 1673 SET(code, TTY_PE); 1674 } 1675 } 1676 if ((*rint)(code, tp) == -1) { 1677 /* 1678 * The line discipline's buffer is out of space. 1679 */ 1680 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) { 1681 /* 1682 * We're either not using flow control, or the 1683 * line discipline didn't tell us to block for 1684 * some reason. Either way, we have no way to 1685 * know when there's more space available, so 1686 * just drop the rest of the data. 1687 */ 1688 sc->sc_rbuf_out = sc->sc_rbuf_in; 1689 cc = 0; 1690 } else { 1691 /* 1692 * Don't schedule any more receive processing 1693 * until the line discipline tells us there's 1694 * space available (through imxuhwiflow()). 1695 * Leave the rest of the data in the input 1696 * buffer. 1697 */ 1698 SET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED); 1699 } 1700 break; 1701 } 1702 outp = IMXUART_RBUF_INC(sc, outp, 1); 1703 cc--; 1704 } 1705 1706 if (cc != scc) { 1707 sc->sc_rbuf_out = outp; 1708 mutex_spin_enter(&sc->sc_lock); 1709 1710 cc = IMXUART_RBUF_SPACE(sc); 1711 1712 /* Buffers should be ok again, release possible block. */ 1713 if (cc >= sc->sc_r_lowat) { 1714 if (ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_OVERFLOWED)) { 1715 CLR(sc->sc_rx_flags, IMXUART_RX_IBUF_OVERFLOWED); 1716 imxuart_control_rxint(sc, true); 1717 } 1718 if (ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED)) { 1719 CLR(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED); 1720 imxuart_hwiflow(sc); 1721 } 1722 } 1723 mutex_spin_exit(&sc->sc_lock); 1724 } 1725 } 1726 1727 integrate void 1728 imxuart_txsoft(struct imxuart_softc *sc, struct tty *tp) 1729 { 1730 1731 CLR(tp->t_state, TS_BUSY); 1732 if (ISSET(tp->t_state, TS_FLUSH)) 1733 CLR(tp->t_state, TS_FLUSH); 1734 else 1735 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1736 (*tp->t_linesw->l_start)(tp); 1737 } 1738 1739 integrate void 1740 imxuart_stsoft(struct imxuart_softc *sc, struct tty *tp) 1741 { 1742 #ifdef notyet 1743 u_char msr, delta; 1744 1745 mutex_spin_enter(&sc->sc_lock); 1746 msr = sc->sc_msr; 1747 delta = sc->sc_msr_delta; 1748 sc->sc_msr_delta = 0; 1749 mutex_spin_exit(&sc->sc_lock); 1750 1751 if (ISSET(delta, sc->sc_msr_dcd)) { 1752 /* 1753 * Inform the tty layer that carrier detect changed. 1754 */ 1755 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1756 } 1757 1758 if (ISSET(delta, sc->sc_msr_cts)) { 1759 /* Block or unblock output according to flow control. */ 1760 if (ISSET(msr, sc->sc_msr_cts)) { 1761 sc->sc_tx_stopped = 0; 1762 (*tp->t_linesw->l_start)(tp); 1763 } else { 1764 sc->sc_tx_stopped = 1; 1765 } 1766 } 1767 1768 #endif 1769 #ifdef IMXUART_DEBUG 1770 if (imxuart_debug) 1771 imxustatus(sc, "imxuart_stsoft"); 1772 #endif 1773 } 1774 1775 void 1776 imxusoft(void *arg) 1777 { 1778 struct imxuart_softc *sc = arg; 1779 struct tty *tp; 1780 1781 if (IMXUART_ISALIVE(sc) == 0) 1782 return; 1783 1784 tp = sc->sc_tty; 1785 1786 if (sc->sc_rx_ready) { 1787 sc->sc_rx_ready = 0; 1788 imxuart_rxsoft(sc, tp); 1789 } 1790 1791 if (sc->sc_st_check) { 1792 sc->sc_st_check = 0; 1793 imxuart_stsoft(sc, tp); 1794 } 1795 1796 if (sc->sc_tx_done) { 1797 sc->sc_tx_done = 0; 1798 imxuart_txsoft(sc, tp); 1799 } 1800 } 1801 1802 int 1803 imxuintr(void *arg) 1804 { 1805 struct imxuart_softc *sc = arg; 1806 uint32_t usr1, usr2; 1807 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1808 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1809 1810 1811 if (IMXUART_ISALIVE(sc) == 0) 1812 return (0); 1813 1814 mutex_spin_enter(&sc->sc_lock); 1815 1816 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1817 1818 1819 do { 1820 bus_space_write_4(iot, ioh, IMX_USR2, 1821 usr2 & (IMX_USR2_BRCD|IMX_USR2_ORE)); 1822 if (usr2 & IMX_USR2_BRCD) { 1823 /* Break signal detected */ 1824 int cn_trapped = 0; 1825 1826 cn_check_magic(sc->sc_tty->t_dev, 1827 CNC_BREAK, imxuart_cnm_state); 1828 if (cn_trapped) 1829 continue; 1830 #if defined(KGDB) && !defined(DDB) 1831 if (ISSET(sc->sc_hwflags, IMXUART_HW_KGDB)) { 1832 kgdb_connect(1); 1833 continue; 1834 } 1835 #endif 1836 } 1837 1838 if (usr2 & IMX_USR2_RDR) 1839 imxuintr_read(sc); 1840 1841 #ifdef IMXUART_PPS 1842 { 1843 u_char msr, delta; 1844 1845 msr = CSR_READ_1(regsp, IMXUART_REG_MSR); 1846 delta = msr ^ sc->sc_msr; 1847 sc->sc_msr = msr; 1848 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 1849 (delta & MSR_DCD)) { 1850 mutex_spin_enter(&timecounter_lock); 1851 pps_capture(&sc->sc_pps_state); 1852 pps_event(&sc->sc_pps_state, 1853 (msr & MSR_DCD) ? 1854 PPS_CAPTUREASSERT : 1855 PPS_CAPTURECLEAR); 1856 mutex_spin_exit(&timecounter_lock); 1857 } 1858 } 1859 #endif 1860 1861 #ifdef notyet 1862 /* 1863 * Process normal status changes 1864 */ 1865 if (ISSET(delta, sc->sc_msr_mask)) { 1866 SET(sc->sc_msr_delta, delta); 1867 1868 /* 1869 * Stop output immediately if we lose the output 1870 * flow control signal or carrier detect. 1871 */ 1872 if (ISSET(~msr, sc->sc_msr_mask)) { 1873 sc->sc_tbc = 0; 1874 sc->sc_heldtbc = 0; 1875 #ifdef IMXUART_DEBUG 1876 if (imxuart_debug) 1877 imxustatus(sc, "imxuintr "); 1878 #endif 1879 } 1880 1881 sc->sc_st_check = 1; 1882 } 1883 #endif 1884 1885 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1886 } while (usr2 & (IMX_USR2_RDR|IMX_USR2_BRCD)); 1887 1888 usr1 = bus_space_read_4(iot, ioh, IMX_USR1); 1889 if (usr1 & IMX_USR1_TRDY) 1890 imxuintr_send(sc); 1891 1892 mutex_spin_exit(&sc->sc_lock); 1893 1894 /* Wake up the poller. */ 1895 softint_schedule(sc->sc_si); 1896 1897 #ifdef RND_COM 1898 rnd_add_uint32(&sc->rnd_source, iir | lsr); 1899 #endif 1900 1901 return (1); 1902 } 1903 1904 1905 /* 1906 * called when there is least one character in rxfifo 1907 * 1908 */ 1909 1910 static void 1911 imxuintr_read(struct imxuart_softc *sc) 1912 { 1913 int cc; 1914 uint16_t rd; 1915 uint32_t usr2; 1916 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1917 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1918 1919 cc = IMXUART_RBUF_SPACE(sc); 1920 1921 /* clear aging timer interrupt */ 1922 bus_space_write_4(iot, ioh, IMX_USR1, IMX_USR1_AGTIM); 1923 1924 while (cc > 0) { 1925 int cn_trapped = 0; 1926 1927 1928 sc->sc_rbuf[sc->sc_rbuf_in] = rd = 1929 bus_space_read_4(iot, ioh, IMX_URXD); 1930 1931 cn_check_magic(sc->sc_tty->t_dev, 1932 rd & 0xff, imxuart_cnm_state); 1933 1934 if (!cn_trapped) { 1935 #if defined(DDB) && defined(DDB_KEYCODE) 1936 /* 1937 * Temporary hack so that I can force the kernel into 1938 * the debugger via the serial port 1939 */ 1940 if ((rd & 0xff) == DDB_KEYCODE) 1941 Debugger(); 1942 #endif 1943 sc->sc_rbuf_in = IMXUART_RBUF_INC(sc, sc->sc_rbuf_in, 1); 1944 cc--; 1945 } 1946 1947 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1948 if (!(usr2 & IMX_USR2_RDR)) 1949 break; 1950 } 1951 1952 /* 1953 * Current string of incoming characters ended because 1954 * no more data was available or we ran out of space. 1955 * Schedule a receive event if any data was received. 1956 * If we're out of space, turn off receive interrupts. 1957 */ 1958 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED)) 1959 sc->sc_rx_ready = 1; 1960 /* 1961 * See if we are in danger of overflowing a buffer. If 1962 * so, use hardware flow control to ease the pressure. 1963 */ 1964 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED) && 1965 cc < sc->sc_r_hiwat) { 1966 sc->sc_rx_flags |= IMXUART_RX_IBUF_BLOCKED; 1967 imxuart_hwiflow(sc); 1968 } 1969 1970 /* 1971 * If we're out of space, disable receive interrupts 1972 * until the queue has drained a bit. 1973 */ 1974 if (!cc) { 1975 sc->sc_rx_flags |= IMXUART_RX_IBUF_OVERFLOWED; 1976 imxuart_control_rxint(sc, false); 1977 } 1978 } 1979 1980 1981 1982 /* 1983 * find how many chars we can put into tx-fifo 1984 */ 1985 static u_int 1986 imxuart_txfifo_space(struct imxuart_softc *sc) 1987 { 1988 uint32_t usr1, usr2; 1989 u_int cc; 1990 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1991 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1992 1993 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1994 if (usr2 & IMX_USR2_TXFE) 1995 cc = sc->sc_txfifo_len; 1996 else { 1997 usr1 = bus_space_read_4(iot, ioh, IMX_USR1); 1998 if (usr1 & IMX_USR1_TRDY) 1999 cc = sc->sc_txfifo_thresh; 2000 else 2001 cc = 0; 2002 } 2003 2004 return cc; 2005 } 2006 2007 void 2008 imxuintr_send(struct imxuart_softc *sc) 2009 { 2010 uint32_t usr2; 2011 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2012 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2013 int cc = 0; 2014 2015 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 2016 2017 if (sc->sc_pending) { 2018 if (usr2 & IMX_USR2_TXFE) { 2019 imxuart_load_pendings(sc); 2020 sc->sc_tbc = sc->sc_heldtbc; 2021 sc->sc_heldtbc = 0; 2022 } 2023 else { 2024 /* wait for TX fifo empty */ 2025 imxuart_control_txint(sc, true); 2026 return; 2027 } 2028 } 2029 2030 cc = imxuart_txfifo_space(sc); 2031 cc = MIN(cc, sc->sc_tbc); 2032 2033 if (cc > 0) { 2034 bus_space_write_multi_1(iot, ioh, IMX_UTXD, sc->sc_tba, cc); 2035 sc->sc_tbc -= cc; 2036 sc->sc_tba += cc; 2037 } 2038 2039 if (sc->sc_tbc > 0) 2040 imxuart_control_txint(sc, true); 2041 else { 2042 /* no more chars to send. 2043 we don't need tx interrupt any more. */ 2044 imxuart_control_txint(sc, false); 2045 if (sc->sc_tx_busy) { 2046 sc->sc_tx_busy = 0; 2047 sc->sc_tx_done = 1; 2048 } 2049 } 2050 } 2051 2052 static void 2053 imxuart_disable_all_interrupts(struct imxuart_softc *sc) 2054 { 2055 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2056 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2057 2058 sc->sc_ucr1 &= ~IMXUART_INTRS_UCR1; 2059 sc->sc_ucr2 &= ~IMXUART_INTRS_UCR2; 2060 sc->sc_ucr3 &= ~IMXUART_INTRS_UCR3; 2061 sc->sc_ucr4 &= ~IMXUART_INTRS_UCR4; 2062 2063 2064 bus_space_write_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 4); 2065 } 2066 2067 static void 2068 imxuart_control_rxint(struct imxuart_softc *sc, bool enable) 2069 { 2070 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2071 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2072 uint32_t ucr1, ucr2; 2073 2074 ucr1 = sc->sc_ucr1; 2075 ucr2 = sc->sc_ucr2; 2076 2077 if (enable) { 2078 ucr1 |= IMX_UCR1_RRDYEN; 2079 ucr2 |= IMX_UCR2_ATEN; 2080 } 2081 else { 2082 ucr1 &= ~IMX_UCR1_RRDYEN; 2083 ucr2 &= ~IMX_UCR2_ATEN; 2084 } 2085 2086 if (ucr1 != sc->sc_ucr1 || ucr2 != sc->sc_ucr2) { 2087 sc->sc_ucr1 = ucr1; 2088 sc->sc_ucr2 = ucr2; 2089 bus_space_write_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 2); 2090 } 2091 } 2092 2093 static void 2094 imxuart_control_txint(struct imxuart_softc *sc, bool enable) 2095 { 2096 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2097 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2098 uint32_t ucr1; 2099 uint32_t mask; 2100 2101 /* if parameter change is pending, get interrupt when Tx fifo 2102 is completely empty. otherwise, get interrupt when txfifo 2103 has less characters than threshold */ 2104 mask = sc->sc_pending ? IMX_UCR1_TXMPTYEN : IMX_UCR1_TRDYEN; 2105 2106 ucr1 = sc->sc_ucr1; 2107 2108 CLR(ucr1, IMX_UCR1_TXMPTYEN|IMX_UCR1_TRDYEN); 2109 if (enable) 2110 SET(ucr1, mask); 2111 2112 if (ucr1 != sc->sc_ucr1) { 2113 bus_space_write_4(iot, ioh, IMX_UCR1, ucr1); 2114 sc->sc_ucr1 = ucr1; 2115 } 2116 } 2117 2118 2119 static void 2120 imxuart_load_params(struct imxuart_softc *sc) 2121 { 2122 uint32_t ucr2; 2123 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2124 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2125 2126 ucr2 = (sc->sc_ucr2_d & ~IMX_UCR2_ATEN) | 2127 (sc->sc_ucr2 & IMX_UCR2_ATEN); 2128 2129 bus_space_write_4(iot, ioh, IMX_UCR2, ucr2); 2130 sc->sc_ucr2 = ucr2; 2131 } 2132 2133 static void 2134 imxuart_load_speed(struct imxuart_softc *sc) 2135 { 2136 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2137 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2138 int n, rfdiv, ufcr; 2139 2140 #ifdef notyet 2141 /* 2142 * Set the FIFO threshold based on the receive speed. 2143 * 2144 * * If it's a low speed, it's probably a mouse or some other 2145 * interactive device, so set the threshold low. 2146 * * If it's a high speed, trim the trigger level down to prevent 2147 * overflows. 2148 * * Otherwise set it a bit higher. 2149 */ 2150 if (t->c_ospeed <= 1200) 2151 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 2152 else if (t->c_ospeed <= 38400) 2153 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 2154 else 2155 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 2156 #endif 2157 2158 n = 32 - sc->sc_txfifo_thresh; 2159 n = MAX(2, n); 2160 2161 rfdiv = IMX_UFCR_DIVIDER_TO_RFDIV(imxuart_freqdiv); 2162 2163 ufcr = (n << IMX_UFCR_TXTL_SHIFT) | 2164 (rfdiv << IMX_UFCR_RFDIV_SHIFT) | 2165 (16 << IMX_UFCR_RXTL_SHIFT); 2166 2167 /* keep DCE/DTE bit */ 2168 ufcr |= bus_space_read_4(iot, ioh, IMX_UFCR) & IMX_UFCR_DCEDTE; 2169 2170 bus_space_write_4(iot, ioh, IMX_UFCR, ufcr); 2171 2172 /* UBIR must updated before UBMR */ 2173 bus_space_write_4(iot, ioh, 2174 IMX_UBIR, sc->sc_ratio.numerator); 2175 bus_space_write_4(iot, ioh, 2176 IMX_UBMR, sc->sc_ratio.modulator); 2177 2178 2179 } 2180 2181 2182 static void 2183 imxuart_load_pendings(struct imxuart_softc *sc) 2184 { 2185 if (sc->sc_pending & IMXUART_PEND_PARAM) 2186 imxuart_load_params(sc); 2187 if (sc->sc_pending & IMXUART_PEND_SPEED) 2188 imxuart_load_speed(sc); 2189 sc->sc_pending = 0; 2190 } 2191 2192 #if defined(IMXUARTCONSOLE) || defined(KGDB) 2193 2194 /* 2195 * The following functions are polled getc and putc routines, shared 2196 * by the console and kgdb glue. 2197 * 2198 * The read-ahead code is so that you can detect pending in-band 2199 * cn_magic in polled mode while doing output rather than having to 2200 * wait until the kernel decides it needs input. 2201 */ 2202 2203 #define READAHEAD_RING_LEN 16 2204 static int imxuart_readahead[READAHEAD_RING_LEN]; 2205 static int imxuart_readahead_in = 0; 2206 static int imxuart_readahead_out = 0; 2207 #define READAHEAD_IS_EMPTY() (imxuart_readahead_in==imxuart_readahead_out) 2208 #define READAHEAD_IS_FULL() \ 2209 (((imxuart_readahead_in+1) & (READAHEAD_RING_LEN-1)) ==imxuart_readahead_out) 2210 2211 int 2212 imxuart_common_getc(dev_t dev, struct imxuart_regs *regsp) 2213 { 2214 int s = splserial(); 2215 u_char c; 2216 bus_space_tag_t iot = regsp->ur_iot; 2217 bus_space_handle_t ioh = regsp->ur_ioh; 2218 uint32_t usr2; 2219 2220 /* got a character from reading things earlier */ 2221 if (imxuart_readahead_in != imxuart_readahead_out) { 2222 2223 c = imxuart_readahead[imxuart_readahead_out]; 2224 imxuart_readahead_out = (imxuart_readahead_out + 1) & 2225 (READAHEAD_RING_LEN-1); 2226 splx(s); 2227 return (c); 2228 } 2229 2230 /* block until a character becomes available */ 2231 while (!((usr2 = bus_space_read_4(iot, ioh, IMX_USR2)) & IMX_USR2_RDR)) 2232 ; 2233 2234 c = 0xff & bus_space_read_4(iot, ioh, IMX_URXD); 2235 2236 { 2237 int __attribute__((__unused__))cn_trapped = 0; /* unused */ 2238 #ifdef DDB 2239 extern int db_active; 2240 if (!db_active) 2241 #endif 2242 cn_check_magic(dev, c, imxuart_cnm_state); 2243 } 2244 splx(s); 2245 return (c); 2246 } 2247 2248 void 2249 imxuart_common_putc(dev_t dev, struct imxuart_regs *regsp, int c) 2250 { 2251 int s = splserial(); 2252 int cin, timo; 2253 bus_space_tag_t iot = regsp->ur_iot; 2254 bus_space_handle_t ioh = regsp->ur_ioh; 2255 uint32_t usr2; 2256 2257 if (!READAHEAD_IS_FULL() && 2258 ((usr2 = bus_space_read_4(iot, ioh, IMX_USR2)) & IMX_USR2_RDR)) { 2259 2260 int __attribute__((__unused__))cn_trapped = 0; 2261 cin = bus_space_read_4(iot, ioh, IMX_URXD); 2262 cn_check_magic(dev, cin & 0xff, imxuart_cnm_state); 2263 imxuart_readahead_in = (imxuart_readahead_in + 1) & 2264 (READAHEAD_RING_LEN-1); 2265 } 2266 2267 /* wait for any pending transmission to finish */ 2268 timo = 150000; 2269 do { 2270 if (bus_space_read_4(iot, ioh, IMX_USR1) & IMX_USR1_TRDY) { 2271 bus_space_write_4(iot, ioh, IMX_UTXD, c); 2272 break; 2273 } 2274 } while(--timo > 0); 2275 2276 IMXUART_BARRIER(regsp, BR | BW); 2277 2278 splx(s); 2279 } 2280 2281 /* 2282 * Initialize UART for use as console or KGDB line. 2283 */ 2284 int 2285 imxuart_init(struct imxuart_regs *regsp, int rate, tcflag_t cflag) 2286 { 2287 struct imxuart_baudrate_ratio ratio; 2288 int rfdiv = IMX_UFCR_DIVIDER_TO_RFDIV(imxuart_freqdiv); 2289 uint32_t ufcr; 2290 2291 if (bus_space_map(regsp->ur_iot, regsp->ur_iobase, IMX_UART_SIZE, 0, 2292 ®sp->ur_ioh)) 2293 return ENOMEM; /* ??? */ 2294 2295 if (imxuspeed(rate, &ratio) < 0) 2296 return EINVAL; 2297 2298 /* UBIR must updated before UBMR */ 2299 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, 2300 IMX_UBIR, ratio.numerator); 2301 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, 2302 IMX_UBMR, ratio.modulator); 2303 2304 2305 /* XXX: DTREN, DPEC */ 2306 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR3, 2307 IMX_UCR3_DSR|IMX_UCR3_RXDMUXSEL); 2308 2309 ufcr = (8 << IMX_UFCR_TXTL_SHIFT) | (rfdiv << IMX_UFCR_RFDIV_SHIFT) | 2310 (1 << IMX_UFCR_RXTL_SHIFT); 2311 /* XXX: keep DCE/DTE bit */ 2312 ufcr |= bus_space_read_4(regsp->ur_iot, regsp->ur_ioh, IMX_UFCR) & 2313 IMX_UFCR_DCEDTE; 2314 2315 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UFCR, ufcr); 2316 2317 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_ONEMS, 2318 imxuart_freq / imxuart_freqdiv / 1000); 2319 2320 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR2, 2321 IMX_UCR2_IRTS| 2322 IMX_UCR2_CTSC| 2323 IMX_UCR2_WS|IMX_UCR2_TXEN| 2324 IMX_UCR2_RXEN|IMX_UCR2_SRST); 2325 /* clear status registers */ 2326 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_USR1, 0xffff); 2327 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_USR2, 0xffff); 2328 2329 2330 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR1, 2331 IMX_UCR1_UARTEN); 2332 2333 return (0); 2334 } 2335 2336 2337 #endif 2338 2339 2340 #ifdef IMXUARTCONSOLE 2341 /* 2342 * Following are all routines needed for UART to act as console 2343 */ 2344 struct consdev imxucons = { 2345 NULL, NULL, imxucngetc, imxucnputc, imxucnpollc, NULL, NULL, NULL, 2346 NODEV, CN_NORMAL 2347 }; 2348 2349 2350 int 2351 imxuart_cons_attach(bus_space_tag_t iot, paddr_t iobase, u_int rate, 2352 tcflag_t cflag) 2353 { 2354 struct imxuart_regs regs; 2355 int res; 2356 2357 regs.ur_iot = iot; 2358 regs.ur_iobase = iobase; 2359 2360 res = imxuart_init(®s, rate, cflag); 2361 if (res) 2362 return (res); 2363 2364 cn_tab = &imxucons; 2365 cn_init_magic(&imxuart_cnm_state); 2366 cn_set_magic("\047\001"); /* default magic is BREAK */ 2367 2368 imxuconsrate = rate; 2369 imxuconscflag = cflag; 2370 2371 imxuconsregs = regs; 2372 2373 return 0; 2374 } 2375 2376 int 2377 imxucngetc(dev_t dev) 2378 { 2379 return (imxuart_common_getc(dev, &imxuconsregs)); 2380 } 2381 2382 /* 2383 * Console kernel output character routine. 2384 */ 2385 void 2386 imxucnputc(dev_t dev, int c) 2387 { 2388 imxuart_common_putc(dev, &imxuconsregs, c); 2389 } 2390 2391 void 2392 imxucnpollc(dev_t dev, int on) 2393 { 2394 2395 imxuart_readahead_in = 0; 2396 imxuart_readahead_out = 0; 2397 } 2398 2399 #endif /* IMXUARTCONSOLE */ 2400 2401 #ifdef KGDB 2402 int 2403 imxuart_kgdb_attach(bus_space_tag_t iot, paddr_t iobase, u_int rate, 2404 tcflag_t cflag) 2405 { 2406 int res; 2407 2408 if (iot == imxuconsregs.ur_iot && 2409 iobase == imxuconsregs.ur_iobase) { 2410 #if !defined(DDB) 2411 return (EBUSY); /* cannot share with console */ 2412 #else 2413 imxu_kgdb_regs.ur_iot = iot; 2414 imxu_kgdb_regs.ur_ioh = imxuconsregs.ur_ioh; 2415 imxu_kgdb_regs.ur_iobase = iobase; 2416 #endif 2417 } else { 2418 imxu_kgdb_regs.ur_iot = iot; 2419 imxu_kgdb_regs.ur_iobase = iobase; 2420 2421 res = imxuart_init(&imxu_kgdb_regs, rate, cflag); 2422 if (res) 2423 return (res); 2424 2425 /* 2426 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2427 * expects this to be initialized 2428 */ 2429 cn_init_magic(&imxuart_cnm_state); 2430 cn_set_magic("\047\001"); 2431 } 2432 2433 kgdb_attach(imxuart_kgdb_getc, imxuart_kgdb_putc, &imxu_kgdb_regs); 2434 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2435 2436 return (0); 2437 } 2438 2439 /* ARGSUSED */ 2440 int 2441 imxuart_kgdb_getc(void *arg) 2442 { 2443 struct imxuart_regs *regs = arg; 2444 2445 return (imxuart_common_getc(NODEV, regs)); 2446 } 2447 2448 /* ARGSUSED */ 2449 void 2450 imxuart_kgdb_putc(void *arg, int c) 2451 { 2452 struct imxuart_regs *regs = arg; 2453 2454 imxuart_common_putc(NODEV, regs, c); 2455 } 2456 #endif /* KGDB */ 2457 2458 /* helper function to identify the imxu ports used by 2459 console or KGDB (and not yet autoconf attached) */ 2460 int 2461 imxuart_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2462 { 2463 bus_space_handle_t help; 2464 2465 if (!imxuconsattached && 2466 iot == imxuconsregs.ur_iot && iobase == imxuconsregs.ur_iobase) 2467 help = imxuconsregs.ur_ioh; 2468 #ifdef KGDB 2469 else if (!imxu_kgdb_attached && 2470 iot == imxu_kgdb_regs.ur_iot && iobase == imxu_kgdb_regs.ur_iobase) 2471 help = imxu_kgdb_regs.ur_ioh; 2472 #endif 2473 else 2474 return (0); 2475 2476 if (ioh) 2477 *ioh = help; 2478 return (1); 2479 } 2480 2481 #ifdef notyet 2482 2483 bool 2484 imxuart_cleanup(device_t self, int how) 2485 { 2486 /* 2487 * this routine exists to serve as a shutdown hook for systems that 2488 * have firmware which doesn't interact properly with a imxuart device in 2489 * FIFO mode. 2490 */ 2491 struct imxuart_softc *sc = device_private(self); 2492 2493 if (ISSET(sc->sc_hwflags, IMXUART_HW_FIFO)) 2494 UR_WRITE_1(&sc->sc_regs, IMXUART_REG_FIFO, 0); 2495 2496 return true; 2497 } 2498 #endif 2499 2500 #ifdef notyet 2501 bool 2502 imxuart_suspend(device_t self PMF_FN_ARGS) 2503 { 2504 struct imxuart_softc *sc = device_private(self); 2505 2506 UR_WRITE_1(&sc->sc_regs, IMXUART_REG_IER, 0); 2507 (void)CSR_READ_1(&sc->sc_regs, IMXUART_REG_IIR); 2508 2509 return true; 2510 } 2511 #endif 2512 2513 #ifdef notyet 2514 bool 2515 imxuart_resume(device_t self PMF_FN_ARGS) 2516 { 2517 struct imxuart_softc *sc = device_private(self); 2518 2519 mutex_spin_enter(&sc->sc_lock); 2520 imxuart_loadchannelregs(sc); 2521 mutex_spin_exit(&sc->sc_lock); 2522 2523 return true; 2524 } 2525 #endif 2526 2527 static void 2528 imxuart_enable_debugport(struct imxuart_softc *sc) 2529 { 2530 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2531 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2532 2533 if (sc->sc_hwflags & (IMXUART_HW_CONSOLE|IMXUART_HW_KGDB)) { 2534 2535 /* Turn on line break interrupt, set carrier. */ 2536 2537 sc->sc_ucr3 |= IMX_UCR3_DSR; 2538 bus_space_write_4(iot, ioh, IMX_UCR3, sc->sc_ucr3); 2539 2540 sc->sc_ucr4 |= IMX_UCR4_BKEN; 2541 bus_space_write_4(iot, ioh, IMX_UCR4, sc->sc_ucr4); 2542 2543 sc->sc_ucr2 |= IMX_UCR2_TXEN|IMX_UCR2_RXEN| 2544 IMX_UCR2_CTS; 2545 bus_space_write_4(iot, ioh, IMX_UCR2, sc->sc_ucr2); 2546 2547 sc->sc_ucr1 |= IMX_UCR1_UARTEN; 2548 bus_space_write_4(iot, ioh, IMX_UCR1, sc->sc_ucr1); 2549 } 2550 } 2551 2552 2553 void 2554 imxuart_set_frequency(u_int freq, u_int div) 2555 { 2556 imxuart_freq = freq; 2557 imxuart_freqdiv = div; 2558 } 2559
Indexes created Mon Sep 29 21:09:56 GMT 2025