imxuart.c revision 1.16.2.2
1 /* $NetBSD: imxuart.c,v 1.16.2.2 2015/09/22 12:05:37 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2009, 2010 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* 31 * derived from sys/dev/ic/com.c 32 */ 33 34 /*- 35 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to The NetBSD Foundation 39 * by Charles M. Hannum. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 51 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 52 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 53 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 60 * POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Copyright (c) 1991 The Regents of the University of California. 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 3. Neither the name of the University nor the names of its contributors 76 * may be used to endorse or promote products derived from this software 77 * without specific prior written permission. 78 * 79 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 80 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 82 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 85 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 86 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 87 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 88 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 89 * SUCH DAMAGE. 90 * 91 * @(#)com.c 7.5 (Berkeley) 5/16/91 92 */ 93 94 /* 95 * driver for UART in i.MX SoC. 96 */ 97 98 #include <sys/cdefs.h> 99 __KERNEL_RCSID(0, "$NetBSD: imxuart.c,v 1.16.2.2 2015/09/22 12:05:37 skrll Exp $"); 100 101 #include "opt_imxuart.h" 102 #include "opt_ddb.h" 103 #include "opt_ddbparam.h" 104 #include "opt_kgdb.h" 105 #include "opt_lockdebug.h" 106 #include "opt_multiprocessor.h" 107 #include "opt_ntp.h" 108 #include "opt_imxuart.h" 109 #include "opt_imx.h" 110 111 #ifdef RND_COM 112 #include <sys/rndsource.h> 113 #endif 114 115 #ifndef IMXUART_TOLERANCE 116 #define IMXUART_TOLERANCE 30 /* baud rate tolerance, in 0.1% units */ 117 #endif 118 119 #ifndef IMXUART_FREQDIV 120 #define IMXUART_FREQDIV 2 /* XXX */ 121 #endif 122 123 #ifndef IMXUART_FREQ 124 #define IMXUART_FREQ (56900000) 125 #endif 126 127 /* 128 * Override cnmagic(9) macro before including <sys/systm.h>. 129 * We need to know if cn_check_magic triggered debugger, so set a flag. 130 * Callers of cn_check_magic must declare int cn_trapped = 0; 131 * XXX: this is *ugly*! 132 */ 133 #define cn_trap() \ 134 do { \ 135 console_debugger(); \ 136 cn_trapped = 1; \ 137 } while (/* CONSTCOND */ 0) 138 139 #include <sys/param.h> 140 #include <sys/systm.h> 141 #include <sys/ioctl.h> 142 #include <sys/select.h> 143 #include <sys/poll.h> 144 #include <sys/tty.h> 145 #include <sys/proc.h> 146 #include <sys/conf.h> 147 #include <sys/file.h> 148 #include <sys/uio.h> 149 #include <sys/kernel.h> 150 #include <sys/syslog.h> 151 #include <sys/device.h> 152 #include <sys/malloc.h> 153 #include <sys/timepps.h> 154 #include <sys/vnode.h> 155 #include <sys/kauth.h> 156 #include <sys/intr.h> 157 158 #include <sys/bus.h> 159 160 #include <arm/imx/imxuartreg.h> 161 #include <arm/imx/imxuartvar.h> 162 #include <dev/cons.h> 163 164 #ifndef IMXUART_RING_SIZE 165 #define IMXUART_RING_SIZE 2048 166 #endif 167 168 typedef struct imxuart_softc { 169 device_t sc_dev; 170 171 struct imxuart_regs { 172 bus_space_tag_t ur_iot; 173 bus_space_handle_t ur_ioh; 174 bus_addr_t ur_iobase; 175 #if 0 176 bus_size_t ur_nports; 177 bus_size_t ur_map[16]; 178 #endif 179 } sc_regs; 180 181 #define sc_bt sc_regs.ur_iot 182 #define sc_bh sc_regs.ur_ioh 183 184 uint32_t sc_intrspec_enb; 185 uint32_t sc_ucr2_d; /* target value for UCR2 */ 186 uint32_t sc_ucr[4]; /* cached value of UCRn */ 187 #define sc_ucr1 sc_ucr[0] 188 #define sc_ucr2 sc_ucr[1] 189 #define sc_ucr3 sc_ucr[2] 190 #define sc_ucr4 sc_ucr[3] 191 192 uint sc_init_cnt; 193 194 bus_addr_t sc_addr; 195 bus_size_t sc_size; 196 int sc_intr; 197 198 u_char sc_hwflags; 199 /* Hardware flag masks */ 200 #define IMXUART_HW_FLOW __BIT(0) 201 #define IMXUART_HW_DEV_OK __BIT(1) 202 #define IMXUART_HW_CONSOLE __BIT(2) 203 #define IMXUART_HW_KGDB __BIT(3) 204 205 206 bool enabled; 207 208 u_char sc_swflags; 209 210 u_char sc_rx_flags; 211 #define IMXUART_RX_TTY_BLOCKED __BIT(0) 212 #define IMXUART_RX_TTY_OVERFLOWED __BIT(1) 213 #define IMXUART_RX_IBUF_BLOCKED __BIT(2) 214 #define IMXUART_RX_IBUF_OVERFLOWED __BIT(3) 215 #define IMXUART_RX_ANY_BLOCK \ 216 (IMXUART_RX_TTY_BLOCKED|IMXUART_RX_TTY_OVERFLOWED| \ 217 IMXUART_RX_IBUF_BLOCKED|IMXUART_RX_IBUF_OVERFLOWED) 218 219 bool sc_tx_busy, sc_tx_done, sc_tx_stopped; 220 bool sc_rx_ready,sc_st_check; 221 u_short sc_txfifo_len, sc_txfifo_thresh; 222 223 uint16_t *sc_rbuf; 224 u_int sc_rbuf_size; 225 u_int sc_rbuf_in; 226 u_int sc_rbuf_out; 227 #define IMXUART_RBUF_AVAIL(sc) \ 228 ((sc->sc_rbuf_out <= sc->sc_rbuf_in) ? \ 229 (sc->sc_rbuf_in - sc->sc_rbuf_out) : \ 230 (sc->sc_rbuf_size - (sc->sc_rbuf_out - sc->sc_rbuf_in))) 231 232 #define IMXUART_RBUF_SPACE(sc) \ 233 ((sc->sc_rbuf_in <= sc->sc_rbuf_out ? \ 234 sc->sc_rbuf_size - (sc->sc_rbuf_out - sc->sc_rbuf_in) : \ 235 sc->sc_rbuf_in - sc->sc_rbuf_out) - 1) 236 /* increment ringbuffer pointer */ 237 #define IMXUART_RBUF_INC(sc,v,i) (((v) + (i))&((sc->sc_rbuf_size)-1)) 238 u_int sc_r_lowat; 239 u_int sc_r_hiwat; 240 241 /* output chunk */ 242 u_char *sc_tba; 243 u_int sc_tbc; 244 u_int sc_heldtbc; 245 /* pending parameter changes */ 246 u_char sc_pending; 247 #define IMXUART_PEND_PARAM __BIT(0) 248 #define IMXUART_PEND_SPEED __BIT(1) 249 250 251 struct callout sc_diag_callout; 252 kmutex_t sc_lock; 253 void *sc_ih; /* interrupt handler */ 254 void *sc_si; /* soft interrupt */ 255 struct tty *sc_tty; 256 257 /* power management hooks */ 258 int (*enable)(struct imxuart_softc *); 259 void (*disable)(struct imxuart_softc *); 260 261 struct { 262 ulong err; 263 ulong brk; 264 ulong prerr; 265 ulong frmerr; 266 ulong ovrrun; 267 } sc_errors; 268 269 struct imxuart_baudrate_ratio { 270 uint16_t numerator; /* UBIR */ 271 uint16_t modulator; /* UBMR */ 272 } sc_ratio; 273 274 } imxuart_softc_t; 275 276 277 int imxuspeed(long, struct imxuart_baudrate_ratio *); 278 int imxuparam(struct tty *, struct termios *); 279 void imxustart(struct tty *); 280 int imxuhwiflow(struct tty *, int); 281 282 void imxuart_shutdown(struct imxuart_softc *); 283 void imxuart_loadchannelregs(struct imxuart_softc *); 284 void imxuart_hwiflow(struct imxuart_softc *); 285 void imxuart_break(struct imxuart_softc *, bool); 286 void imxuart_modem(struct imxuart_softc *, int); 287 void tiocm_to_imxu(struct imxuart_softc *, u_long, int); 288 int imxuart_to_tiocm(struct imxuart_softc *); 289 void imxuart_iflush(struct imxuart_softc *); 290 int imxuintr(void *); 291 292 int imxuart_common_getc(dev_t, struct imxuart_regs *); 293 void imxuart_common_putc(dev_t, struct imxuart_regs *, int); 294 295 296 int imxuart_init(struct imxuart_regs *, int, tcflag_t, int); 297 298 int imxucngetc(dev_t); 299 void imxucnputc(dev_t, int); 300 void imxucnpollc(dev_t, int); 301 302 static void imxuintr_read(struct imxuart_softc *); 303 static void imxuintr_send(struct imxuart_softc *); 304 305 static void imxuart_enable_debugport(struct imxuart_softc *); 306 static void imxuart_disable_all_interrupts(struct imxuart_softc *); 307 static void imxuart_control_rxint(struct imxuart_softc *, bool); 308 static void imxuart_control_txint(struct imxuart_softc *, bool); 309 static u_int imxuart_txfifo_space(struct imxuart_softc *sc); 310 311 static uint32_t cflag_to_ucr2(tcflag_t, uint32_t); 312 313 CFATTACH_DECL_NEW(imxuart, sizeof(struct imxuart_softc), 314 imxuart_match, imxuart_attach, NULL, NULL); 315 316 317 #define integrate static inline 318 void imxusoft(void *); 319 integrate void imxuart_rxsoft(struct imxuart_softc *, struct tty *); 320 integrate void imxuart_txsoft(struct imxuart_softc *, struct tty *); 321 integrate void imxuart_stsoft(struct imxuart_softc *, struct tty *); 322 integrate void imxuart_schedrx(struct imxuart_softc *); 323 void imxudiag(void *); 324 static void imxuart_load_speed(struct imxuart_softc *); 325 static void imxuart_load_params(struct imxuart_softc *); 326 integrate void imxuart_load_pendings(struct imxuart_softc *); 327 328 329 extern struct cfdriver imxuart_cd; 330 331 dev_type_open(imxuopen); 332 dev_type_close(imxuclose); 333 dev_type_read(imxuread); 334 dev_type_write(imxuwrite); 335 dev_type_ioctl(imxuioctl); 336 dev_type_stop(imxustop); 337 dev_type_tty(imxutty); 338 dev_type_poll(imxupoll); 339 340 const struct cdevsw imxcom_cdevsw = { 341 .d_open = imxuopen, 342 .d_close = imxuclose, 343 .d_read = imxuread, 344 .d_write = imxuwrite, 345 .d_ioctl = imxuioctl, 346 .d_stop = imxustop, 347 .d_tty = imxutty, 348 .d_poll = imxupoll, 349 .d_mmap = nommap, 350 .d_kqfilter = ttykqfilter, 351 .d_discard = nodiscard, 352 .d_flag = D_TTY 353 }; 354 355 /* 356 * Make this an option variable one can patch. 357 * But be warned: this must be a power of 2! 358 */ 359 u_int imxuart_rbuf_size = IMXUART_RING_SIZE; 360 361 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 362 u_int imxuart_rbuf_hiwat = (IMXUART_RING_SIZE * 1) / 4; 363 u_int imxuart_rbuf_lowat = (IMXUART_RING_SIZE * 3) / 4; 364 365 static struct imxuart_regs imxuconsregs; 366 static int imxuconsattached; 367 static int imxuconsrate; 368 static tcflag_t imxuconscflag; 369 static struct cnm_state imxuart_cnm_state; 370 371 u_int imxuart_freq = IMXUART_FREQ; 372 u_int imxuart_freqdiv = IMXUART_FREQDIV; 373 374 #ifdef KGDB 375 #include <sys/kgdb.h> 376 377 static struct imxuart_regs imxu_kgdb_regs; 378 static int imxu_kgdb_attached; 379 380 int imxuart_kgdb_getc(void *); 381 void imxuart_kgdb_putc(void *, int); 382 #endif /* KGDB */ 383 384 #define IMXUART_DIALOUT_MASK TTDIALOUT_MASK 385 386 #define IMXUART_UNIT(x) TTUNIT(x) 387 #define IMXUART_DIALOUT(x) TTDIALOUT(x) 388 389 #define IMXUART_ISALIVE(sc) ((sc)->enabled != 0 && \ 390 device_is_active((sc)->sc_dev)) 391 392 #define BR BUS_SPACE_BARRIER_READ 393 #define BW BUS_SPACE_BARRIER_WRITE 394 #define IMXUART_BARRIER(r, f) \ 395 bus_space_barrier((r)->ur_iot, (r)->ur_ioh, 0, IMX_UART_SIZE, (f)) 396 397 398 void 399 imxuart_attach_common(device_t parent, device_t self, 400 bus_space_tag_t iot, paddr_t iobase, size_t size, int intr, int flags) 401 { 402 imxuart_softc_t *sc = device_private(self); 403 struct imxuart_regs *regsp = &sc->sc_regs; 404 struct tty *tp; 405 bus_space_handle_t ioh; 406 407 aprint_naive("\n"); 408 aprint_normal("\n"); 409 410 sc->sc_dev = self; 411 412 if (size <= 0) 413 size = IMX_UART_SIZE; 414 415 sc->sc_intr = intr; 416 regsp->ur_iot = iot; 417 regsp->ur_iobase = iobase; 418 419 if (bus_space_map(iot, regsp->ur_iobase, size, 0, &ioh)) { 420 return; 421 } 422 regsp->ur_ioh = ioh; 423 424 callout_init(&sc->sc_diag_callout, 0); 425 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 426 427 if (regsp->ur_iobase != imxuconsregs.ur_iobase) 428 imxuart_init(&sc->sc_regs, TTYDEF_SPEED, TTYDEF_CFLAG, false); 429 430 bus_space_read_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 4); 431 sc->sc_ucr2_d = sc->sc_ucr2; 432 433 /* Disable interrupts before configuring the device. */ 434 imxuart_disable_all_interrupts(sc); 435 436 if (regsp->ur_iobase == imxuconsregs.ur_iobase) { 437 imxuconsattached = 1; 438 439 /* Make sure the console is always "hardwired". */ 440 #if 0 441 delay(10000); /* wait for output to finish */ 442 #endif 443 SET(sc->sc_hwflags, IMXUART_HW_CONSOLE); 444 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 445 } 446 447 448 tp = tty_alloc(); 449 tp->t_oproc = imxustart; 450 tp->t_param = imxuparam; 451 tp->t_hwiflow = imxuhwiflow; 452 453 sc->sc_tty = tp; 454 sc->sc_rbuf = malloc(sizeof (*sc->sc_rbuf) * imxuart_rbuf_size, 455 M_DEVBUF, M_NOWAIT); 456 sc->sc_rbuf_size = imxuart_rbuf_size; 457 sc->sc_rbuf_in = sc->sc_rbuf_out = 0; 458 if (sc->sc_rbuf == NULL) { 459 aprint_error_dev(sc->sc_dev, 460 "unable to allocate ring buffer\n"); 461 return; 462 } 463 464 sc->sc_txfifo_len = 32; 465 sc->sc_txfifo_thresh = 16; /* when USR1.TRDY, fifo has space 466 * for this many characters */ 467 468 tty_attach(tp); 469 470 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 471 int maj; 472 473 /* locate the major number */ 474 maj = cdevsw_lookup_major(&imxcom_cdevsw); 475 476 if (maj != NODEVMAJOR) { 477 tp->t_dev = cn_tab->cn_dev = makedev(maj, 478 device_unit(sc->sc_dev)); 479 480 aprint_normal_dev(sc->sc_dev, "console\n"); 481 } 482 } 483 484 sc->sc_ih = intr_establish(sc->sc_intr, IPL_SERIAL, IST_LEVEL, 485 imxuintr, sc); 486 if (sc->sc_ih == NULL) 487 aprint_error_dev(sc->sc_dev, "intr_establish failed\n"); 488 489 #ifdef KGDB 490 /* 491 * Allow kgdb to "take over" this port. If this is 492 * not the console and is the kgdb device, it has 493 * exclusive use. If it's the console _and_ the 494 * kgdb device, it doesn't. 495 */ 496 if (regsp->ur_iobase == imxu_kgdb_regs.ur_iobase) { 497 if (!ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 498 imxu_kgdb_attached = 1; 499 500 SET(sc->sc_hwflags, IMXUART_HW_KGDB); 501 } 502 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 503 } 504 #endif 505 506 sc->sc_si = softint_establish(SOFTINT_SERIAL, imxusoft, sc); 507 508 #ifdef RND_COM 509 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 510 RND_TYPE_TTY, RND_FLAG_COLLECT_TIME | 511 RND_FLAG_ESTIMATE_TIME); 512 #endif 513 514 /* if there are no enable/disable functions, assume the device 515 is always enabled */ 516 if (!sc->enable) 517 sc->enabled = 1; 518 519 imxuart_enable_debugport(sc); 520 521 SET(sc->sc_hwflags, IMXUART_HW_DEV_OK); 522 523 //shutdownhook_establish(imxuart_shutdownhook, sc); 524 525 526 #if 0 527 { 528 uint32_t reg; 529 reg = bus_space_read_4(iot, ioh, IMX_UCR1); 530 reg |= IMX_UCR1_TXDMAEN | IMX_UCR1_RXDMAEN; 531 bus_space_write_4(iot, ioh, IMX_UCR1, reg); 532 } 533 #endif 534 } 535 536 /* 537 * baudrate = RefFreq / (16 * (UMBR + 1)/(UBIR + 1)) 538 * 539 * (UBIR + 1) / (UBMR + 1) = (16 * BaurdRate) / RefFreq 540 */ 541 542 static long 543 gcd(long m, long n) 544 { 545 546 if (m < n) 547 return gcd(n, m); 548 549 if (n <= 0) 550 return m; 551 return gcd(n, m % n); 552 } 553 554 555 int 556 imxuspeed(long speed, struct imxuart_baudrate_ratio *ratio) 557 { 558 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 559 long b = 16 * speed; 560 long f = imxuart_freq / imxuart_freqdiv; 561 long d; 562 int err = 0; 563 564 /* reduce b/f */ 565 while ((f > (1<<16) || b > (1<<16)) && (d = gcd(f, b)) > 1) { 566 f /= d; 567 b /= d; 568 } 569 570 571 while (f > (1<<16) || b > (1<<16)) { 572 f /= 2; 573 b /= 2; 574 } 575 if (f <= 0 || b <= 0) 576 return -1; 577 578 #ifdef DIAGNOSTIC 579 err = divrnd(((uint64_t)imxuart_freq) * 1000 / imxuart_freqdiv, 580 (uint64_t)speed * 16 * f / b) - 1000; 581 if (err < 0) 582 err = -err; 583 #endif 584 585 ratio->numerator = b-1; 586 ratio->modulator = f-1; 587 588 if (err > IMXUART_TOLERANCE) 589 return -1; 590 591 return 0; 592 #undef divrnd 593 } 594 595 #ifdef IMXUART_DEBUG 596 int imxuart_debug = 0; 597 598 void imxustatus(struct imxuart_softc *, const char *); 599 void 600 imxustatus(struct imxuart_softc *sc, const char *str) 601 { 602 struct tty *tp = sc->sc_tty; 603 604 aprint_normal_dev(sc->sc_dev, 605 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 606 str, 607 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 608 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 609 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 610 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 611 sc->sc_tx_stopped ? '+' : '-'); 612 613 aprint_normal_dev(sc->sc_dev, 614 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 615 str, 616 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 617 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 618 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 619 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 620 sc->sc_rx_flags); 621 } 622 #endif 623 624 #if 0 625 int 626 imxuart_detach(device_t self, int flags) 627 { 628 struct imxuart_softc *sc = device_private(self); 629 int maj, mn; 630 631 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) 632 return EBUSY; 633 634 /* locate the major number */ 635 maj = cdevsw_lookup_major(&imxcom_cdevsw); 636 637 /* Nuke the vnodes for any open instances. */ 638 mn = device_unit(self); 639 vdevgone(maj, mn, mn, VCHR); 640 641 mn |= IMXUART_DIALOUT_MASK; 642 vdevgone(maj, mn, mn, VCHR); 643 644 if (sc->sc_rbuf == NULL) { 645 /* 646 * Ring buffer allocation failed in the imxuart_attach_subr, 647 * only the tty is allocated, and nothing else. 648 */ 649 tty_free(sc->sc_tty); 650 return 0; 651 } 652 653 /* Free the receive buffer. */ 654 free(sc->sc_rbuf, M_DEVBUF); 655 656 /* Detach and free the tty. */ 657 tty_detach(sc->sc_tty); 658 tty_free(sc->sc_tty); 659 660 /* Unhook the soft interrupt handler. */ 661 softint_disestablish(sc->sc_si); 662 663 #ifdef RND_COM 664 /* Unhook the entropy source. */ 665 rnd_detach_source(&sc->rnd_source); 666 #endif 667 callout_destroy(&sc->sc_diag_callout); 668 669 /* Destroy the lock. */ 670 mutex_destroy(&sc->sc_lock); 671 672 return (0); 673 } 674 #endif 675 676 #ifdef notyet 677 int 678 imxuart_activate(device_t self, enum devact act) 679 { 680 struct imxuart_softc *sc = device_private(self); 681 int rv = 0; 682 683 switch (act) { 684 case DVACT_ACTIVATE: 685 rv = EOPNOTSUPP; 686 break; 687 688 case DVACT_DEACTIVATE: 689 if (sc->sc_hwflags & (IMXUART_HW_CONSOLE|IMXUART_HW_KGDB)) { 690 rv = EBUSY; 691 break; 692 } 693 694 if (sc->disable != NULL && sc->enabled != 0) { 695 (*sc->disable)(sc); 696 sc->enabled = 0; 697 } 698 break; 699 } 700 701 return (rv); 702 } 703 #endif 704 705 void 706 imxuart_shutdown(struct imxuart_softc *sc) 707 { 708 struct tty *tp = sc->sc_tty; 709 710 mutex_spin_enter(&sc->sc_lock); 711 712 /* If we were asserting flow control, then deassert it. */ 713 SET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED); 714 imxuart_hwiflow(sc); 715 716 /* Clear any break condition set with TIOCSBRK. */ 717 imxuart_break(sc, false); 718 719 /* 720 * Hang up if necessary. Wait a bit, so the other side has time to 721 * notice even if we immediately open the port again. 722 * Avoid tsleeping above splhigh(). 723 */ 724 if (ISSET(tp->t_cflag, HUPCL)) { 725 imxuart_modem(sc, 0); 726 mutex_spin_exit(&sc->sc_lock); 727 /* XXX will only timeout */ 728 (void) kpause(ttclos, false, hz, NULL); 729 mutex_spin_enter(&sc->sc_lock); 730 } 731 732 /* Turn off interrupts. */ 733 imxuart_disable_all_interrupts(sc); 734 /* re-enable recv interrupt for console or kgdb port */ 735 imxuart_enable_debugport(sc); 736 737 mutex_spin_exit(&sc->sc_lock); 738 739 #ifdef notyet 740 if (sc->disable) { 741 #ifdef DIAGNOSTIC 742 if (!sc->enabled) 743 panic("imxuart_shutdown: not enabled?"); 744 #endif 745 (*sc->disable)(sc); 746 sc->enabled = 0; 747 } 748 #endif 749 } 750 751 int 752 imxuopen(dev_t dev, int flag, int mode, struct lwp *l) 753 { 754 struct imxuart_softc *sc; 755 struct tty *tp; 756 int s; 757 int error; 758 759 sc = device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 760 if (sc == NULL || !ISSET(sc->sc_hwflags, IMXUART_HW_DEV_OK) || 761 sc->sc_rbuf == NULL) 762 return (ENXIO); 763 764 if (!device_is_active(sc->sc_dev)) 765 return (ENXIO); 766 767 #ifdef KGDB 768 /* 769 * If this is the kgdb port, no other use is permitted. 770 */ 771 if (ISSET(sc->sc_hwflags, IMXUART_HW_KGDB)) 772 return (EBUSY); 773 #endif 774 775 tp = sc->sc_tty; 776 777 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 778 return (EBUSY); 779 780 s = spltty(); 781 782 /* 783 * Do the following iff this is a first open. 784 */ 785 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 786 struct termios t; 787 788 tp->t_dev = dev; 789 790 791 #ifdef notyet 792 if (sc->enable) { 793 if ((*sc->enable)(sc)) { 794 splx(s); 795 aprint_error_dev(sc->sc_dev, 796 "device enable failed\n"); 797 return (EIO); 798 } 799 sc->enabled = 1; 800 } 801 #endif 802 803 mutex_spin_enter(&sc->sc_lock); 804 805 imxuart_disable_all_interrupts(sc); 806 807 /* Fetch the current modem control status, needed later. */ 808 809 #ifdef IMXUART_PPS 810 /* Clear PPS capture state on first open. */ 811 mutex_spin_enter(&timecounter_lock); 812 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 813 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 814 pps_init(&sc->sc_pps_state); 815 mutex_spin_exit(&timecounter_lock); 816 #endif 817 818 mutex_spin_exit(&sc->sc_lock); 819 820 /* 821 * Initialize the termios status to the defaults. Add in the 822 * sticky bits from TIOCSFLAGS. 823 */ 824 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 825 t.c_ospeed = imxuconsrate; 826 t.c_cflag = imxuconscflag; 827 } else { 828 t.c_ospeed = TTYDEF_SPEED; 829 t.c_cflag = TTYDEF_CFLAG; 830 } 831 t.c_ispeed = t.c_ospeed; 832 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 833 SET(t.c_cflag, CLOCAL); 834 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 835 SET(t.c_cflag, CRTSCTS); 836 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 837 SET(t.c_cflag, MDMBUF); 838 /* Make sure imxuparam() will do something. */ 839 tp->t_ospeed = 0; 840 (void) imxuparam(tp, &t); 841 tp->t_iflag = TTYDEF_IFLAG; 842 tp->t_oflag = TTYDEF_OFLAG; 843 tp->t_lflag = TTYDEF_LFLAG; 844 ttychars(tp); 845 ttsetwater(tp); 846 847 mutex_spin_enter(&sc->sc_lock); 848 849 /* 850 * Turn on DTR. We must always do this, even if carrier is not 851 * present, because otherwise we'd have to use TIOCSDTR 852 * immediately after setting CLOCAL, which applications do not 853 * expect. We always assert DTR while the device is open 854 * unless explicitly requested to deassert it. 855 */ 856 imxuart_modem(sc, 1); 857 858 /* Clear the input ring, and unblock. */ 859 sc->sc_rbuf_in = sc->sc_rbuf_out = 0; 860 imxuart_iflush(sc); 861 CLR(sc->sc_rx_flags, IMXUART_RX_ANY_BLOCK); 862 imxuart_hwiflow(sc); 863 864 /* Turn on interrupts. */ 865 imxuart_control_rxint(sc, true); 866 867 #ifdef IMXUART_DEBUG 868 if (imxuart_debug) 869 imxustatus(sc, "imxuopen "); 870 #endif 871 872 mutex_spin_exit(&sc->sc_lock); 873 } 874 875 splx(s); 876 877 #if 0 878 error = ttyopen(tp, IMXUART_DIALOUT(dev), ISSET(flag, O_NONBLOCK)); 879 #else 880 error = ttyopen(tp, 1, ISSET(flag, O_NONBLOCK)); 881 #endif 882 if (error) 883 goto bad; 884 885 error = (*tp->t_linesw->l_open)(dev, tp); 886 if (error) 887 goto bad; 888 889 return (0); 890 891 bad: 892 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 893 /* 894 * We failed to open the device, and nobody else had it opened. 895 * Clean up the state as appropriate. 896 */ 897 imxuart_shutdown(sc); 898 } 899 900 return (error); 901 } 902 903 int 904 imxuclose(dev_t dev, int flag, int mode, struct lwp *l) 905 { 906 struct imxuart_softc *sc = 907 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 908 struct tty *tp = sc->sc_tty; 909 910 /* XXX This is for cons.c. */ 911 if (!ISSET(tp->t_state, TS_ISOPEN)) 912 return (0); 913 914 (*tp->t_linesw->l_close)(tp, flag); 915 ttyclose(tp); 916 917 if (IMXUART_ISALIVE(sc) == 0) 918 return (0); 919 920 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 921 /* 922 * Although we got a last close, the device may still be in 923 * use; e.g. if this was the dialout node, and there are still 924 * processes waiting for carrier on the non-dialout node. 925 */ 926 imxuart_shutdown(sc); 927 } 928 929 return (0); 930 } 931 932 int 933 imxuread(dev_t dev, struct uio *uio, int flag) 934 { 935 struct imxuart_softc *sc = 936 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 937 struct tty *tp = sc->sc_tty; 938 939 if (IMXUART_ISALIVE(sc) == 0) 940 return (EIO); 941 942 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 943 } 944 945 int 946 imxuwrite(dev_t dev, struct uio *uio, int flag) 947 { 948 struct imxuart_softc *sc = 949 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 950 struct tty *tp = sc->sc_tty; 951 952 if (IMXUART_ISALIVE(sc) == 0) 953 return (EIO); 954 955 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 956 } 957 958 int 959 imxupoll(dev_t dev, int events, struct lwp *l) 960 { 961 struct imxuart_softc *sc = 962 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 963 struct tty *tp = sc->sc_tty; 964 965 if (IMXUART_ISALIVE(sc) == 0) 966 return (POLLHUP); 967 968 return ((*tp->t_linesw->l_poll)(tp, events, l)); 969 } 970 971 struct tty * 972 imxutty(dev_t dev) 973 { 974 struct imxuart_softc *sc = 975 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 976 struct tty *tp = sc->sc_tty; 977 978 return (tp); 979 } 980 981 int 982 imxuioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 983 { 984 struct imxuart_softc *sc; 985 struct tty *tp; 986 int error; 987 988 sc = device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 989 if (sc == NULL) 990 return ENXIO; 991 if (IMXUART_ISALIVE(sc) == 0) 992 return (EIO); 993 994 tp = sc->sc_tty; 995 996 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 997 if (error != EPASSTHROUGH) 998 return (error); 999 1000 error = ttioctl(tp, cmd, data, flag, l); 1001 if (error != EPASSTHROUGH) 1002 return (error); 1003 1004 error = 0; 1005 switch (cmd) { 1006 case TIOCSFLAGS: 1007 error = kauth_authorize_device_tty(l->l_cred, 1008 KAUTH_DEVICE_TTY_PRIVSET, tp); 1009 break; 1010 default: 1011 /* nothing */ 1012 break; 1013 } 1014 if (error) { 1015 return error; 1016 } 1017 1018 mutex_spin_enter(&sc->sc_lock); 1019 1020 switch (cmd) { 1021 case TIOCSBRK: 1022 imxuart_break(sc, true); 1023 break; 1024 1025 case TIOCCBRK: 1026 imxuart_break(sc, false); 1027 break; 1028 1029 case TIOCSDTR: 1030 imxuart_modem(sc, 1); 1031 break; 1032 1033 case TIOCCDTR: 1034 imxuart_modem(sc, 0); 1035 break; 1036 1037 case TIOCGFLAGS: 1038 *(int *)data = sc->sc_swflags; 1039 break; 1040 1041 case TIOCSFLAGS: 1042 sc->sc_swflags = *(int *)data; 1043 break; 1044 1045 case TIOCMSET: 1046 case TIOCMBIS: 1047 case TIOCMBIC: 1048 tiocm_to_imxu(sc, cmd, *(int *)data); 1049 break; 1050 1051 case TIOCMGET: 1052 *(int *)data = imxuart_to_tiocm(sc); 1053 break; 1054 1055 #ifdef notyet 1056 case PPS_IOC_CREATE: 1057 case PPS_IOC_DESTROY: 1058 case PPS_IOC_GETPARAMS: 1059 case PPS_IOC_SETPARAMS: 1060 case PPS_IOC_GETCAP: 1061 case PPS_IOC_FETCH: 1062 #ifdef PPS_SYNC 1063 case PPS_IOC_KCBIND: 1064 #endif 1065 mutex_spin_enter(&timecounter_lock); 1066 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1067 mutex_spin_exit(&timecounter_lock); 1068 break; 1069 1070 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1071 mutex_spin_enter(&timecounter_lock); 1072 #ifndef PPS_TRAILING_EDGE 1073 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1074 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1075 #else 1076 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1077 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1078 #endif 1079 mutex_spin_exit(&timecounter_lock); 1080 break; 1081 #endif 1082 1083 default: 1084 error = EPASSTHROUGH; 1085 break; 1086 } 1087 1088 mutex_spin_exit(&sc->sc_lock); 1089 1090 #ifdef IMXUART_DEBUG 1091 if (imxuart_debug) 1092 imxustatus(sc, "imxuioctl "); 1093 #endif 1094 1095 return (error); 1096 } 1097 1098 integrate void 1099 imxuart_schedrx(struct imxuart_softc *sc) 1100 { 1101 sc->sc_rx_ready = 1; 1102 1103 /* Wake up the poller. */ 1104 softint_schedule(sc->sc_si); 1105 } 1106 1107 void 1108 imxuart_break(struct imxuart_softc *sc, bool onoff) 1109 { 1110 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1111 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1112 1113 if (onoff) 1114 SET(sc->sc_ucr1, IMX_UCR1_SNDBRK); 1115 else 1116 CLR(sc->sc_ucr1, IMX_UCR1_SNDBRK); 1117 1118 bus_space_write_4(iot, ioh, IMX_UCR1, sc->sc_ucr1); 1119 } 1120 1121 void 1122 imxuart_modem(struct imxuart_softc *sc, int onoff) 1123 { 1124 #ifdef notyet 1125 if (sc->sc_mcr_dtr == 0) 1126 return; 1127 1128 if (onoff) 1129 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1130 else 1131 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1132 1133 if (!sc->sc_heldchange) { 1134 if (sc->sc_tx_busy) { 1135 sc->sc_heldtbc = sc->sc_tbc; 1136 sc->sc_tbc = 0; 1137 sc->sc_heldchange = 1; 1138 } else 1139 imxuart_loadchannelregs(sc); 1140 } 1141 #endif 1142 } 1143 1144 /* 1145 * RTS output is controlled by UCR2.CTS bit. 1146 * DTR output is controlled by UCR3.DSR bit. 1147 * (i.MX reference manual uses names in DCE mode) 1148 * 1149 * note: if UCR2.CTSC == 1 for automatic HW flow control, UCR2.CTS is ignored. 1150 */ 1151 void 1152 tiocm_to_imxu(struct imxuart_softc *sc, u_long how, int ttybits) 1153 { 1154 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1155 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1156 1157 uint32_t ucr2 = sc->sc_ucr2_d; 1158 uint32_t ucr3 = sc->sc_ucr3; 1159 1160 uint32_t ucr2_mask = 0; 1161 uint32_t ucr3_mask = 0; 1162 1163 1164 if (ISSET(ttybits, TIOCM_DTR)) 1165 ucr3_mask = IMX_UCR3_DSR; 1166 if (ISSET(ttybits, TIOCM_RTS)) 1167 ucr2_mask = IMX_UCR2_CTS; 1168 1169 switch (how) { 1170 case TIOCMBIC: 1171 CLR(ucr2, ucr2_mask); 1172 CLR(ucr3, ucr3_mask); 1173 break; 1174 1175 case TIOCMBIS: 1176 SET(ucr2, ucr2_mask); 1177 SET(ucr3, ucr3_mask); 1178 break; 1179 1180 case TIOCMSET: 1181 CLR(ucr2, ucr2_mask); 1182 CLR(ucr3, ucr3_mask); 1183 SET(ucr2, ucr2_mask); 1184 SET(ucr3, ucr3_mask); 1185 break; 1186 } 1187 1188 if (ucr3 != sc->sc_ucr3) { 1189 bus_space_write_4(iot, ioh, IMX_UCR3, ucr3); 1190 sc->sc_ucr3 = ucr3; 1191 } 1192 1193 if (ucr2 == sc->sc_ucr2_d) 1194 return; 1195 1196 sc->sc_ucr2_d = ucr2; 1197 /* update CTS bit only */ 1198 ucr2 = (sc->sc_ucr2 & ~IMX_UCR2_CTS) | 1199 (ucr2 & IMX_UCR2_CTS); 1200 1201 bus_space_write_4(iot, ioh, IMX_UCR2, ucr2); 1202 sc->sc_ucr2 = ucr2; 1203 } 1204 1205 int 1206 imxuart_to_tiocm(struct imxuart_softc *sc) 1207 { 1208 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1209 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1210 int ttybits = 0; 1211 uint32_t usr[2]; 1212 1213 if (ISSET(sc->sc_ucr3, IMX_UCR3_DSR)) 1214 SET(ttybits, TIOCM_DTR); 1215 if (ISSET(sc->sc_ucr2, IMX_UCR2_CTS)) 1216 SET(ttybits, TIOCM_RTS); 1217 1218 bus_space_read_region_4(iot, ioh, IMX_USR1, usr, 2); 1219 1220 if (ISSET(usr[0], IMX_USR1_RTSS)) 1221 SET(ttybits, TIOCM_CTS); 1222 1223 if (ISSET(usr[1], IMX_USR2_DCDIN)) 1224 SET(ttybits, TIOCM_CD); 1225 1226 #if 0 1227 /* XXXbsh: I couldn't find the way to read ipp_uart_dsr_dte_i signal, 1228 although there are bits in UART registers to detect delta of DSR. 1229 */ 1230 if (ISSET(imxubits, MSR_DSR)) 1231 SET(ttybits, TIOCM_DSR); 1232 #endif 1233 1234 if (ISSET(usr[1], IMX_USR2_RIIN)) 1235 SET(ttybits, TIOCM_RI); 1236 1237 1238 #ifdef notyet 1239 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1240 SET(ttybits, TIOCM_LE); 1241 #endif 1242 1243 return (ttybits); 1244 } 1245 1246 static uint32_t 1247 cflag_to_ucr2(tcflag_t cflag, uint32_t oldval) 1248 { 1249 uint32_t val = oldval; 1250 1251 CLR(val,IMX_UCR2_WS|IMX_UCR2_PREN|IMX_UCR2_PROE|IMX_UCR2_STPB); 1252 1253 switch (cflag & CSIZE) { 1254 case CS5: 1255 case CS6: 1256 /* not suppreted. use 7-bits */ 1257 case CS7: 1258 break; 1259 case CS8: 1260 SET(val, IMX_UCR2_WS); 1261 break; 1262 } 1263 1264 1265 if (ISSET(cflag, PARENB)) { 1266 SET(val, IMX_UCR2_PREN); 1267 1268 /* odd parity */ 1269 if (!ISSET(cflag, PARODD)) 1270 SET(val, IMX_UCR2_PROE); 1271 } 1272 1273 if (ISSET(cflag, CSTOPB)) 1274 SET(val, IMX_UCR2_STPB); 1275 1276 val |= IMX_UCR2_TXEN| IMX_UCR2_RXEN|IMX_UCR2_SRST; 1277 1278 return val; 1279 } 1280 1281 int 1282 imxuparam(struct tty *tp, struct termios *t) 1283 { 1284 struct imxuart_softc *sc = 1285 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1286 struct imxuart_baudrate_ratio ratio; 1287 uint32_t ucr2; 1288 bool change_speed = tp->t_ospeed != t->c_ospeed; 1289 1290 if (IMXUART_ISALIVE(sc) == 0) 1291 return (EIO); 1292 1293 /* Check requested parameters. */ 1294 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1295 return (EINVAL); 1296 1297 /* 1298 * For the console, always force CLOCAL and !HUPCL, so that the port 1299 * is always active. 1300 */ 1301 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1302 ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 1303 SET(t->c_cflag, CLOCAL); 1304 CLR(t->c_cflag, HUPCL); 1305 } 1306 1307 /* 1308 * If there were no changes, don't do anything. This avoids dropping 1309 * input and improves performance when all we did was frob things like 1310 * VMIN and VTIME. 1311 */ 1312 if ( !change_speed && tp->t_cflag == t->c_cflag) 1313 return (0); 1314 1315 if (change_speed) { 1316 /* calculate baudrate modulator value */ 1317 if (imxuspeed(t->c_ospeed, &ratio) < 0) 1318 return (EINVAL); 1319 sc->sc_ratio = ratio; 1320 } 1321 1322 ucr2 = cflag_to_ucr2(t->c_cflag, sc->sc_ucr2_d); 1323 1324 mutex_spin_enter(&sc->sc_lock); 1325 1326 #if 0 /* flow control stuff. not yet */ 1327 /* 1328 * If we're not in a mode that assumes a connection is present, then 1329 * ignore carrier changes. 1330 */ 1331 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1332 sc->sc_msr_dcd = 0; 1333 else 1334 sc->sc_msr_dcd = MSR_DCD; 1335 /* 1336 * Set the flow control pins depending on the current flow control 1337 * mode. 1338 */ 1339 if (ISSET(t->c_cflag, CRTSCTS)) { 1340 sc->sc_mcr_dtr = MCR_DTR; 1341 sc->sc_mcr_rts = MCR_RTS; 1342 sc->sc_msr_cts = MSR_CTS; 1343 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1344 } else if (ISSET(t->c_cflag, MDMBUF)) { 1345 /* 1346 * For DTR/DCD flow control, make sure we don't toggle DTR for 1347 * carrier detection. 1348 */ 1349 sc->sc_mcr_dtr = 0; 1350 sc->sc_mcr_rts = MCR_DTR; 1351 sc->sc_msr_cts = MSR_DCD; 1352 sc->sc_efr = 0; 1353 } else { 1354 /* 1355 * If no flow control, then always set RTS. This will make 1356 * the other side happy if it mistakenly thinks we're doing 1357 * RTS/CTS flow control. 1358 */ 1359 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1360 sc->sc_mcr_rts = 0; 1361 sc->sc_msr_cts = 0; 1362 sc->sc_efr = 0; 1363 if (ISSET(sc->sc_mcr, MCR_DTR)) 1364 SET(sc->sc_mcr, MCR_RTS); 1365 else 1366 CLR(sc->sc_mcr, MCR_RTS); 1367 } 1368 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1369 #endif 1370 1371 /* And copy to tty. */ 1372 tp->t_ispeed = t->c_ospeed; 1373 tp->t_ospeed = t->c_ospeed; 1374 tp->t_cflag = t->c_cflag; 1375 1376 if (!change_speed && ucr2 == sc->sc_ucr2_d) { 1377 /* noop */ 1378 } 1379 else if (!sc->sc_pending && !sc->sc_tx_busy) { 1380 if (ucr2 != sc->sc_ucr2_d) { 1381 sc->sc_ucr2_d = ucr2; 1382 imxuart_load_params(sc); 1383 } 1384 if (change_speed) 1385 imxuart_load_speed(sc); 1386 } 1387 else { 1388 if (!sc->sc_pending) { 1389 sc->sc_heldtbc = sc->sc_tbc; 1390 sc->sc_tbc = 0; 1391 } 1392 sc->sc_pending |= 1393 (ucr2 == sc->sc_ucr2_d ? 0 : IMXUART_PEND_PARAM) | 1394 (change_speed ? 0 : IMXUART_PEND_SPEED); 1395 sc->sc_ucr2_d = ucr2; 1396 } 1397 1398 if (!ISSET(t->c_cflag, CHWFLOW)) { 1399 /* Disable the high water mark. */ 1400 sc->sc_r_hiwat = 0; 1401 sc->sc_r_lowat = 0; 1402 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED)) { 1403 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED); 1404 imxuart_schedrx(sc); 1405 } 1406 if (ISSET(sc->sc_rx_flags, 1407 IMXUART_RX_TTY_BLOCKED|IMXUART_RX_IBUF_BLOCKED)) { 1408 CLR(sc->sc_rx_flags, 1409 IMXUART_RX_TTY_BLOCKED|IMXUART_RX_IBUF_BLOCKED); 1410 imxuart_hwiflow(sc); 1411 } 1412 } else { 1413 sc->sc_r_hiwat = imxuart_rbuf_hiwat; 1414 sc->sc_r_lowat = imxuart_rbuf_lowat; 1415 } 1416 1417 mutex_spin_exit(&sc->sc_lock); 1418 1419 #if 0 1420 /* 1421 * Update the tty layer's idea of the carrier bit, in case we changed 1422 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1423 * explicit request. 1424 */ 1425 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1426 #else 1427 /* XXX: always report that we have DCD */ 1428 (void) (*tp->t_linesw->l_modem)(tp, 1); 1429 #endif 1430 1431 #ifdef IMXUART_DEBUG 1432 if (imxuart_debug) 1433 imxustatus(sc, "imxuparam "); 1434 #endif 1435 1436 if (!ISSET(t->c_cflag, CHWFLOW)) { 1437 if (sc->sc_tx_stopped) { 1438 sc->sc_tx_stopped = 0; 1439 imxustart(tp); 1440 } 1441 } 1442 1443 return (0); 1444 } 1445 1446 void 1447 imxuart_iflush(struct imxuart_softc *sc) 1448 { 1449 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1450 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1451 #ifdef DIAGNOSTIC 1452 uint32_t reg = 0xffff; 1453 #endif 1454 int timo; 1455 1456 timo = 50000; 1457 /* flush any pending I/O */ 1458 while (ISSET(bus_space_read_4(iot, ioh, IMX_USR2), IMX_USR2_RDR) 1459 && --timo) 1460 #ifdef DIAGNOSTIC 1461 reg = 1462 #else 1463 (void) 1464 #endif 1465 bus_space_read_4(iot, ioh, IMX_URXD); 1466 #ifdef DIAGNOSTIC 1467 if (!timo) 1468 aprint_error_dev(sc->sc_dev, "imxuart_iflush timeout %02x\n", reg); 1469 #endif 1470 } 1471 1472 int 1473 imxuhwiflow(struct tty *tp, int block) 1474 { 1475 struct imxuart_softc *sc = 1476 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1477 1478 if (IMXUART_ISALIVE(sc) == 0) 1479 return (0); 1480 1481 #ifdef notyet 1482 if (sc->sc_mcr_rts == 0) 1483 return (0); 1484 #endif 1485 1486 mutex_spin_enter(&sc->sc_lock); 1487 1488 if (block) { 1489 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) { 1490 SET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED); 1491 imxuart_hwiflow(sc); 1492 } 1493 } else { 1494 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED)) { 1495 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED); 1496 imxuart_schedrx(sc); 1497 } 1498 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) { 1499 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED); 1500 imxuart_hwiflow(sc); 1501 } 1502 } 1503 1504 mutex_spin_exit(&sc->sc_lock); 1505 return (1); 1506 } 1507 1508 /* 1509 * (un)block input via hw flowcontrol 1510 */ 1511 void 1512 imxuart_hwiflow(struct imxuart_softc *sc) 1513 { 1514 #ifdef notyet 1515 struct imxuart_regs *regsp= &sc->sc_regs; 1516 1517 if (sc->sc_mcr_rts == 0) 1518 return; 1519 1520 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1521 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1522 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1523 } else { 1524 SET(sc->sc_mcr, sc->sc_mcr_rts); 1525 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1526 } 1527 UR_WRITE_1(regsp, IMXUART_REG_MCR, sc->sc_mcr_active); 1528 #endif 1529 } 1530 1531 1532 void 1533 imxustart(struct tty *tp) 1534 { 1535 struct imxuart_softc *sc = 1536 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1537 int s; 1538 u_char *tba; 1539 int tbc; 1540 u_int n; 1541 u_int space; 1542 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1543 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1544 1545 if (IMXUART_ISALIVE(sc) == 0) 1546 return; 1547 1548 s = spltty(); 1549 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1550 goto out; 1551 if (sc->sc_tx_stopped) 1552 goto out; 1553 if (!ttypull(tp)) 1554 goto out; 1555 1556 /* Grab the first contiguous region of buffer space. */ 1557 tba = tp->t_outq.c_cf; 1558 tbc = ndqb(&tp->t_outq, 0); 1559 1560 mutex_spin_enter(&sc->sc_lock); 1561 1562 sc->sc_tba = tba; 1563 sc->sc_tbc = tbc; 1564 1565 SET(tp->t_state, TS_BUSY); 1566 sc->sc_tx_busy = 1; 1567 1568 space = imxuart_txfifo_space(sc); 1569 n = MIN(sc->sc_tbc, space); 1570 1571 bus_space_write_multi_1(iot, ioh, IMX_UTXD, sc->sc_tba, n); 1572 sc->sc_tbc -= n; 1573 sc->sc_tba += n; 1574 1575 /* Enable transmit completion interrupts */ 1576 imxuart_control_txint(sc, true); 1577 1578 mutex_spin_exit(&sc->sc_lock); 1579 out: 1580 splx(s); 1581 return; 1582 } 1583 1584 /* 1585 * Stop output on a line. 1586 */ 1587 void 1588 imxustop(struct tty *tp, int flag) 1589 { 1590 struct imxuart_softc *sc = 1591 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1592 1593 mutex_spin_enter(&sc->sc_lock); 1594 if (ISSET(tp->t_state, TS_BUSY)) { 1595 /* Stop transmitting at the next chunk. */ 1596 sc->sc_tbc = 0; 1597 sc->sc_heldtbc = 0; 1598 if (!ISSET(tp->t_state, TS_TTSTOP)) 1599 SET(tp->t_state, TS_FLUSH); 1600 } 1601 mutex_spin_exit(&sc->sc_lock); 1602 } 1603 1604 void 1605 imxudiag(void *arg) 1606 { 1607 #ifdef notyet 1608 struct imxuart_softc *sc = arg; 1609 int overflows, floods; 1610 1611 mutex_spin_enter(&sc->sc_lock); 1612 overflows = sc->sc_overflows; 1613 sc->sc_overflows = 0; 1614 floods = sc->sc_floods; 1615 sc->sc_floods = 0; 1616 sc->sc_errors = 0; 1617 mutex_spin_exit(&sc->sc_lock); 1618 1619 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1620 device_xname(sc->sc_dev), 1621 overflows, overflows == 1 ? "" : "s", 1622 floods, floods == 1 ? "" : "s"); 1623 #endif 1624 } 1625 1626 integrate void 1627 imxuart_rxsoft(struct imxuart_softc *sc, struct tty *tp) 1628 { 1629 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1630 u_int cc, scc, outp; 1631 uint16_t data; 1632 u_int code; 1633 1634 scc = cc = IMXUART_RBUF_AVAIL(sc); 1635 1636 #if 0 1637 if (cc == imxuart_rbuf_size-1) { 1638 sc->sc_floods++; 1639 if (sc->sc_errors++ == 0) 1640 callout_reset(&sc->sc_diag_callout, 60 * hz, 1641 imxudiag, sc); 1642 } 1643 #endif 1644 1645 /* If not yet open, drop the entire buffer content here */ 1646 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1647 sc->sc_rbuf_out = sc->sc_rbuf_in; 1648 cc = 0; 1649 } 1650 1651 outp = sc->sc_rbuf_out; 1652 1653 #define ERRBITS (IMX_URXD_PRERR|IMX_URXD_BRK|IMX_URXD_FRMERR|IMX_URXD_OVRRUN) 1654 1655 while (cc) { 1656 data = sc->sc_rbuf[outp]; 1657 code = data & IMX_URXD_RX_DATA; 1658 if (ISSET(data, ERRBITS)) { 1659 if (sc->sc_errors.err == 0) 1660 callout_reset(&sc->sc_diag_callout, 1661 60 * hz, imxudiag, sc); 1662 if (ISSET(data, IMX_URXD_OVRRUN)) 1663 sc->sc_errors.ovrrun++; 1664 if (ISSET(data, IMX_URXD_BRK)) { 1665 sc->sc_errors.brk++; 1666 SET(code, TTY_FE); 1667 } 1668 if (ISSET(data, IMX_URXD_FRMERR)) { 1669 sc->sc_errors.frmerr++; 1670 SET(code, TTY_FE); 1671 } 1672 if (ISSET(data, IMX_URXD_PRERR)) { 1673 sc->sc_errors.prerr++; 1674 SET(code, TTY_PE); 1675 } 1676 } 1677 if ((*rint)(code, tp) == -1) { 1678 /* 1679 * The line discipline's buffer is out of space. 1680 */ 1681 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) { 1682 /* 1683 * We're either not using flow control, or the 1684 * line discipline didn't tell us to block for 1685 * some reason. Either way, we have no way to 1686 * know when there's more space available, so 1687 * just drop the rest of the data. 1688 */ 1689 sc->sc_rbuf_out = sc->sc_rbuf_in; 1690 cc = 0; 1691 } else { 1692 /* 1693 * Don't schedule any more receive processing 1694 * until the line discipline tells us there's 1695 * space available (through imxuhwiflow()). 1696 * Leave the rest of the data in the input 1697 * buffer. 1698 */ 1699 SET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED); 1700 } 1701 break; 1702 } 1703 outp = IMXUART_RBUF_INC(sc, outp, 1); 1704 cc--; 1705 } 1706 1707 if (cc != scc) { 1708 sc->sc_rbuf_out = outp; 1709 mutex_spin_enter(&sc->sc_lock); 1710 1711 cc = IMXUART_RBUF_SPACE(sc); 1712 1713 /* Buffers should be ok again, release possible block. */ 1714 if (cc >= sc->sc_r_lowat) { 1715 if (ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_OVERFLOWED)) { 1716 CLR(sc->sc_rx_flags, IMXUART_RX_IBUF_OVERFLOWED); 1717 imxuart_control_rxint(sc, true); 1718 } 1719 if (ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED)) { 1720 CLR(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED); 1721 imxuart_hwiflow(sc); 1722 } 1723 } 1724 mutex_spin_exit(&sc->sc_lock); 1725 } 1726 } 1727 1728 integrate void 1729 imxuart_txsoft(struct imxuart_softc *sc, struct tty *tp) 1730 { 1731 1732 CLR(tp->t_state, TS_BUSY); 1733 if (ISSET(tp->t_state, TS_FLUSH)) 1734 CLR(tp->t_state, TS_FLUSH); 1735 else 1736 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1737 (*tp->t_linesw->l_start)(tp); 1738 } 1739 1740 integrate void 1741 imxuart_stsoft(struct imxuart_softc *sc, struct tty *tp) 1742 { 1743 #ifdef notyet 1744 u_char msr, delta; 1745 1746 mutex_spin_enter(&sc->sc_lock); 1747 msr = sc->sc_msr; 1748 delta = sc->sc_msr_delta; 1749 sc->sc_msr_delta = 0; 1750 mutex_spin_exit(&sc->sc_lock); 1751 1752 if (ISSET(delta, sc->sc_msr_dcd)) { 1753 /* 1754 * Inform the tty layer that carrier detect changed. 1755 */ 1756 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1757 } 1758 1759 if (ISSET(delta, sc->sc_msr_cts)) { 1760 /* Block or unblock output according to flow control. */ 1761 if (ISSET(msr, sc->sc_msr_cts)) { 1762 sc->sc_tx_stopped = 0; 1763 (*tp->t_linesw->l_start)(tp); 1764 } else { 1765 sc->sc_tx_stopped = 1; 1766 } 1767 } 1768 1769 #endif 1770 #ifdef IMXUART_DEBUG 1771 if (imxuart_debug) 1772 imxustatus(sc, "imxuart_stsoft"); 1773 #endif 1774 } 1775 1776 void 1777 imxusoft(void *arg) 1778 { 1779 struct imxuart_softc *sc = arg; 1780 struct tty *tp; 1781 1782 if (IMXUART_ISALIVE(sc) == 0) 1783 return; 1784 1785 tp = sc->sc_tty; 1786 1787 if (sc->sc_rx_ready) { 1788 sc->sc_rx_ready = 0; 1789 imxuart_rxsoft(sc, tp); 1790 } 1791 1792 if (sc->sc_st_check) { 1793 sc->sc_st_check = 0; 1794 imxuart_stsoft(sc, tp); 1795 } 1796 1797 if (sc->sc_tx_done) { 1798 sc->sc_tx_done = 0; 1799 imxuart_txsoft(sc, tp); 1800 } 1801 } 1802 1803 int 1804 imxuintr(void *arg) 1805 { 1806 struct imxuart_softc *sc = arg; 1807 uint32_t usr1, usr2; 1808 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1809 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1810 1811 1812 if (IMXUART_ISALIVE(sc) == 0) 1813 return (0); 1814 1815 mutex_spin_enter(&sc->sc_lock); 1816 1817 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1818 1819 1820 do { 1821 bus_space_write_4(iot, ioh, IMX_USR2, 1822 usr2 & (IMX_USR2_BRCD|IMX_USR2_ORE)); 1823 if (usr2 & IMX_USR2_BRCD) { 1824 /* Break signal detected */ 1825 int cn_trapped = 0; 1826 1827 cn_check_magic(sc->sc_tty->t_dev, 1828 CNC_BREAK, imxuart_cnm_state); 1829 if (cn_trapped) 1830 continue; 1831 #if defined(KGDB) && !defined(DDB) 1832 if (ISSET(sc->sc_hwflags, IMXUART_HW_KGDB)) { 1833 kgdb_connect(1); 1834 continue; 1835 } 1836 #endif 1837 } 1838 1839 if (usr2 & IMX_USR2_RDR) 1840 imxuintr_read(sc); 1841 1842 #ifdef IMXUART_PPS 1843 { 1844 u_char msr, delta; 1845 1846 msr = CSR_READ_1(regsp, IMXUART_REG_MSR); 1847 delta = msr ^ sc->sc_msr; 1848 sc->sc_msr = msr; 1849 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 1850 (delta & MSR_DCD)) { 1851 mutex_spin_enter(&timecounter_lock); 1852 pps_capture(&sc->sc_pps_state); 1853 pps_event(&sc->sc_pps_state, 1854 (msr & MSR_DCD) ? 1855 PPS_CAPTUREASSERT : 1856 PPS_CAPTURECLEAR); 1857 mutex_spin_exit(&timecounter_lock); 1858 } 1859 } 1860 #endif 1861 1862 #ifdef notyet 1863 /* 1864 * Process normal status changes 1865 */ 1866 if (ISSET(delta, sc->sc_msr_mask)) { 1867 SET(sc->sc_msr_delta, delta); 1868 1869 /* 1870 * Stop output immediately if we lose the output 1871 * flow control signal or carrier detect. 1872 */ 1873 if (ISSET(~msr, sc->sc_msr_mask)) { 1874 sc->sc_tbc = 0; 1875 sc->sc_heldtbc = 0; 1876 #ifdef IMXUART_DEBUG 1877 if (imxuart_debug) 1878 imxustatus(sc, "imxuintr "); 1879 #endif 1880 } 1881 1882 sc->sc_st_check = 1; 1883 } 1884 #endif 1885 1886 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1887 } while (usr2 & (IMX_USR2_RDR|IMX_USR2_BRCD)); 1888 1889 usr1 = bus_space_read_4(iot, ioh, IMX_USR1); 1890 if (usr1 & IMX_USR1_TRDY) 1891 imxuintr_send(sc); 1892 1893 mutex_spin_exit(&sc->sc_lock); 1894 1895 /* Wake up the poller. */ 1896 softint_schedule(sc->sc_si); 1897 1898 #ifdef RND_COM 1899 rnd_add_uint32(&sc->rnd_source, iir | lsr); 1900 #endif 1901 1902 return (1); 1903 } 1904 1905 1906 /* 1907 * called when there is least one character in rxfifo 1908 * 1909 */ 1910 1911 static void 1912 imxuintr_read(struct imxuart_softc *sc) 1913 { 1914 int cc; 1915 uint16_t rd; 1916 uint32_t usr2; 1917 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1918 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1919 1920 cc = IMXUART_RBUF_SPACE(sc); 1921 1922 /* clear aging timer interrupt */ 1923 bus_space_write_4(iot, ioh, IMX_USR1, IMX_USR1_AGTIM); 1924 1925 while (cc > 0) { 1926 int cn_trapped = 0; 1927 1928 1929 sc->sc_rbuf[sc->sc_rbuf_in] = rd = 1930 bus_space_read_4(iot, ioh, IMX_URXD); 1931 1932 cn_check_magic(sc->sc_tty->t_dev, 1933 rd & 0xff, imxuart_cnm_state); 1934 1935 if (!cn_trapped) { 1936 #if defined(DDB) && defined(DDB_KEYCODE) 1937 /* 1938 * Temporary hack so that I can force the kernel into 1939 * the debugger via the serial port 1940 */ 1941 if ((rd & 0xff) == DDB_KEYCODE) 1942 Debugger(); 1943 #endif 1944 sc->sc_rbuf_in = IMXUART_RBUF_INC(sc, sc->sc_rbuf_in, 1); 1945 cc--; 1946 } 1947 1948 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1949 if (!(usr2 & IMX_USR2_RDR)) 1950 break; 1951 } 1952 1953 /* 1954 * Current string of incoming characters ended because 1955 * no more data was available or we ran out of space. 1956 * Schedule a receive event if any data was received. 1957 * If we're out of space, turn off receive interrupts. 1958 */ 1959 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED)) 1960 sc->sc_rx_ready = 1; 1961 /* 1962 * See if we are in danger of overflowing a buffer. If 1963 * so, use hardware flow control to ease the pressure. 1964 */ 1965 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED) && 1966 cc < sc->sc_r_hiwat) { 1967 sc->sc_rx_flags |= IMXUART_RX_IBUF_BLOCKED; 1968 imxuart_hwiflow(sc); 1969 } 1970 1971 /* 1972 * If we're out of space, disable receive interrupts 1973 * until the queue has drained a bit. 1974 */ 1975 if (!cc) { 1976 sc->sc_rx_flags |= IMXUART_RX_IBUF_OVERFLOWED; 1977 imxuart_control_rxint(sc, false); 1978 } 1979 } 1980 1981 1982 1983 /* 1984 * find how many chars we can put into tx-fifo 1985 */ 1986 static u_int 1987 imxuart_txfifo_space(struct imxuart_softc *sc) 1988 { 1989 uint32_t usr1, usr2; 1990 u_int cc; 1991 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1992 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1993 1994 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1995 if (usr2 & IMX_USR2_TXFE) 1996 cc = sc->sc_txfifo_len; 1997 else { 1998 usr1 = bus_space_read_4(iot, ioh, IMX_USR1); 1999 if (usr1 & IMX_USR1_TRDY) 2000 cc = sc->sc_txfifo_thresh; 2001 else 2002 cc = 0; 2003 } 2004 2005 return cc; 2006 } 2007 2008 void 2009 imxuintr_send(struct imxuart_softc *sc) 2010 { 2011 uint32_t usr2; 2012 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2013 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2014 int cc = 0; 2015 2016 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 2017 2018 if (sc->sc_pending) { 2019 if (usr2 & IMX_USR2_TXFE) { 2020 imxuart_load_pendings(sc); 2021 sc->sc_tbc = sc->sc_heldtbc; 2022 sc->sc_heldtbc = 0; 2023 } 2024 else { 2025 /* wait for TX fifo empty */ 2026 imxuart_control_txint(sc, true); 2027 return; 2028 } 2029 } 2030 2031 cc = imxuart_txfifo_space(sc); 2032 cc = MIN(cc, sc->sc_tbc); 2033 2034 if (cc > 0) { 2035 bus_space_write_multi_1(iot, ioh, IMX_UTXD, sc->sc_tba, cc); 2036 sc->sc_tbc -= cc; 2037 sc->sc_tba += cc; 2038 } 2039 2040 if (sc->sc_tbc > 0) 2041 imxuart_control_txint(sc, true); 2042 else { 2043 /* no more chars to send. 2044 we don't need tx interrupt any more. */ 2045 imxuart_control_txint(sc, false); 2046 if (sc->sc_tx_busy) { 2047 sc->sc_tx_busy = 0; 2048 sc->sc_tx_done = 1; 2049 } 2050 } 2051 } 2052 2053 static void 2054 imxuart_disable_all_interrupts(struct imxuart_softc *sc) 2055 { 2056 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2057 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2058 2059 sc->sc_ucr1 &= ~IMXUART_INTRS_UCR1; 2060 sc->sc_ucr2 &= ~IMXUART_INTRS_UCR2; 2061 sc->sc_ucr3 &= ~IMXUART_INTRS_UCR3; 2062 sc->sc_ucr4 &= ~IMXUART_INTRS_UCR4; 2063 2064 2065 bus_space_write_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 4); 2066 } 2067 2068 static void 2069 imxuart_control_rxint(struct imxuart_softc *sc, bool enable) 2070 { 2071 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2072 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2073 uint32_t ucr1, ucr2; 2074 2075 ucr1 = sc->sc_ucr1; 2076 ucr2 = sc->sc_ucr2; 2077 2078 if (enable) { 2079 ucr1 |= IMX_UCR1_RRDYEN; 2080 ucr2 |= IMX_UCR2_ATEN; 2081 } 2082 else { 2083 ucr1 &= ~IMX_UCR1_RRDYEN; 2084 ucr2 &= ~IMX_UCR2_ATEN; 2085 } 2086 2087 if (ucr1 != sc->sc_ucr1 || ucr2 != sc->sc_ucr2) { 2088 sc->sc_ucr1 = ucr1; 2089 sc->sc_ucr2 = ucr2; 2090 bus_space_write_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 2); 2091 } 2092 } 2093 2094 static void 2095 imxuart_control_txint(struct imxuart_softc *sc, bool enable) 2096 { 2097 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2098 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2099 uint32_t ucr1; 2100 uint32_t mask; 2101 2102 /* if parameter change is pending, get interrupt when Tx fifo 2103 is completely empty. otherwise, get interrupt when txfifo 2104 has less characters than threshold */ 2105 mask = sc->sc_pending ? IMX_UCR1_TXMPTYEN : IMX_UCR1_TRDYEN; 2106 2107 ucr1 = sc->sc_ucr1; 2108 2109 CLR(ucr1, IMX_UCR1_TXMPTYEN|IMX_UCR1_TRDYEN); 2110 if (enable) 2111 SET(ucr1, mask); 2112 2113 if (ucr1 != sc->sc_ucr1) { 2114 bus_space_write_4(iot, ioh, IMX_UCR1, ucr1); 2115 sc->sc_ucr1 = ucr1; 2116 } 2117 } 2118 2119 2120 static void 2121 imxuart_load_params(struct imxuart_softc *sc) 2122 { 2123 uint32_t ucr2; 2124 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2125 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2126 2127 ucr2 = (sc->sc_ucr2_d & ~IMX_UCR2_ATEN) | 2128 (sc->sc_ucr2 & IMX_UCR2_ATEN); 2129 2130 bus_space_write_4(iot, ioh, IMX_UCR2, ucr2); 2131 sc->sc_ucr2 = ucr2; 2132 } 2133 2134 static void 2135 imxuart_load_speed(struct imxuart_softc *sc) 2136 { 2137 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2138 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2139 int n, rfdiv, ufcr; 2140 2141 #ifdef notyet 2142 /* 2143 * Set the FIFO threshold based on the receive speed. 2144 * 2145 * * If it's a low speed, it's probably a mouse or some other 2146 * interactive device, so set the threshold low. 2147 * * If it's a high speed, trim the trigger level down to prevent 2148 * overflows. 2149 * * Otherwise set it a bit higher. 2150 */ 2151 if (t->c_ospeed <= 1200) 2152 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 2153 else if (t->c_ospeed <= 38400) 2154 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 2155 else 2156 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 2157 #endif 2158 2159 n = 32 - sc->sc_txfifo_thresh; 2160 n = MAX(2, n); 2161 2162 rfdiv = IMX_UFCR_DIVIDER_TO_RFDIV(imxuart_freqdiv); 2163 2164 ufcr = (n << IMX_UFCR_TXTL_SHIFT) | 2165 (rfdiv << IMX_UFCR_RFDIV_SHIFT) | 2166 (16 << IMX_UFCR_RXTL_SHIFT); 2167 2168 /* keep DCE/DTE bit */ 2169 ufcr |= bus_space_read_4(iot, ioh, IMX_UFCR) & IMX_UFCR_DCEDTE; 2170 2171 bus_space_write_4(iot, ioh, IMX_UFCR, ufcr); 2172 2173 /* UBIR must updated before UBMR */ 2174 bus_space_write_4(iot, ioh, 2175 IMX_UBIR, sc->sc_ratio.numerator); 2176 bus_space_write_4(iot, ioh, 2177 IMX_UBMR, sc->sc_ratio.modulator); 2178 2179 2180 } 2181 2182 2183 static void 2184 imxuart_load_pendings(struct imxuart_softc *sc) 2185 { 2186 if (sc->sc_pending & IMXUART_PEND_PARAM) 2187 imxuart_load_params(sc); 2188 if (sc->sc_pending & IMXUART_PEND_SPEED) 2189 imxuart_load_speed(sc); 2190 sc->sc_pending = 0; 2191 } 2192 2193 #if defined(IMXUARTCONSOLE) || defined(KGDB) 2194 2195 /* 2196 * The following functions are polled getc and putc routines, shared 2197 * by the console and kgdb glue. 2198 * 2199 * The read-ahead code is so that you can detect pending in-band 2200 * cn_magic in polled mode while doing output rather than having to 2201 * wait until the kernel decides it needs input. 2202 */ 2203 2204 #define READAHEAD_RING_LEN 16 2205 static int imxuart_readahead[READAHEAD_RING_LEN]; 2206 static int imxuart_readahead_in = 0; 2207 static int imxuart_readahead_out = 0; 2208 #define READAHEAD_IS_EMPTY() (imxuart_readahead_in==imxuart_readahead_out) 2209 #define READAHEAD_IS_FULL() \ 2210 (((imxuart_readahead_in+1) & (READAHEAD_RING_LEN-1)) ==imxuart_readahead_out) 2211 2212 int 2213 imxuart_common_getc(dev_t dev, struct imxuart_regs *regsp) 2214 { 2215 int s = splserial(); 2216 u_char c; 2217 bus_space_tag_t iot = regsp->ur_iot; 2218 bus_space_handle_t ioh = regsp->ur_ioh; 2219 uint32_t usr2; 2220 2221 /* got a character from reading things earlier */ 2222 if (imxuart_readahead_in != imxuart_readahead_out) { 2223 2224 c = imxuart_readahead[imxuart_readahead_out]; 2225 imxuart_readahead_out = (imxuart_readahead_out + 1) & 2226 (READAHEAD_RING_LEN-1); 2227 splx(s); 2228 return (c); 2229 } 2230 2231 /* block until a character becomes available */ 2232 while (!((usr2 = bus_space_read_4(iot, ioh, IMX_USR2)) & IMX_USR2_RDR)) 2233 ; 2234 2235 c = 0xff & bus_space_read_4(iot, ioh, IMX_URXD); 2236 2237 { 2238 int __attribute__((__unused__))cn_trapped = 0; /* unused */ 2239 #ifdef DDB 2240 extern int db_active; 2241 if (!db_active) 2242 #endif 2243 cn_check_magic(dev, c, imxuart_cnm_state); 2244 } 2245 splx(s); 2246 return (c); 2247 } 2248 2249 void 2250 imxuart_common_putc(dev_t dev, struct imxuart_regs *regsp, int c) 2251 { 2252 int s = splserial(); 2253 int cin, timo; 2254 bus_space_tag_t iot = regsp->ur_iot; 2255 bus_space_handle_t ioh = regsp->ur_ioh; 2256 uint32_t usr2; 2257 2258 if (!READAHEAD_IS_FULL() && 2259 ((usr2 = bus_space_read_4(iot, ioh, IMX_USR2)) & IMX_USR2_RDR)) { 2260 2261 int __attribute__((__unused__))cn_trapped = 0; 2262 cin = bus_space_read_4(iot, ioh, IMX_URXD); 2263 cn_check_magic(dev, cin & 0xff, imxuart_cnm_state); 2264 imxuart_readahead_in = (imxuart_readahead_in + 1) & 2265 (READAHEAD_RING_LEN-1); 2266 } 2267 2268 /* wait for any pending transmission to finish */ 2269 timo = 150000; 2270 do { 2271 if (bus_space_read_4(iot, ioh, IMX_USR1) & IMX_USR1_TRDY) { 2272 bus_space_write_4(iot, ioh, IMX_UTXD, c); 2273 break; 2274 } 2275 } while(--timo > 0); 2276 2277 IMXUART_BARRIER(regsp, BR | BW); 2278 2279 splx(s); 2280 } 2281 #endif /* defined(IMXUARTCONSOLE) || defined(KGDB) */ 2282 2283 /* 2284 * Initialize UART 2285 */ 2286 int 2287 imxuart_init(struct imxuart_regs *regsp, int rate, tcflag_t cflag, int domap) 2288 { 2289 struct imxuart_baudrate_ratio ratio; 2290 int rfdiv = IMX_UFCR_DIVIDER_TO_RFDIV(imxuart_freqdiv); 2291 uint32_t ufcr; 2292 int error; 2293 2294 if (domap && (error = bus_space_map(regsp->ur_iot, regsp->ur_iobase, 2295 IMX_UART_SIZE, 0, ®sp->ur_ioh)) != 0) 2296 return error; 2297 2298 if (imxuspeed(rate, &ratio) < 0) 2299 return EINVAL; 2300 2301 /* UBIR must updated before UBMR */ 2302 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, 2303 IMX_UBIR, ratio.numerator); 2304 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, 2305 IMX_UBMR, ratio.modulator); 2306 2307 2308 /* XXX: DTREN, DPEC */ 2309 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR3, 2310 IMX_UCR3_DSR|IMX_UCR3_RXDMUXSEL); 2311 2312 ufcr = (8 << IMX_UFCR_TXTL_SHIFT) | (rfdiv << IMX_UFCR_RFDIV_SHIFT) | 2313 (1 << IMX_UFCR_RXTL_SHIFT); 2314 /* XXX: keep DCE/DTE bit */ 2315 ufcr |= bus_space_read_4(regsp->ur_iot, regsp->ur_ioh, IMX_UFCR) & 2316 IMX_UFCR_DCEDTE; 2317 2318 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UFCR, ufcr); 2319 2320 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_ONEMS, 2321 imxuart_freq / imxuart_freqdiv / 1000); 2322 2323 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR2, 2324 IMX_UCR2_IRTS| 2325 IMX_UCR2_CTSC| 2326 IMX_UCR2_WS|IMX_UCR2_TXEN| 2327 IMX_UCR2_RXEN|IMX_UCR2_SRST); 2328 /* clear status registers */ 2329 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_USR1, 0xffff); 2330 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_USR2, 0xffff); 2331 2332 2333 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR1, 2334 IMX_UCR1_UARTEN); 2335 2336 return (0); 2337 } 2338 2339 2340 #ifdef IMXUARTCONSOLE 2341 /* 2342 * Following are all routines needed for UART to act as console 2343 */ 2344 struct consdev imxucons = { 2345 NULL, NULL, imxucngetc, imxucnputc, imxucnpollc, NULL, NULL, NULL, 2346 NODEV, CN_NORMAL 2347 }; 2348 2349 2350 int 2351 imxuart_cons_attach(bus_space_tag_t iot, paddr_t iobase, u_int rate, 2352 tcflag_t cflag) 2353 { 2354 struct imxuart_regs regs; 2355 int res; 2356 2357 regs.ur_iot = iot; 2358 regs.ur_iobase = iobase; 2359 2360 res = imxuart_init(®s, rate, cflag, true); 2361 if (res) 2362 return (res); 2363 2364 cn_tab = &imxucons; 2365 cn_init_magic(&imxuart_cnm_state); 2366 cn_set_magic("\047\001"); /* default magic is BREAK */ 2367 2368 imxuconsrate = rate; 2369 imxuconscflag = cflag; 2370 2371 imxuconsregs = regs; 2372 2373 return 0; 2374 } 2375 2376 int 2377 imxucngetc(dev_t dev) 2378 { 2379 return (imxuart_common_getc(dev, &imxuconsregs)); 2380 } 2381 2382 /* 2383 * Console kernel output character routine. 2384 */ 2385 void 2386 imxucnputc(dev_t dev, int c) 2387 { 2388 imxuart_common_putc(dev, &imxuconsregs, c); 2389 } 2390 2391 void 2392 imxucnpollc(dev_t dev, int on) 2393 { 2394 2395 imxuart_readahead_in = 0; 2396 imxuart_readahead_out = 0; 2397 } 2398 2399 #endif /* IMXUARTCONSOLE */ 2400 2401 #ifdef KGDB 2402 int 2403 imxuart_kgdb_attach(bus_space_tag_t iot, paddr_t iobase, u_int rate, 2404 tcflag_t cflag) 2405 { 2406 int res; 2407 2408 if (iot == imxuconsregs.ur_iot && 2409 iobase == imxuconsregs.ur_iobase) { 2410 #if !defined(DDB) 2411 return (EBUSY); /* cannot share with console */ 2412 #else 2413 imxu_kgdb_regs.ur_iot = iot; 2414 imxu_kgdb_regs.ur_ioh = imxuconsregs.ur_ioh; 2415 imxu_kgdb_regs.ur_iobase = iobase; 2416 #endif 2417 } else { 2418 imxu_kgdb_regs.ur_iot = iot; 2419 imxu_kgdb_regs.ur_iobase = iobase; 2420 2421 res = imxuart_init(&imxu_kgdb_regs, rate, cflag, true); 2422 if (res) 2423 return (res); 2424 2425 /* 2426 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2427 * expects this to be initialized 2428 */ 2429 cn_init_magic(&imxuart_cnm_state); 2430 cn_set_magic("\047\001"); 2431 } 2432 2433 kgdb_attach(imxuart_kgdb_getc, imxuart_kgdb_putc, &imxu_kgdb_regs); 2434 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2435 2436 return (0); 2437 } 2438 2439 /* ARGSUSED */ 2440 int 2441 imxuart_kgdb_getc(void *arg) 2442 { 2443 struct imxuart_regs *regs = arg; 2444 2445 return (imxuart_common_getc(NODEV, regs)); 2446 } 2447 2448 /* ARGSUSED */ 2449 void 2450 imxuart_kgdb_putc(void *arg, int c) 2451 { 2452 struct imxuart_regs *regs = arg; 2453 2454 imxuart_common_putc(NODEV, regs, c); 2455 } 2456 #endif /* KGDB */ 2457 2458 /* helper function to identify the imxu ports used by 2459 console or KGDB (and not yet autoconf attached) */ 2460 int 2461 imxuart_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2462 { 2463 bus_space_handle_t help; 2464 2465 if (!imxuconsattached && 2466 iot == imxuconsregs.ur_iot && iobase == imxuconsregs.ur_iobase) 2467 help = imxuconsregs.ur_ioh; 2468 #ifdef KGDB 2469 else if (!imxu_kgdb_attached && 2470 iot == imxu_kgdb_regs.ur_iot && iobase == imxu_kgdb_regs.ur_iobase) 2471 help = imxu_kgdb_regs.ur_ioh; 2472 #endif 2473 else 2474 return (0); 2475 2476 if (ioh) 2477 *ioh = help; 2478 return (1); 2479 } 2480 2481 #ifdef notyet 2482 2483 bool 2484 imxuart_cleanup(device_t self, int how) 2485 { 2486 /* 2487 * this routine exists to serve as a shutdown hook for systems that 2488 * have firmware which doesn't interact properly with a imxuart device in 2489 * FIFO mode. 2490 */ 2491 struct imxuart_softc *sc = device_private(self); 2492 2493 if (ISSET(sc->sc_hwflags, IMXUART_HW_FIFO)) 2494 UR_WRITE_1(&sc->sc_regs, IMXUART_REG_FIFO, 0); 2495 2496 return true; 2497 } 2498 #endif 2499 2500 #ifdef notyet 2501 bool 2502 imxuart_suspend(device_t self PMF_FN_ARGS) 2503 { 2504 struct imxuart_softc *sc = device_private(self); 2505 2506 UR_WRITE_1(&sc->sc_regs, IMXUART_REG_IER, 0); 2507 (void)CSR_READ_1(&sc->sc_regs, IMXUART_REG_IIR); 2508 2509 return true; 2510 } 2511 #endif 2512 2513 #ifdef notyet 2514 bool 2515 imxuart_resume(device_t self PMF_FN_ARGS) 2516 { 2517 struct imxuart_softc *sc = device_private(self); 2518 2519 mutex_spin_enter(&sc->sc_lock); 2520 imxuart_loadchannelregs(sc); 2521 mutex_spin_exit(&sc->sc_lock); 2522 2523 return true; 2524 } 2525 #endif 2526 2527 static void 2528 imxuart_enable_debugport(struct imxuart_softc *sc) 2529 { 2530 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2531 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2532 2533 if (sc->sc_hwflags & (IMXUART_HW_CONSOLE|IMXUART_HW_KGDB)) { 2534 2535 /* Turn on line break interrupt, set carrier. */ 2536 2537 sc->sc_ucr3 |= IMX_UCR3_DSR; 2538 bus_space_write_4(iot, ioh, IMX_UCR3, sc->sc_ucr3); 2539 2540 sc->sc_ucr4 |= IMX_UCR4_BKEN; 2541 bus_space_write_4(iot, ioh, IMX_UCR4, sc->sc_ucr4); 2542 2543 sc->sc_ucr2 |= IMX_UCR2_TXEN|IMX_UCR2_RXEN| 2544 IMX_UCR2_CTS; 2545 bus_space_write_4(iot, ioh, IMX_UCR2, sc->sc_ucr2); 2546 2547 sc->sc_ucr1 |= IMX_UCR1_UARTEN; 2548 bus_space_write_4(iot, ioh, IMX_UCR1, sc->sc_ucr1); 2549 } 2550 } 2551 2552 2553 void 2554 imxuart_set_frequency(u_int freq, u_int div) 2555 { 2556 imxuart_freq = freq; 2557 imxuart_freqdiv = div; 2558 } 2559
Indexes created Mon Sep 29 21:09:56 GMT 2025