imxuart.c revision 1.20
1 /* $NetBSD: imxuart.c,v 1.20 2017/09/08 05:29:12 hkenken Exp $ */ 2 3 /* 4 * Copyright (c) 2009, 2010 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* 31 * derived from sys/dev/ic/com.c 32 */ 33 34 /*- 35 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to The NetBSD Foundation 39 * by Charles M. Hannum. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 51 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 52 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 53 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 60 * POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Copyright (c) 1991 The Regents of the University of California. 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 3. Neither the name of the University nor the names of its contributors 76 * may be used to endorse or promote products derived from this software 77 * without specific prior written permission. 78 * 79 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 80 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 82 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 85 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 86 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 87 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 88 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 89 * SUCH DAMAGE. 90 * 91 * @(#)com.c 7.5 (Berkeley) 5/16/91 92 */ 93 94 /* 95 * driver for UART in i.MX SoC. 96 */ 97 98 #include <sys/cdefs.h> 99 __KERNEL_RCSID(0, "$NetBSD: imxuart.c,v 1.20 2017/09/08 05:29:12 hkenken Exp $"); 100 101 #include "opt_imxuart.h" 102 #include "opt_ddb.h" 103 #include "opt_ddbparam.h" 104 #include "opt_kgdb.h" 105 #include "opt_lockdebug.h" 106 #include "opt_multiprocessor.h" 107 #include "opt_ntp.h" 108 #include "opt_imxuart.h" 109 110 #ifdef RND_COM 111 #include <sys/rndsource.h> 112 #endif 113 114 #ifndef IMXUART_TOLERANCE 115 #define IMXUART_TOLERANCE 30 /* baud rate tolerance, in 0.1% units */ 116 #endif 117 118 #ifndef IMXUART_FREQDIV 119 #define IMXUART_FREQDIV 2 /* XXX */ 120 #endif 121 122 #ifndef IMXUART_FREQ 123 #define IMXUART_FREQ (56900000) 124 #endif 125 126 /* 127 * Override cnmagic(9) macro before including <sys/systm.h>. 128 * We need to know if cn_check_magic triggered debugger, so set a flag. 129 * Callers of cn_check_magic must declare int cn_trapped = 0; 130 * XXX: this is *ugly*! 131 */ 132 #define cn_trap() \ 133 do { \ 134 console_debugger(); \ 135 cn_trapped = 1; \ 136 } while (/* CONSTCOND */ 0) 137 138 #include <sys/param.h> 139 #include <sys/systm.h> 140 #include <sys/ioctl.h> 141 #include <sys/select.h> 142 #include <sys/poll.h> 143 #include <sys/tty.h> 144 #include <sys/proc.h> 145 #include <sys/conf.h> 146 #include <sys/file.h> 147 #include <sys/uio.h> 148 #include <sys/kernel.h> 149 #include <sys/syslog.h> 150 #include <sys/device.h> 151 #include <sys/malloc.h> 152 #include <sys/timepps.h> 153 #include <sys/vnode.h> 154 #include <sys/kauth.h> 155 #include <sys/intr.h> 156 157 #include <sys/bus.h> 158 159 #include <arm/imx/imxuartreg.h> 160 #include <arm/imx/imxuartvar.h> 161 #include <dev/cons.h> 162 163 #ifndef IMXUART_RING_SIZE 164 #define IMXUART_RING_SIZE 2048 165 #endif 166 167 int imxuspeed(long, struct imxuart_baudrate_ratio *); 168 int imxuparam(struct tty *, struct termios *); 169 void imxustart(struct tty *); 170 int imxuhwiflow(struct tty *, int); 171 172 void imxuart_shutdown(struct imxuart_softc *); 173 void imxuart_loadchannelregs(struct imxuart_softc *); 174 void imxuart_hwiflow(struct imxuart_softc *); 175 void imxuart_break(struct imxuart_softc *, bool); 176 void imxuart_modem(struct imxuart_softc *, int); 177 void tiocm_to_imxu(struct imxuart_softc *, u_long, int); 178 int imxuart_to_tiocm(struct imxuart_softc *); 179 void imxuart_iflush(struct imxuart_softc *); 180 int imxuintr(void *); 181 182 int imxuart_common_getc(dev_t, struct imxuart_regs *); 183 void imxuart_common_putc(dev_t, struct imxuart_regs *, int); 184 185 186 int imxuart_init(struct imxuart_regs *, int, tcflag_t, int); 187 188 int imxucngetc(dev_t); 189 void imxucnputc(dev_t, int); 190 void imxucnpollc(dev_t, int); 191 192 static void imxuintr_read(struct imxuart_softc *); 193 static void imxuintr_send(struct imxuart_softc *); 194 195 static void imxuart_enable_debugport(struct imxuart_softc *); 196 static void imxuart_disable_all_interrupts(struct imxuart_softc *); 197 static void imxuart_control_rxint(struct imxuart_softc *, bool); 198 static void imxuart_control_txint(struct imxuart_softc *, bool); 199 static u_int imxuart_txfifo_space(struct imxuart_softc *sc); 200 201 static uint32_t cflag_to_ucr2(tcflag_t, uint32_t); 202 203 #define integrate static inline 204 void imxusoft(void *); 205 integrate void imxuart_rxsoft(struct imxuart_softc *, struct tty *); 206 integrate void imxuart_txsoft(struct imxuart_softc *, struct tty *); 207 integrate void imxuart_stsoft(struct imxuart_softc *, struct tty *); 208 integrate void imxuart_schedrx(struct imxuart_softc *); 209 void imxudiag(void *); 210 static void imxuart_load_speed(struct imxuart_softc *); 211 static void imxuart_load_params(struct imxuart_softc *); 212 integrate void imxuart_load_pendings(struct imxuart_softc *); 213 214 215 extern struct cfdriver imxuart_cd; 216 217 dev_type_open(imxuopen); 218 dev_type_close(imxuclose); 219 dev_type_read(imxuread); 220 dev_type_write(imxuwrite); 221 dev_type_ioctl(imxuioctl); 222 dev_type_stop(imxustop); 223 dev_type_tty(imxutty); 224 dev_type_poll(imxupoll); 225 226 const struct cdevsw imxcom_cdevsw = { 227 .d_open = imxuopen, 228 .d_close = imxuclose, 229 .d_read = imxuread, 230 .d_write = imxuwrite, 231 .d_ioctl = imxuioctl, 232 .d_stop = imxustop, 233 .d_tty = imxutty, 234 .d_poll = imxupoll, 235 .d_mmap = nommap, 236 .d_kqfilter = ttykqfilter, 237 .d_discard = nodiscard, 238 .d_flag = D_TTY 239 }; 240 241 /* 242 * Make this an option variable one can patch. 243 * But be warned: this must be a power of 2! 244 */ 245 u_int imxuart_rbuf_size = IMXUART_RING_SIZE; 246 247 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 248 u_int imxuart_rbuf_hiwat = (IMXUART_RING_SIZE * 1) / 4; 249 u_int imxuart_rbuf_lowat = (IMXUART_RING_SIZE * 3) / 4; 250 251 static struct imxuart_regs imxuconsregs; 252 static int imxuconsattached; 253 static int imxuconsrate; 254 static tcflag_t imxuconscflag; 255 static struct cnm_state imxuart_cnm_state; 256 257 u_int imxuart_freq = IMXUART_FREQ; 258 u_int imxuart_freqdiv = IMXUART_FREQDIV; 259 260 #ifdef KGDB 261 #include <sys/kgdb.h> 262 263 static struct imxuart_regs imxu_kgdb_regs; 264 static int imxu_kgdb_attached; 265 266 int imxuart_kgdb_getc(void *); 267 void imxuart_kgdb_putc(void *, int); 268 #endif /* KGDB */ 269 270 #define IMXUART_DIALOUT_MASK TTDIALOUT_MASK 271 272 #define IMXUART_UNIT(x) TTUNIT(x) 273 #define IMXUART_DIALOUT(x) TTDIALOUT(x) 274 275 #define IMXUART_ISALIVE(sc) ((sc)->enabled != 0 && \ 276 device_is_active((sc)->sc_dev)) 277 278 #define BR BUS_SPACE_BARRIER_READ 279 #define BW BUS_SPACE_BARRIER_WRITE 280 #define IMXUART_BARRIER(r, f) \ 281 bus_space_barrier((r)->ur_iot, (r)->ur_ioh, 0, IMX_UART_SIZE, (f)) 282 283 284 void 285 imxuart_attach_common(device_t parent, device_t self, 286 bus_space_tag_t iot, paddr_t iobase, size_t size, int intr, int flags) 287 { 288 struct imxuart_softc *sc = device_private(self); 289 struct imxuart_regs *regsp = &sc->sc_regs; 290 bus_space_handle_t ioh; 291 292 aprint_naive("\n"); 293 aprint_normal("\n"); 294 295 sc->sc_dev = self; 296 297 if (size <= 0) 298 size = IMX_UART_SIZE; 299 300 sc->sc_intr = intr; 301 regsp->ur_iot = iot; 302 regsp->ur_iobase = iobase; 303 304 if (bus_space_map(iot, regsp->ur_iobase, size, 0, &ioh)) { 305 return; 306 } 307 regsp->ur_ioh = ioh; 308 309 imxuart_attach_subr(sc); 310 } 311 312 void 313 imxuart_attach_subr(struct imxuart_softc *sc) 314 { 315 struct imxuart_regs *regsp = &sc->sc_regs; 316 bus_space_tag_t iot = regsp->ur_iot; 317 bus_space_handle_t ioh = regsp->ur_ioh; 318 struct tty *tp; 319 320 callout_init(&sc->sc_diag_callout, 0); 321 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 322 323 if (regsp->ur_iobase != imxuconsregs.ur_iobase) 324 imxuart_init(&sc->sc_regs, TTYDEF_SPEED, TTYDEF_CFLAG, false); 325 326 bus_space_read_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 4); 327 sc->sc_ucr2_d = sc->sc_ucr2; 328 329 /* Disable interrupts before configuring the device. */ 330 imxuart_disable_all_interrupts(sc); 331 332 if (regsp->ur_iobase == imxuconsregs.ur_iobase) { 333 imxuconsattached = 1; 334 335 /* Make sure the console is always "hardwired". */ 336 #if 0 337 delay(10000); /* wait for output to finish */ 338 #endif 339 SET(sc->sc_hwflags, IMXUART_HW_CONSOLE); 340 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 341 } 342 343 344 tp = tty_alloc(); 345 tp->t_oproc = imxustart; 346 tp->t_param = imxuparam; 347 tp->t_hwiflow = imxuhwiflow; 348 349 sc->sc_tty = tp; 350 sc->sc_rbuf = malloc(sizeof (*sc->sc_rbuf) * imxuart_rbuf_size, 351 M_DEVBUF, M_NOWAIT); 352 sc->sc_rbuf_size = imxuart_rbuf_size; 353 sc->sc_rbuf_in = sc->sc_rbuf_out = 0; 354 if (sc->sc_rbuf == NULL) { 355 aprint_error_dev(sc->sc_dev, 356 "unable to allocate ring buffer\n"); 357 return; 358 } 359 360 sc->sc_txfifo_len = 32; 361 sc->sc_txfifo_thresh = 16; /* when USR1.TRDY, fifo has space 362 * for this many characters */ 363 364 tty_attach(tp); 365 366 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 367 int maj; 368 369 /* locate the major number */ 370 maj = cdevsw_lookup_major(&imxcom_cdevsw); 371 372 if (maj != NODEVMAJOR) { 373 tp->t_dev = cn_tab->cn_dev = makedev(maj, 374 device_unit(sc->sc_dev)); 375 376 aprint_normal_dev(sc->sc_dev, "console\n"); 377 } 378 } 379 380 sc->sc_ih = intr_establish(sc->sc_intr, IPL_SERIAL, IST_LEVEL, 381 imxuintr, sc); 382 if (sc->sc_ih == NULL) 383 aprint_error_dev(sc->sc_dev, "intr_establish failed\n"); 384 385 #ifdef KGDB 386 /* 387 * Allow kgdb to "take over" this port. If this is 388 * not the console and is the kgdb device, it has 389 * exclusive use. If it's the console _and_ the 390 * kgdb device, it doesn't. 391 */ 392 if (regsp->ur_iobase == imxu_kgdb_regs.ur_iobase) { 393 if (!ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 394 imxu_kgdb_attached = 1; 395 396 SET(sc->sc_hwflags, IMXUART_HW_KGDB); 397 } 398 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 399 } 400 #endif 401 402 sc->sc_si = softint_establish(SOFTINT_SERIAL, imxusoft, sc); 403 404 #ifdef RND_COM 405 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 406 RND_TYPE_TTY, RND_FLAG_COLLECT_TIME | 407 RND_FLAG_ESTIMATE_TIME); 408 #endif 409 410 /* if there are no enable/disable functions, assume the device 411 is always enabled */ 412 if (!sc->enable) 413 sc->enabled = 1; 414 415 imxuart_enable_debugport(sc); 416 417 SET(sc->sc_hwflags, IMXUART_HW_DEV_OK); 418 419 //shutdownhook_establish(imxuart_shutdownhook, sc); 420 421 422 #if 0 423 { 424 uint32_t reg; 425 reg = bus_space_read_4(iot, ioh, IMX_UCR1); 426 reg |= IMX_UCR1_TXDMAEN | IMX_UCR1_RXDMAEN; 427 bus_space_write_4(iot, ioh, IMX_UCR1, reg); 428 } 429 #endif 430 } 431 432 /* 433 * baudrate = RefFreq / (16 * (UMBR + 1)/(UBIR + 1)) 434 * 435 * (UBIR + 1) / (UBMR + 1) = (16 * BaurdRate) / RefFreq 436 */ 437 438 static long 439 gcd(long m, long n) 440 { 441 442 if (m < n) 443 return gcd(n, m); 444 445 if (n <= 0) 446 return m; 447 return gcd(n, m % n); 448 } 449 450 int 451 imxuspeed(long speed, struct imxuart_baudrate_ratio *ratio) 452 { 453 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 454 long b = 16 * speed; 455 long f = imxuart_freq / imxuart_freqdiv; 456 long d; 457 int err = 0; 458 459 /* reduce b/f */ 460 while ((f > (1<<16) || b > (1<<16)) && (d = gcd(f, b)) > 1) { 461 f /= d; 462 b /= d; 463 } 464 465 466 while (f > (1<<16) || b > (1<<16)) { 467 f /= 2; 468 b /= 2; 469 } 470 if (f <= 0 || b <= 0) 471 return -1; 472 473 #ifdef DIAGNOSTIC 474 err = divrnd(((uint64_t)imxuart_freq) * 1000 / imxuart_freqdiv, 475 (uint64_t)speed * 16 * f / b) - 1000; 476 if (err < 0) 477 err = -err; 478 #endif 479 480 ratio->numerator = b-1; 481 ratio->modulator = f-1; 482 483 if (err > IMXUART_TOLERANCE) 484 return -1; 485 486 return 0; 487 #undef divrnd 488 } 489 490 #ifdef IMXUART_DEBUG 491 int imxuart_debug = 0; 492 493 void imxustatus(struct imxuart_softc *, const char *); 494 void 495 imxustatus(struct imxuart_softc *sc, const char *str) 496 { 497 struct tty *tp = sc->sc_tty; 498 499 aprint_normal_dev(sc->sc_dev, 500 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 501 str, 502 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 503 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 504 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 505 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 506 sc->sc_tx_stopped ? '+' : '-'); 507 508 aprint_normal_dev(sc->sc_dev, 509 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 510 str, 511 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 512 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 513 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 514 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 515 sc->sc_rx_flags); 516 } 517 #endif 518 519 #if 0 520 int 521 imxuart_detach(device_t self, int flags) 522 { 523 struct imxuart_softc *sc = device_private(self); 524 int maj, mn; 525 526 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) 527 return EBUSY; 528 529 /* locate the major number */ 530 maj = cdevsw_lookup_major(&imxcom_cdevsw); 531 532 /* Nuke the vnodes for any open instances. */ 533 mn = device_unit(self); 534 vdevgone(maj, mn, mn, VCHR); 535 536 mn |= IMXUART_DIALOUT_MASK; 537 vdevgone(maj, mn, mn, VCHR); 538 539 if (sc->sc_rbuf == NULL) { 540 /* 541 * Ring buffer allocation failed in the imxuart_attach_subr, 542 * only the tty is allocated, and nothing else. 543 */ 544 tty_free(sc->sc_tty); 545 return 0; 546 } 547 548 /* Free the receive buffer. */ 549 free(sc->sc_rbuf, M_DEVBUF); 550 551 /* Detach and free the tty. */ 552 tty_detach(sc->sc_tty); 553 tty_free(sc->sc_tty); 554 555 /* Unhook the soft interrupt handler. */ 556 softint_disestablish(sc->sc_si); 557 558 #ifdef RND_COM 559 /* Unhook the entropy source. */ 560 rnd_detach_source(&sc->rnd_source); 561 #endif 562 callout_destroy(&sc->sc_diag_callout); 563 564 /* Destroy the lock. */ 565 mutex_destroy(&sc->sc_lock); 566 567 return (0); 568 } 569 #endif 570 571 #ifdef notyet 572 int 573 imxuart_activate(device_t self, enum devact act) 574 { 575 struct imxuart_softc *sc = device_private(self); 576 int rv = 0; 577 578 switch (act) { 579 case DVACT_ACTIVATE: 580 rv = EOPNOTSUPP; 581 break; 582 583 case DVACT_DEACTIVATE: 584 if (sc->sc_hwflags & (IMXUART_HW_CONSOLE|IMXUART_HW_KGDB)) { 585 rv = EBUSY; 586 break; 587 } 588 589 if (sc->disable != NULL && sc->enabled != 0) { 590 (*sc->disable)(sc); 591 sc->enabled = 0; 592 } 593 break; 594 } 595 596 return (rv); 597 } 598 #endif 599 600 void 601 imxuart_shutdown(struct imxuart_softc *sc) 602 { 603 struct tty *tp = sc->sc_tty; 604 605 mutex_spin_enter(&sc->sc_lock); 606 607 /* If we were asserting flow control, then deassert it. */ 608 SET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED); 609 imxuart_hwiflow(sc); 610 611 /* Clear any break condition set with TIOCSBRK. */ 612 imxuart_break(sc, false); 613 614 /* 615 * Hang up if necessary. Wait a bit, so the other side has time to 616 * notice even if we immediately open the port again. 617 * Avoid tsleeping above splhigh(). 618 */ 619 if (ISSET(tp->t_cflag, HUPCL)) { 620 imxuart_modem(sc, 0); 621 mutex_spin_exit(&sc->sc_lock); 622 /* XXX will only timeout */ 623 (void) kpause(ttclos, false, hz, NULL); 624 mutex_spin_enter(&sc->sc_lock); 625 } 626 627 /* Turn off interrupts. */ 628 imxuart_disable_all_interrupts(sc); 629 /* re-enable recv interrupt for console or kgdb port */ 630 imxuart_enable_debugport(sc); 631 632 mutex_spin_exit(&sc->sc_lock); 633 634 #ifdef notyet 635 if (sc->disable) { 636 #ifdef DIAGNOSTIC 637 if (!sc->enabled) 638 panic("imxuart_shutdown: not enabled?"); 639 #endif 640 (*sc->disable)(sc); 641 sc->enabled = 0; 642 } 643 #endif 644 } 645 646 int 647 imxuopen(dev_t dev, int flag, int mode, struct lwp *l) 648 { 649 struct imxuart_softc *sc; 650 struct tty *tp; 651 int s; 652 int error; 653 654 sc = device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 655 if (sc == NULL || !ISSET(sc->sc_hwflags, IMXUART_HW_DEV_OK) || 656 sc->sc_rbuf == NULL) 657 return (ENXIO); 658 659 if (!device_is_active(sc->sc_dev)) 660 return (ENXIO); 661 662 #ifdef KGDB 663 /* 664 * If this is the kgdb port, no other use is permitted. 665 */ 666 if (ISSET(sc->sc_hwflags, IMXUART_HW_KGDB)) 667 return (EBUSY); 668 #endif 669 670 tp = sc->sc_tty; 671 672 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 673 return (EBUSY); 674 675 s = spltty(); 676 677 /* 678 * Do the following iff this is a first open. 679 */ 680 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 681 struct termios t; 682 683 tp->t_dev = dev; 684 685 686 #ifdef notyet 687 if (sc->enable) { 688 if ((*sc->enable)(sc)) { 689 splx(s); 690 aprint_error_dev(sc->sc_dev, 691 "device enable failed\n"); 692 return (EIO); 693 } 694 sc->enabled = 1; 695 } 696 #endif 697 698 mutex_spin_enter(&sc->sc_lock); 699 700 imxuart_disable_all_interrupts(sc); 701 702 /* Fetch the current modem control status, needed later. */ 703 704 #ifdef IMXUART_PPS 705 /* Clear PPS capture state on first open. */ 706 mutex_spin_enter(&timecounter_lock); 707 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 708 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 709 pps_init(&sc->sc_pps_state); 710 mutex_spin_exit(&timecounter_lock); 711 #endif 712 713 mutex_spin_exit(&sc->sc_lock); 714 715 /* 716 * Initialize the termios status to the defaults. Add in the 717 * sticky bits from TIOCSFLAGS. 718 */ 719 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 720 t.c_ospeed = imxuconsrate; 721 t.c_cflag = imxuconscflag; 722 } else { 723 t.c_ospeed = TTYDEF_SPEED; 724 t.c_cflag = TTYDEF_CFLAG; 725 } 726 t.c_ispeed = t.c_ospeed; 727 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 728 SET(t.c_cflag, CLOCAL); 729 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 730 SET(t.c_cflag, CRTSCTS); 731 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 732 SET(t.c_cflag, MDMBUF); 733 /* Make sure imxuparam() will do something. */ 734 tp->t_ospeed = 0; 735 (void) imxuparam(tp, &t); 736 tp->t_iflag = TTYDEF_IFLAG; 737 tp->t_oflag = TTYDEF_OFLAG; 738 tp->t_lflag = TTYDEF_LFLAG; 739 ttychars(tp); 740 ttsetwater(tp); 741 742 mutex_spin_enter(&sc->sc_lock); 743 744 /* 745 * Turn on DTR. We must always do this, even if carrier is not 746 * present, because otherwise we'd have to use TIOCSDTR 747 * immediately after setting CLOCAL, which applications do not 748 * expect. We always assert DTR while the device is open 749 * unless explicitly requested to deassert it. 750 */ 751 imxuart_modem(sc, 1); 752 753 /* Clear the input ring, and unblock. */ 754 sc->sc_rbuf_in = sc->sc_rbuf_out = 0; 755 imxuart_iflush(sc); 756 CLR(sc->sc_rx_flags, IMXUART_RX_ANY_BLOCK); 757 imxuart_hwiflow(sc); 758 759 /* Turn on interrupts. */ 760 imxuart_control_rxint(sc, true); 761 762 #ifdef IMXUART_DEBUG 763 if (imxuart_debug) 764 imxustatus(sc, "imxuopen "); 765 #endif 766 767 mutex_spin_exit(&sc->sc_lock); 768 } 769 770 splx(s); 771 772 #if 0 773 error = ttyopen(tp, IMXUART_DIALOUT(dev), ISSET(flag, O_NONBLOCK)); 774 #else 775 error = ttyopen(tp, 1, ISSET(flag, O_NONBLOCK)); 776 #endif 777 if (error) 778 goto bad; 779 780 error = (*tp->t_linesw->l_open)(dev, tp); 781 if (error) 782 goto bad; 783 784 return (0); 785 786 bad: 787 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 788 /* 789 * We failed to open the device, and nobody else had it opened. 790 * Clean up the state as appropriate. 791 */ 792 imxuart_shutdown(sc); 793 } 794 795 return (error); 796 } 797 798 int 799 imxuclose(dev_t dev, int flag, int mode, struct lwp *l) 800 { 801 struct imxuart_softc *sc = 802 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 803 struct tty *tp = sc->sc_tty; 804 805 /* XXX This is for cons.c. */ 806 if (!ISSET(tp->t_state, TS_ISOPEN)) 807 return (0); 808 809 (*tp->t_linesw->l_close)(tp, flag); 810 ttyclose(tp); 811 812 if (IMXUART_ISALIVE(sc) == 0) 813 return (0); 814 815 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 816 /* 817 * Although we got a last close, the device may still be in 818 * use; e.g. if this was the dialout node, and there are still 819 * processes waiting for carrier on the non-dialout node. 820 */ 821 imxuart_shutdown(sc); 822 } 823 824 return (0); 825 } 826 827 int 828 imxuread(dev_t dev, struct uio *uio, int flag) 829 { 830 struct imxuart_softc *sc = 831 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 832 struct tty *tp = sc->sc_tty; 833 834 if (IMXUART_ISALIVE(sc) == 0) 835 return (EIO); 836 837 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 838 } 839 840 int 841 imxuwrite(dev_t dev, struct uio *uio, int flag) 842 { 843 struct imxuart_softc *sc = 844 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 845 struct tty *tp = sc->sc_tty; 846 847 if (IMXUART_ISALIVE(sc) == 0) 848 return (EIO); 849 850 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 851 } 852 853 int 854 imxupoll(dev_t dev, int events, struct lwp *l) 855 { 856 struct imxuart_softc *sc = 857 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 858 struct tty *tp = sc->sc_tty; 859 860 if (IMXUART_ISALIVE(sc) == 0) 861 return (POLLHUP); 862 863 return ((*tp->t_linesw->l_poll)(tp, events, l)); 864 } 865 866 struct tty * 867 imxutty(dev_t dev) 868 { 869 struct imxuart_softc *sc = 870 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 871 struct tty *tp = sc->sc_tty; 872 873 return (tp); 874 } 875 876 int 877 imxuioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 878 { 879 struct imxuart_softc *sc; 880 struct tty *tp; 881 int error; 882 883 sc = device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 884 if (sc == NULL) 885 return ENXIO; 886 if (IMXUART_ISALIVE(sc) == 0) 887 return (EIO); 888 889 tp = sc->sc_tty; 890 891 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 892 if (error != EPASSTHROUGH) 893 return (error); 894 895 error = ttioctl(tp, cmd, data, flag, l); 896 if (error != EPASSTHROUGH) 897 return (error); 898 899 error = 0; 900 switch (cmd) { 901 case TIOCSFLAGS: 902 error = kauth_authorize_device_tty(l->l_cred, 903 KAUTH_DEVICE_TTY_PRIVSET, tp); 904 break; 905 default: 906 /* nothing */ 907 break; 908 } 909 if (error) { 910 return error; 911 } 912 913 mutex_spin_enter(&sc->sc_lock); 914 915 switch (cmd) { 916 case TIOCSBRK: 917 imxuart_break(sc, true); 918 break; 919 920 case TIOCCBRK: 921 imxuart_break(sc, false); 922 break; 923 924 case TIOCSDTR: 925 imxuart_modem(sc, 1); 926 break; 927 928 case TIOCCDTR: 929 imxuart_modem(sc, 0); 930 break; 931 932 case TIOCGFLAGS: 933 *(int *)data = sc->sc_swflags; 934 break; 935 936 case TIOCSFLAGS: 937 sc->sc_swflags = *(int *)data; 938 break; 939 940 case TIOCMSET: 941 case TIOCMBIS: 942 case TIOCMBIC: 943 tiocm_to_imxu(sc, cmd, *(int *)data); 944 break; 945 946 case TIOCMGET: 947 *(int *)data = imxuart_to_tiocm(sc); 948 break; 949 950 #ifdef notyet 951 case PPS_IOC_CREATE: 952 case PPS_IOC_DESTROY: 953 case PPS_IOC_GETPARAMS: 954 case PPS_IOC_SETPARAMS: 955 case PPS_IOC_GETCAP: 956 case PPS_IOC_FETCH: 957 #ifdef PPS_SYNC 958 case PPS_IOC_KCBIND: 959 #endif 960 mutex_spin_enter(&timecounter_lock); 961 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 962 mutex_spin_exit(&timecounter_lock); 963 break; 964 965 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 966 mutex_spin_enter(&timecounter_lock); 967 #ifndef PPS_TRAILING_EDGE 968 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 969 &sc->sc_pps_state.ppsinfo.assert_timestamp); 970 #else 971 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 972 &sc->sc_pps_state.ppsinfo.clear_timestamp); 973 #endif 974 mutex_spin_exit(&timecounter_lock); 975 break; 976 #endif 977 978 default: 979 error = EPASSTHROUGH; 980 break; 981 } 982 983 mutex_spin_exit(&sc->sc_lock); 984 985 #ifdef IMXUART_DEBUG 986 if (imxuart_debug) 987 imxustatus(sc, "imxuioctl "); 988 #endif 989 990 return (error); 991 } 992 993 integrate void 994 imxuart_schedrx(struct imxuart_softc *sc) 995 { 996 sc->sc_rx_ready = 1; 997 998 /* Wake up the poller. */ 999 softint_schedule(sc->sc_si); 1000 } 1001 1002 void 1003 imxuart_break(struct imxuart_softc *sc, bool onoff) 1004 { 1005 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1006 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1007 1008 if (onoff) 1009 SET(sc->sc_ucr1, IMX_UCR1_SNDBRK); 1010 else 1011 CLR(sc->sc_ucr1, IMX_UCR1_SNDBRK); 1012 1013 bus_space_write_4(iot, ioh, IMX_UCR1, sc->sc_ucr1); 1014 } 1015 1016 void 1017 imxuart_modem(struct imxuart_softc *sc, int onoff) 1018 { 1019 #ifdef notyet 1020 if (sc->sc_mcr_dtr == 0) 1021 return; 1022 1023 if (onoff) 1024 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1025 else 1026 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1027 1028 if (!sc->sc_heldchange) { 1029 if (sc->sc_tx_busy) { 1030 sc->sc_heldtbc = sc->sc_tbc; 1031 sc->sc_tbc = 0; 1032 sc->sc_heldchange = 1; 1033 } else 1034 imxuart_loadchannelregs(sc); 1035 } 1036 #endif 1037 } 1038 1039 /* 1040 * RTS output is controlled by UCR2.CTS bit. 1041 * DTR output is controlled by UCR3.DSR bit. 1042 * (i.MX reference manual uses names in DCE mode) 1043 * 1044 * note: if UCR2.CTSC == 1 for automatic HW flow control, UCR2.CTS is ignored. 1045 */ 1046 void 1047 tiocm_to_imxu(struct imxuart_softc *sc, u_long how, int ttybits) 1048 { 1049 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1050 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1051 1052 uint32_t ucr2 = sc->sc_ucr2_d; 1053 uint32_t ucr3 = sc->sc_ucr3; 1054 1055 uint32_t ucr2_mask = 0; 1056 uint32_t ucr3_mask = 0; 1057 1058 1059 if (ISSET(ttybits, TIOCM_DTR)) 1060 ucr3_mask = IMX_UCR3_DSR; 1061 if (ISSET(ttybits, TIOCM_RTS)) 1062 ucr2_mask = IMX_UCR2_CTS; 1063 1064 switch (how) { 1065 case TIOCMBIC: 1066 CLR(ucr2, ucr2_mask); 1067 CLR(ucr3, ucr3_mask); 1068 break; 1069 1070 case TIOCMBIS: 1071 SET(ucr2, ucr2_mask); 1072 SET(ucr3, ucr3_mask); 1073 break; 1074 1075 case TIOCMSET: 1076 CLR(ucr2, ucr2_mask); 1077 CLR(ucr3, ucr3_mask); 1078 SET(ucr2, ucr2_mask); 1079 SET(ucr3, ucr3_mask); 1080 break; 1081 } 1082 1083 if (ucr3 != sc->sc_ucr3) { 1084 bus_space_write_4(iot, ioh, IMX_UCR3, ucr3); 1085 sc->sc_ucr3 = ucr3; 1086 } 1087 1088 if (ucr2 == sc->sc_ucr2_d) 1089 return; 1090 1091 sc->sc_ucr2_d = ucr2; 1092 /* update CTS bit only */ 1093 ucr2 = (sc->sc_ucr2 & ~IMX_UCR2_CTS) | 1094 (ucr2 & IMX_UCR2_CTS); 1095 1096 bus_space_write_4(iot, ioh, IMX_UCR2, ucr2); 1097 sc->sc_ucr2 = ucr2; 1098 } 1099 1100 int 1101 imxuart_to_tiocm(struct imxuart_softc *sc) 1102 { 1103 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1104 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1105 int ttybits = 0; 1106 uint32_t usr[2]; 1107 1108 if (ISSET(sc->sc_ucr3, IMX_UCR3_DSR)) 1109 SET(ttybits, TIOCM_DTR); 1110 if (ISSET(sc->sc_ucr2, IMX_UCR2_CTS)) 1111 SET(ttybits, TIOCM_RTS); 1112 1113 bus_space_read_region_4(iot, ioh, IMX_USR1, usr, 2); 1114 1115 if (ISSET(usr[0], IMX_USR1_RTSS)) 1116 SET(ttybits, TIOCM_CTS); 1117 1118 if (ISSET(usr[1], IMX_USR2_DCDIN)) 1119 SET(ttybits, TIOCM_CD); 1120 1121 #if 0 1122 /* XXXbsh: I couldn't find the way to read ipp_uart_dsr_dte_i signal, 1123 although there are bits in UART registers to detect delta of DSR. 1124 */ 1125 if (ISSET(imxubits, MSR_DSR)) 1126 SET(ttybits, TIOCM_DSR); 1127 #endif 1128 1129 if (ISSET(usr[1], IMX_USR2_RIIN)) 1130 SET(ttybits, TIOCM_RI); 1131 1132 1133 #ifdef notyet 1134 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1135 SET(ttybits, TIOCM_LE); 1136 #endif 1137 1138 return (ttybits); 1139 } 1140 1141 static uint32_t 1142 cflag_to_ucr2(tcflag_t cflag, uint32_t oldval) 1143 { 1144 uint32_t val = oldval; 1145 1146 CLR(val,IMX_UCR2_WS|IMX_UCR2_PREN|IMX_UCR2_PROE|IMX_UCR2_STPB); 1147 1148 switch (cflag & CSIZE) { 1149 case CS5: 1150 case CS6: 1151 /* not suppreted. use 7-bits */ 1152 case CS7: 1153 break; 1154 case CS8: 1155 SET(val, IMX_UCR2_WS); 1156 break; 1157 } 1158 1159 1160 if (ISSET(cflag, PARENB)) { 1161 SET(val, IMX_UCR2_PREN); 1162 1163 /* odd parity */ 1164 if (!ISSET(cflag, PARODD)) 1165 SET(val, IMX_UCR2_PROE); 1166 } 1167 1168 if (ISSET(cflag, CSTOPB)) 1169 SET(val, IMX_UCR2_STPB); 1170 1171 val |= IMX_UCR2_TXEN| IMX_UCR2_RXEN|IMX_UCR2_SRST; 1172 1173 return val; 1174 } 1175 1176 int 1177 imxuparam(struct tty *tp, struct termios *t) 1178 { 1179 struct imxuart_softc *sc = 1180 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1181 struct imxuart_baudrate_ratio ratio; 1182 uint32_t ucr2; 1183 bool change_speed = tp->t_ospeed != t->c_ospeed; 1184 1185 if (IMXUART_ISALIVE(sc) == 0) 1186 return (EIO); 1187 1188 /* Check requested parameters. */ 1189 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1190 return (EINVAL); 1191 1192 /* 1193 * For the console, always force CLOCAL and !HUPCL, so that the port 1194 * is always active. 1195 */ 1196 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1197 ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 1198 SET(t->c_cflag, CLOCAL); 1199 CLR(t->c_cflag, HUPCL); 1200 } 1201 1202 /* 1203 * If there were no changes, don't do anything. This avoids dropping 1204 * input and improves performance when all we did was frob things like 1205 * VMIN and VTIME. 1206 */ 1207 if ( !change_speed && tp->t_cflag == t->c_cflag) 1208 return (0); 1209 1210 if (change_speed) { 1211 /* calculate baudrate modulator value */ 1212 if (imxuspeed(t->c_ospeed, &ratio) < 0) 1213 return (EINVAL); 1214 sc->sc_ratio = ratio; 1215 } 1216 1217 ucr2 = cflag_to_ucr2(t->c_cflag, sc->sc_ucr2_d); 1218 1219 mutex_spin_enter(&sc->sc_lock); 1220 1221 #if 0 /* flow control stuff. not yet */ 1222 /* 1223 * If we're not in a mode that assumes a connection is present, then 1224 * ignore carrier changes. 1225 */ 1226 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1227 sc->sc_msr_dcd = 0; 1228 else 1229 sc->sc_msr_dcd = MSR_DCD; 1230 /* 1231 * Set the flow control pins depending on the current flow control 1232 * mode. 1233 */ 1234 if (ISSET(t->c_cflag, CRTSCTS)) { 1235 sc->sc_mcr_dtr = MCR_DTR; 1236 sc->sc_mcr_rts = MCR_RTS; 1237 sc->sc_msr_cts = MSR_CTS; 1238 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1239 } else if (ISSET(t->c_cflag, MDMBUF)) { 1240 /* 1241 * For DTR/DCD flow control, make sure we don't toggle DTR for 1242 * carrier detection. 1243 */ 1244 sc->sc_mcr_dtr = 0; 1245 sc->sc_mcr_rts = MCR_DTR; 1246 sc->sc_msr_cts = MSR_DCD; 1247 sc->sc_efr = 0; 1248 } else { 1249 /* 1250 * If no flow control, then always set RTS. This will make 1251 * the other side happy if it mistakenly thinks we're doing 1252 * RTS/CTS flow control. 1253 */ 1254 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1255 sc->sc_mcr_rts = 0; 1256 sc->sc_msr_cts = 0; 1257 sc->sc_efr = 0; 1258 if (ISSET(sc->sc_mcr, MCR_DTR)) 1259 SET(sc->sc_mcr, MCR_RTS); 1260 else 1261 CLR(sc->sc_mcr, MCR_RTS); 1262 } 1263 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1264 #endif 1265 1266 /* And copy to tty. */ 1267 tp->t_ispeed = t->c_ospeed; 1268 tp->t_ospeed = t->c_ospeed; 1269 tp->t_cflag = t->c_cflag; 1270 1271 if (!change_speed && ucr2 == sc->sc_ucr2_d) { 1272 /* noop */ 1273 } 1274 else if (!sc->sc_pending && !sc->sc_tx_busy) { 1275 if (ucr2 != sc->sc_ucr2_d) { 1276 sc->sc_ucr2_d = ucr2; 1277 imxuart_load_params(sc); 1278 } 1279 if (change_speed) 1280 imxuart_load_speed(sc); 1281 } 1282 else { 1283 if (!sc->sc_pending) { 1284 sc->sc_heldtbc = sc->sc_tbc; 1285 sc->sc_tbc = 0; 1286 } 1287 sc->sc_pending |= 1288 (ucr2 == sc->sc_ucr2_d ? 0 : IMXUART_PEND_PARAM) | 1289 (change_speed ? 0 : IMXUART_PEND_SPEED); 1290 sc->sc_ucr2_d = ucr2; 1291 } 1292 1293 if (!ISSET(t->c_cflag, CHWFLOW)) { 1294 /* Disable the high water mark. */ 1295 sc->sc_r_hiwat = 0; 1296 sc->sc_r_lowat = 0; 1297 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED)) { 1298 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED); 1299 imxuart_schedrx(sc); 1300 } 1301 if (ISSET(sc->sc_rx_flags, 1302 IMXUART_RX_TTY_BLOCKED|IMXUART_RX_IBUF_BLOCKED)) { 1303 CLR(sc->sc_rx_flags, 1304 IMXUART_RX_TTY_BLOCKED|IMXUART_RX_IBUF_BLOCKED); 1305 imxuart_hwiflow(sc); 1306 } 1307 } else { 1308 sc->sc_r_hiwat = imxuart_rbuf_hiwat; 1309 sc->sc_r_lowat = imxuart_rbuf_lowat; 1310 } 1311 1312 mutex_spin_exit(&sc->sc_lock); 1313 1314 #if 0 1315 /* 1316 * Update the tty layer's idea of the carrier bit, in case we changed 1317 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1318 * explicit request. 1319 */ 1320 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1321 #else 1322 /* XXX: always report that we have DCD */ 1323 (void) (*tp->t_linesw->l_modem)(tp, 1); 1324 #endif 1325 1326 #ifdef IMXUART_DEBUG 1327 if (imxuart_debug) 1328 imxustatus(sc, "imxuparam "); 1329 #endif 1330 1331 if (!ISSET(t->c_cflag, CHWFLOW)) { 1332 if (sc->sc_tx_stopped) { 1333 sc->sc_tx_stopped = 0; 1334 imxustart(tp); 1335 } 1336 } 1337 1338 return (0); 1339 } 1340 1341 void 1342 imxuart_iflush(struct imxuart_softc *sc) 1343 { 1344 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1345 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1346 #ifdef DIAGNOSTIC 1347 uint32_t reg = 0xffff; 1348 #endif 1349 int timo; 1350 1351 timo = 50000; 1352 /* flush any pending I/O */ 1353 while (ISSET(bus_space_read_4(iot, ioh, IMX_USR2), IMX_USR2_RDR) 1354 && --timo) 1355 #ifdef DIAGNOSTIC 1356 reg = 1357 #else 1358 (void) 1359 #endif 1360 bus_space_read_4(iot, ioh, IMX_URXD); 1361 #ifdef DIAGNOSTIC 1362 if (!timo) 1363 aprint_error_dev(sc->sc_dev, "imxuart_iflush timeout %02x\n", reg); 1364 #endif 1365 } 1366 1367 int 1368 imxuhwiflow(struct tty *tp, int block) 1369 { 1370 struct imxuart_softc *sc = 1371 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1372 1373 if (IMXUART_ISALIVE(sc) == 0) 1374 return (0); 1375 1376 #ifdef notyet 1377 if (sc->sc_mcr_rts == 0) 1378 return (0); 1379 #endif 1380 1381 mutex_spin_enter(&sc->sc_lock); 1382 1383 if (block) { 1384 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) { 1385 SET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED); 1386 imxuart_hwiflow(sc); 1387 } 1388 } else { 1389 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED)) { 1390 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED); 1391 imxuart_schedrx(sc); 1392 } 1393 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) { 1394 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED); 1395 imxuart_hwiflow(sc); 1396 } 1397 } 1398 1399 mutex_spin_exit(&sc->sc_lock); 1400 return (1); 1401 } 1402 1403 /* 1404 * (un)block input via hw flowcontrol 1405 */ 1406 void 1407 imxuart_hwiflow(struct imxuart_softc *sc) 1408 { 1409 #ifdef notyet 1410 struct imxuart_regs *regsp= &sc->sc_regs; 1411 1412 if (sc->sc_mcr_rts == 0) 1413 return; 1414 1415 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1416 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1417 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1418 } else { 1419 SET(sc->sc_mcr, sc->sc_mcr_rts); 1420 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1421 } 1422 UR_WRITE_1(regsp, IMXUART_REG_MCR, sc->sc_mcr_active); 1423 #endif 1424 } 1425 1426 1427 void 1428 imxustart(struct tty *tp) 1429 { 1430 struct imxuart_softc *sc = 1431 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1432 int s; 1433 u_char *tba; 1434 int tbc; 1435 u_int n; 1436 u_int space; 1437 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1438 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1439 1440 if (IMXUART_ISALIVE(sc) == 0) 1441 return; 1442 1443 s = spltty(); 1444 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1445 goto out; 1446 if (sc->sc_tx_stopped) 1447 goto out; 1448 if (!ttypull(tp)) 1449 goto out; 1450 1451 /* Grab the first contiguous region of buffer space. */ 1452 tba = tp->t_outq.c_cf; 1453 tbc = ndqb(&tp->t_outq, 0); 1454 1455 mutex_spin_enter(&sc->sc_lock); 1456 1457 sc->sc_tba = tba; 1458 sc->sc_tbc = tbc; 1459 1460 SET(tp->t_state, TS_BUSY); 1461 sc->sc_tx_busy = 1; 1462 1463 space = imxuart_txfifo_space(sc); 1464 n = MIN(sc->sc_tbc, space); 1465 1466 bus_space_write_multi_1(iot, ioh, IMX_UTXD, sc->sc_tba, n); 1467 sc->sc_tbc -= n; 1468 sc->sc_tba += n; 1469 1470 /* Enable transmit completion interrupts */ 1471 imxuart_control_txint(sc, true); 1472 1473 mutex_spin_exit(&sc->sc_lock); 1474 out: 1475 splx(s); 1476 return; 1477 } 1478 1479 /* 1480 * Stop output on a line. 1481 */ 1482 void 1483 imxustop(struct tty *tp, int flag) 1484 { 1485 struct imxuart_softc *sc = 1486 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1487 1488 mutex_spin_enter(&sc->sc_lock); 1489 if (ISSET(tp->t_state, TS_BUSY)) { 1490 /* Stop transmitting at the next chunk. */ 1491 sc->sc_tbc = 0; 1492 sc->sc_heldtbc = 0; 1493 if (!ISSET(tp->t_state, TS_TTSTOP)) 1494 SET(tp->t_state, TS_FLUSH); 1495 } 1496 mutex_spin_exit(&sc->sc_lock); 1497 } 1498 1499 void 1500 imxudiag(void *arg) 1501 { 1502 #ifdef notyet 1503 struct imxuart_softc *sc = arg; 1504 int overflows, floods; 1505 1506 mutex_spin_enter(&sc->sc_lock); 1507 overflows = sc->sc_overflows; 1508 sc->sc_overflows = 0; 1509 floods = sc->sc_floods; 1510 sc->sc_floods = 0; 1511 sc->sc_errors = 0; 1512 mutex_spin_exit(&sc->sc_lock); 1513 1514 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1515 device_xname(sc->sc_dev), 1516 overflows, overflows == 1 ? "" : "s", 1517 floods, floods == 1 ? "" : "s"); 1518 #endif 1519 } 1520 1521 integrate void 1522 imxuart_rxsoft(struct imxuart_softc *sc, struct tty *tp) 1523 { 1524 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1525 u_int cc, scc, outp; 1526 uint16_t data; 1527 u_int code; 1528 1529 scc = cc = IMXUART_RBUF_AVAIL(sc); 1530 1531 #if 0 1532 if (cc == imxuart_rbuf_size-1) { 1533 sc->sc_floods++; 1534 if (sc->sc_errors++ == 0) 1535 callout_reset(&sc->sc_diag_callout, 60 * hz, 1536 imxudiag, sc); 1537 } 1538 #endif 1539 1540 /* If not yet open, drop the entire buffer content here */ 1541 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1542 sc->sc_rbuf_out = sc->sc_rbuf_in; 1543 cc = 0; 1544 } 1545 1546 outp = sc->sc_rbuf_out; 1547 1548 #define ERRBITS (IMX_URXD_PRERR|IMX_URXD_BRK|IMX_URXD_FRMERR|IMX_URXD_OVRRUN) 1549 1550 while (cc) { 1551 data = sc->sc_rbuf[outp]; 1552 code = data & IMX_URXD_RX_DATA; 1553 if (ISSET(data, ERRBITS)) { 1554 if (sc->sc_errors.err == 0) 1555 callout_reset(&sc->sc_diag_callout, 1556 60 * hz, imxudiag, sc); 1557 if (ISSET(data, IMX_URXD_OVRRUN)) 1558 sc->sc_errors.ovrrun++; 1559 if (ISSET(data, IMX_URXD_BRK)) { 1560 sc->sc_errors.brk++; 1561 SET(code, TTY_FE); 1562 } 1563 if (ISSET(data, IMX_URXD_FRMERR)) { 1564 sc->sc_errors.frmerr++; 1565 SET(code, TTY_FE); 1566 } 1567 if (ISSET(data, IMX_URXD_PRERR)) { 1568 sc->sc_errors.prerr++; 1569 SET(code, TTY_PE); 1570 } 1571 } 1572 if ((*rint)(code, tp) == -1) { 1573 /* 1574 * The line discipline's buffer is out of space. 1575 */ 1576 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) { 1577 /* 1578 * We're either not using flow control, or the 1579 * line discipline didn't tell us to block for 1580 * some reason. Either way, we have no way to 1581 * know when there's more space available, so 1582 * just drop the rest of the data. 1583 */ 1584 sc->sc_rbuf_out = sc->sc_rbuf_in; 1585 cc = 0; 1586 } else { 1587 /* 1588 * Don't schedule any more receive processing 1589 * until the line discipline tells us there's 1590 * space available (through imxuhwiflow()). 1591 * Leave the rest of the data in the input 1592 * buffer. 1593 */ 1594 SET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED); 1595 } 1596 break; 1597 } 1598 outp = IMXUART_RBUF_INC(sc, outp, 1); 1599 cc--; 1600 } 1601 1602 if (cc != scc) { 1603 sc->sc_rbuf_out = outp; 1604 mutex_spin_enter(&sc->sc_lock); 1605 1606 cc = IMXUART_RBUF_SPACE(sc); 1607 1608 /* Buffers should be ok again, release possible block. */ 1609 if (cc >= sc->sc_r_lowat) { 1610 if (ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_OVERFLOWED)) { 1611 CLR(sc->sc_rx_flags, IMXUART_RX_IBUF_OVERFLOWED); 1612 imxuart_control_rxint(sc, true); 1613 } 1614 if (ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED)) { 1615 CLR(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED); 1616 imxuart_hwiflow(sc); 1617 } 1618 } 1619 mutex_spin_exit(&sc->sc_lock); 1620 } 1621 } 1622 1623 integrate void 1624 imxuart_txsoft(struct imxuart_softc *sc, struct tty *tp) 1625 { 1626 1627 CLR(tp->t_state, TS_BUSY); 1628 if (ISSET(tp->t_state, TS_FLUSH)) 1629 CLR(tp->t_state, TS_FLUSH); 1630 else 1631 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1632 (*tp->t_linesw->l_start)(tp); 1633 } 1634 1635 integrate void 1636 imxuart_stsoft(struct imxuart_softc *sc, struct tty *tp) 1637 { 1638 #ifdef notyet 1639 u_char msr, delta; 1640 1641 mutex_spin_enter(&sc->sc_lock); 1642 msr = sc->sc_msr; 1643 delta = sc->sc_msr_delta; 1644 sc->sc_msr_delta = 0; 1645 mutex_spin_exit(&sc->sc_lock); 1646 1647 if (ISSET(delta, sc->sc_msr_dcd)) { 1648 /* 1649 * Inform the tty layer that carrier detect changed. 1650 */ 1651 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1652 } 1653 1654 if (ISSET(delta, sc->sc_msr_cts)) { 1655 /* Block or unblock output according to flow control. */ 1656 if (ISSET(msr, sc->sc_msr_cts)) { 1657 sc->sc_tx_stopped = 0; 1658 (*tp->t_linesw->l_start)(tp); 1659 } else { 1660 sc->sc_tx_stopped = 1; 1661 } 1662 } 1663 1664 #endif 1665 #ifdef IMXUART_DEBUG 1666 if (imxuart_debug) 1667 imxustatus(sc, "imxuart_stsoft"); 1668 #endif 1669 } 1670 1671 void 1672 imxusoft(void *arg) 1673 { 1674 struct imxuart_softc *sc = arg; 1675 struct tty *tp; 1676 1677 if (IMXUART_ISALIVE(sc) == 0) 1678 return; 1679 1680 tp = sc->sc_tty; 1681 1682 if (sc->sc_rx_ready) { 1683 sc->sc_rx_ready = 0; 1684 imxuart_rxsoft(sc, tp); 1685 } 1686 1687 if (sc->sc_st_check) { 1688 sc->sc_st_check = 0; 1689 imxuart_stsoft(sc, tp); 1690 } 1691 1692 if (sc->sc_tx_done) { 1693 sc->sc_tx_done = 0; 1694 imxuart_txsoft(sc, tp); 1695 } 1696 } 1697 1698 int 1699 imxuintr(void *arg) 1700 { 1701 struct imxuart_softc *sc = arg; 1702 uint32_t usr1, usr2; 1703 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1704 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1705 1706 1707 if (IMXUART_ISALIVE(sc) == 0) 1708 return (0); 1709 1710 mutex_spin_enter(&sc->sc_lock); 1711 1712 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1713 1714 1715 do { 1716 bus_space_write_4(iot, ioh, IMX_USR2, 1717 usr2 & (IMX_USR2_BRCD|IMX_USR2_ORE)); 1718 if (usr2 & IMX_USR2_BRCD) { 1719 /* Break signal detected */ 1720 int cn_trapped = 0; 1721 1722 cn_check_magic(sc->sc_tty->t_dev, 1723 CNC_BREAK, imxuart_cnm_state); 1724 if (cn_trapped) 1725 continue; 1726 #if defined(KGDB) && !defined(DDB) 1727 if (ISSET(sc->sc_hwflags, IMXUART_HW_KGDB)) { 1728 kgdb_connect(1); 1729 continue; 1730 } 1731 #endif 1732 } 1733 1734 if (usr2 & IMX_USR2_RDR) 1735 imxuintr_read(sc); 1736 1737 #ifdef IMXUART_PPS 1738 { 1739 u_char msr, delta; 1740 1741 msr = CSR_READ_1(regsp, IMXUART_REG_MSR); 1742 delta = msr ^ sc->sc_msr; 1743 sc->sc_msr = msr; 1744 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 1745 (delta & MSR_DCD)) { 1746 mutex_spin_enter(&timecounter_lock); 1747 pps_capture(&sc->sc_pps_state); 1748 pps_event(&sc->sc_pps_state, 1749 (msr & MSR_DCD) ? 1750 PPS_CAPTUREASSERT : 1751 PPS_CAPTURECLEAR); 1752 mutex_spin_exit(&timecounter_lock); 1753 } 1754 } 1755 #endif 1756 1757 #ifdef notyet 1758 /* 1759 * Process normal status changes 1760 */ 1761 if (ISSET(delta, sc->sc_msr_mask)) { 1762 SET(sc->sc_msr_delta, delta); 1763 1764 /* 1765 * Stop output immediately if we lose the output 1766 * flow control signal or carrier detect. 1767 */ 1768 if (ISSET(~msr, sc->sc_msr_mask)) { 1769 sc->sc_tbc = 0; 1770 sc->sc_heldtbc = 0; 1771 #ifdef IMXUART_DEBUG 1772 if (imxuart_debug) 1773 imxustatus(sc, "imxuintr "); 1774 #endif 1775 } 1776 1777 sc->sc_st_check = 1; 1778 } 1779 #endif 1780 1781 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1782 } while (usr2 & (IMX_USR2_RDR|IMX_USR2_BRCD)); 1783 1784 usr1 = bus_space_read_4(iot, ioh, IMX_USR1); 1785 if (usr1 & IMX_USR1_TRDY) 1786 imxuintr_send(sc); 1787 1788 mutex_spin_exit(&sc->sc_lock); 1789 1790 /* Wake up the poller. */ 1791 softint_schedule(sc->sc_si); 1792 1793 #ifdef RND_COM 1794 rnd_add_uint32(&sc->rnd_source, iir | lsr); 1795 #endif 1796 1797 return (1); 1798 } 1799 1800 1801 /* 1802 * called when there is least one character in rxfifo 1803 * 1804 */ 1805 1806 static void 1807 imxuintr_read(struct imxuart_softc *sc) 1808 { 1809 int cc; 1810 uint16_t rd; 1811 uint32_t usr2; 1812 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1813 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1814 1815 cc = IMXUART_RBUF_SPACE(sc); 1816 1817 /* clear aging timer interrupt */ 1818 bus_space_write_4(iot, ioh, IMX_USR1, IMX_USR1_AGTIM); 1819 1820 while (cc > 0) { 1821 int cn_trapped = 0; 1822 1823 1824 sc->sc_rbuf[sc->sc_rbuf_in] = rd = 1825 bus_space_read_4(iot, ioh, IMX_URXD); 1826 1827 cn_check_magic(sc->sc_tty->t_dev, 1828 rd & 0xff, imxuart_cnm_state); 1829 1830 if (!cn_trapped) { 1831 #if defined(DDB) && defined(DDB_KEYCODE) 1832 /* 1833 * Temporary hack so that I can force the kernel into 1834 * the debugger via the serial port 1835 */ 1836 if ((rd & 0xff) == DDB_KEYCODE) 1837 Debugger(); 1838 #endif 1839 sc->sc_rbuf_in = IMXUART_RBUF_INC(sc, sc->sc_rbuf_in, 1); 1840 cc--; 1841 } 1842 1843 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1844 if (!(usr2 & IMX_USR2_RDR)) 1845 break; 1846 } 1847 1848 /* 1849 * Current string of incoming characters ended because 1850 * no more data was available or we ran out of space. 1851 * Schedule a receive event if any data was received. 1852 * If we're out of space, turn off receive interrupts. 1853 */ 1854 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED)) 1855 sc->sc_rx_ready = 1; 1856 /* 1857 * See if we are in danger of overflowing a buffer. If 1858 * so, use hardware flow control to ease the pressure. 1859 */ 1860 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED) && 1861 cc < sc->sc_r_hiwat) { 1862 sc->sc_rx_flags |= IMXUART_RX_IBUF_BLOCKED; 1863 imxuart_hwiflow(sc); 1864 } 1865 1866 /* 1867 * If we're out of space, disable receive interrupts 1868 * until the queue has drained a bit. 1869 */ 1870 if (!cc) { 1871 sc->sc_rx_flags |= IMXUART_RX_IBUF_OVERFLOWED; 1872 imxuart_control_rxint(sc, false); 1873 } 1874 } 1875 1876 1877 1878 /* 1879 * find how many chars we can put into tx-fifo 1880 */ 1881 static u_int 1882 imxuart_txfifo_space(struct imxuart_softc *sc) 1883 { 1884 uint32_t usr1, usr2; 1885 u_int cc; 1886 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1887 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1888 1889 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1890 if (usr2 & IMX_USR2_TXFE) 1891 cc = sc->sc_txfifo_len; 1892 else { 1893 usr1 = bus_space_read_4(iot, ioh, IMX_USR1); 1894 if (usr1 & IMX_USR1_TRDY) 1895 cc = sc->sc_txfifo_thresh; 1896 else 1897 cc = 0; 1898 } 1899 1900 return cc; 1901 } 1902 1903 void 1904 imxuintr_send(struct imxuart_softc *sc) 1905 { 1906 uint32_t usr2; 1907 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1908 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1909 int cc = 0; 1910 1911 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1912 1913 if (sc->sc_pending) { 1914 if (usr2 & IMX_USR2_TXFE) { 1915 imxuart_load_pendings(sc); 1916 sc->sc_tbc = sc->sc_heldtbc; 1917 sc->sc_heldtbc = 0; 1918 } 1919 else { 1920 /* wait for TX fifo empty */ 1921 imxuart_control_txint(sc, true); 1922 return; 1923 } 1924 } 1925 1926 cc = imxuart_txfifo_space(sc); 1927 cc = MIN(cc, sc->sc_tbc); 1928 1929 if (cc > 0) { 1930 bus_space_write_multi_1(iot, ioh, IMX_UTXD, sc->sc_tba, cc); 1931 sc->sc_tbc -= cc; 1932 sc->sc_tba += cc; 1933 } 1934 1935 if (sc->sc_tbc > 0) 1936 imxuart_control_txint(sc, true); 1937 else { 1938 /* no more chars to send. 1939 we don't need tx interrupt any more. */ 1940 imxuart_control_txint(sc, false); 1941 if (sc->sc_tx_busy) { 1942 sc->sc_tx_busy = 0; 1943 sc->sc_tx_done = 1; 1944 } 1945 } 1946 } 1947 1948 static void 1949 imxuart_disable_all_interrupts(struct imxuart_softc *sc) 1950 { 1951 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1952 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1953 1954 sc->sc_ucr1 &= ~IMXUART_INTRS_UCR1; 1955 sc->sc_ucr2 &= ~IMXUART_INTRS_UCR2; 1956 sc->sc_ucr3 &= ~IMXUART_INTRS_UCR3; 1957 sc->sc_ucr4 &= ~IMXUART_INTRS_UCR4; 1958 1959 1960 bus_space_write_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 4); 1961 } 1962 1963 static void 1964 imxuart_control_rxint(struct imxuart_softc *sc, bool enable) 1965 { 1966 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1967 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1968 uint32_t ucr1, ucr2; 1969 1970 ucr1 = sc->sc_ucr1; 1971 ucr2 = sc->sc_ucr2; 1972 1973 if (enable) { 1974 ucr1 |= IMX_UCR1_RRDYEN; 1975 ucr2 |= IMX_UCR2_ATEN; 1976 } 1977 else { 1978 ucr1 &= ~IMX_UCR1_RRDYEN; 1979 ucr2 &= ~IMX_UCR2_ATEN; 1980 } 1981 1982 if (ucr1 != sc->sc_ucr1 || ucr2 != sc->sc_ucr2) { 1983 sc->sc_ucr1 = ucr1; 1984 sc->sc_ucr2 = ucr2; 1985 bus_space_write_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 2); 1986 } 1987 } 1988 1989 static void 1990 imxuart_control_txint(struct imxuart_softc *sc, bool enable) 1991 { 1992 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1993 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1994 uint32_t ucr1; 1995 uint32_t mask; 1996 1997 /* if parameter change is pending, get interrupt when Tx fifo 1998 is completely empty. otherwise, get interrupt when txfifo 1999 has less characters than threshold */ 2000 mask = sc->sc_pending ? IMX_UCR1_TXMPTYEN : IMX_UCR1_TRDYEN; 2001 2002 ucr1 = sc->sc_ucr1; 2003 2004 CLR(ucr1, IMX_UCR1_TXMPTYEN|IMX_UCR1_TRDYEN); 2005 if (enable) 2006 SET(ucr1, mask); 2007 2008 if (ucr1 != sc->sc_ucr1) { 2009 bus_space_write_4(iot, ioh, IMX_UCR1, ucr1); 2010 sc->sc_ucr1 = ucr1; 2011 } 2012 } 2013 2014 2015 static void 2016 imxuart_load_params(struct imxuart_softc *sc) 2017 { 2018 uint32_t ucr2; 2019 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2020 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2021 2022 ucr2 = (sc->sc_ucr2_d & ~IMX_UCR2_ATEN) | 2023 (sc->sc_ucr2 & IMX_UCR2_ATEN); 2024 2025 bus_space_write_4(iot, ioh, IMX_UCR2, ucr2); 2026 sc->sc_ucr2 = ucr2; 2027 } 2028 2029 static void 2030 imxuart_load_speed(struct imxuart_softc *sc) 2031 { 2032 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2033 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2034 int n, rfdiv, ufcr; 2035 2036 #ifdef notyet 2037 /* 2038 * Set the FIFO threshold based on the receive speed. 2039 * 2040 * * If it's a low speed, it's probably a mouse or some other 2041 * interactive device, so set the threshold low. 2042 * * If it's a high speed, trim the trigger level down to prevent 2043 * overflows. 2044 * * Otherwise set it a bit higher. 2045 */ 2046 if (t->c_ospeed <= 1200) 2047 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 2048 else if (t->c_ospeed <= 38400) 2049 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 2050 else 2051 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 2052 #endif 2053 2054 n = 32 - sc->sc_txfifo_thresh; 2055 n = MAX(2, n); 2056 2057 rfdiv = IMX_UFCR_DIVIDER_TO_RFDIV(imxuart_freqdiv); 2058 2059 ufcr = (n << IMX_UFCR_TXTL_SHIFT) | 2060 (rfdiv << IMX_UFCR_RFDIV_SHIFT) | 2061 (16 << IMX_UFCR_RXTL_SHIFT); 2062 2063 /* keep DCE/DTE bit */ 2064 ufcr |= bus_space_read_4(iot, ioh, IMX_UFCR) & IMX_UFCR_DCEDTE; 2065 2066 bus_space_write_4(iot, ioh, IMX_UFCR, ufcr); 2067 2068 /* UBIR must updated before UBMR */ 2069 bus_space_write_4(iot, ioh, 2070 IMX_UBIR, sc->sc_ratio.numerator); 2071 bus_space_write_4(iot, ioh, 2072 IMX_UBMR, sc->sc_ratio.modulator); 2073 2074 2075 } 2076 2077 2078 static void 2079 imxuart_load_pendings(struct imxuart_softc *sc) 2080 { 2081 if (sc->sc_pending & IMXUART_PEND_PARAM) 2082 imxuart_load_params(sc); 2083 if (sc->sc_pending & IMXUART_PEND_SPEED) 2084 imxuart_load_speed(sc); 2085 sc->sc_pending = 0; 2086 } 2087 2088 #if defined(IMXUARTCONSOLE) || defined(KGDB) 2089 2090 /* 2091 * The following functions are polled getc and putc routines, shared 2092 * by the console and kgdb glue. 2093 * 2094 * The read-ahead code is so that you can detect pending in-band 2095 * cn_magic in polled mode while doing output rather than having to 2096 * wait until the kernel decides it needs input. 2097 */ 2098 2099 #define READAHEAD_RING_LEN 16 2100 static int imxuart_readahead[READAHEAD_RING_LEN]; 2101 static int imxuart_readahead_in = 0; 2102 static int imxuart_readahead_out = 0; 2103 #define READAHEAD_IS_EMPTY() (imxuart_readahead_in==imxuart_readahead_out) 2104 #define READAHEAD_IS_FULL() \ 2105 (((imxuart_readahead_in+1) & (READAHEAD_RING_LEN-1)) ==imxuart_readahead_out) 2106 2107 int 2108 imxuart_common_getc(dev_t dev, struct imxuart_regs *regsp) 2109 { 2110 int s = splserial(); 2111 u_char c; 2112 bus_space_tag_t iot = regsp->ur_iot; 2113 bus_space_handle_t ioh = regsp->ur_ioh; 2114 uint32_t usr2; 2115 2116 /* got a character from reading things earlier */ 2117 if (imxuart_readahead_in != imxuart_readahead_out) { 2118 2119 c = imxuart_readahead[imxuart_readahead_out]; 2120 imxuart_readahead_out = (imxuart_readahead_out + 1) & 2121 (READAHEAD_RING_LEN-1); 2122 splx(s); 2123 return (c); 2124 } 2125 2126 /* block until a character becomes available */ 2127 while (!((usr2 = bus_space_read_4(iot, ioh, IMX_USR2)) & IMX_USR2_RDR)) 2128 ; 2129 2130 c = 0xff & bus_space_read_4(iot, ioh, IMX_URXD); 2131 2132 { 2133 int __attribute__((__unused__))cn_trapped = 0; /* unused */ 2134 #ifdef DDB 2135 extern int db_active; 2136 if (!db_active) 2137 #endif 2138 cn_check_magic(dev, c, imxuart_cnm_state); 2139 } 2140 splx(s); 2141 return (c); 2142 } 2143 2144 void 2145 imxuart_common_putc(dev_t dev, struct imxuart_regs *regsp, int c) 2146 { 2147 int s = splserial(); 2148 int cin, timo; 2149 bus_space_tag_t iot = regsp->ur_iot; 2150 bus_space_handle_t ioh = regsp->ur_ioh; 2151 uint32_t usr2; 2152 2153 if (!READAHEAD_IS_FULL() && 2154 ((usr2 = bus_space_read_4(iot, ioh, IMX_USR2)) & IMX_USR2_RDR)) { 2155 2156 int __attribute__((__unused__))cn_trapped = 0; 2157 cin = bus_space_read_4(iot, ioh, IMX_URXD); 2158 cn_check_magic(dev, cin & 0xff, imxuart_cnm_state); 2159 imxuart_readahead_in = (imxuart_readahead_in + 1) & 2160 (READAHEAD_RING_LEN-1); 2161 } 2162 2163 /* wait for any pending transmission to finish */ 2164 timo = 150000; 2165 do { 2166 if (bus_space_read_4(iot, ioh, IMX_USR1) & IMX_USR1_TRDY) { 2167 bus_space_write_4(iot, ioh, IMX_UTXD, c); 2168 break; 2169 } 2170 } while(--timo > 0); 2171 2172 IMXUART_BARRIER(regsp, BR | BW); 2173 2174 splx(s); 2175 } 2176 #endif /* defined(IMXUARTCONSOLE) || defined(KGDB) */ 2177 2178 /* 2179 * Initialize UART 2180 */ 2181 int 2182 imxuart_init(struct imxuart_regs *regsp, int rate, tcflag_t cflag, int domap) 2183 { 2184 struct imxuart_baudrate_ratio ratio; 2185 int rfdiv = IMX_UFCR_DIVIDER_TO_RFDIV(imxuart_freqdiv); 2186 uint32_t ufcr; 2187 int error; 2188 2189 if (domap && (error = bus_space_map(regsp->ur_iot, regsp->ur_iobase, 2190 IMX_UART_SIZE, 0, ®sp->ur_ioh)) != 0) 2191 return error; 2192 2193 if (imxuspeed(rate, &ratio) < 0) 2194 return EINVAL; 2195 2196 /* UBIR must updated before UBMR */ 2197 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, 2198 IMX_UBIR, ratio.numerator); 2199 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, 2200 IMX_UBMR, ratio.modulator); 2201 2202 2203 /* XXX: DTREN, DPEC */ 2204 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR3, 2205 IMX_UCR3_DSR|IMX_UCR3_RXDMUXSEL); 2206 2207 ufcr = (8 << IMX_UFCR_TXTL_SHIFT) | (rfdiv << IMX_UFCR_RFDIV_SHIFT) | 2208 (1 << IMX_UFCR_RXTL_SHIFT); 2209 /* XXX: keep DCE/DTE bit */ 2210 ufcr |= bus_space_read_4(regsp->ur_iot, regsp->ur_ioh, IMX_UFCR) & 2211 IMX_UFCR_DCEDTE; 2212 2213 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UFCR, ufcr); 2214 2215 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_ONEMS, 2216 imxuart_freq / imxuart_freqdiv / 1000); 2217 2218 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR2, 2219 IMX_UCR2_IRTS| 2220 IMX_UCR2_CTSC| 2221 IMX_UCR2_WS|IMX_UCR2_TXEN| 2222 IMX_UCR2_RXEN|IMX_UCR2_SRST); 2223 /* clear status registers */ 2224 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_USR1, 0xffff); 2225 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_USR2, 0xffff); 2226 2227 2228 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR1, 2229 IMX_UCR1_UARTEN); 2230 2231 return (0); 2232 } 2233 2234 2235 #ifdef IMXUARTCONSOLE 2236 /* 2237 * Following are all routines needed for UART to act as console 2238 */ 2239 struct consdev imxucons = { 2240 NULL, NULL, imxucngetc, imxucnputc, imxucnpollc, NULL, NULL, NULL, 2241 NODEV, CN_NORMAL 2242 }; 2243 2244 2245 int 2246 imxuart_cnattach(bus_space_tag_t iot, paddr_t iobase, u_int rate, 2247 tcflag_t cflag) 2248 { 2249 struct imxuart_regs regs; 2250 int res; 2251 2252 regs.ur_iot = iot; 2253 regs.ur_iobase = iobase; 2254 2255 res = imxuart_init(®s, rate, cflag, true); 2256 if (res) 2257 return (res); 2258 2259 cn_tab = &imxucons; 2260 cn_init_magic(&imxuart_cnm_state); 2261 cn_set_magic("\047\001"); /* default magic is BREAK */ 2262 2263 imxuconsrate = rate; 2264 imxuconscflag = cflag; 2265 2266 imxuconsregs = regs; 2267 2268 return 0; 2269 } 2270 2271 int 2272 imxucngetc(dev_t dev) 2273 { 2274 return (imxuart_common_getc(dev, &imxuconsregs)); 2275 } 2276 2277 /* 2278 * Console kernel output character routine. 2279 */ 2280 void 2281 imxucnputc(dev_t dev, int c) 2282 { 2283 imxuart_common_putc(dev, &imxuconsregs, c); 2284 } 2285 2286 void 2287 imxucnpollc(dev_t dev, int on) 2288 { 2289 2290 imxuart_readahead_in = 0; 2291 imxuart_readahead_out = 0; 2292 } 2293 2294 #endif /* IMXUARTCONSOLE */ 2295 2296 #ifdef KGDB 2297 int 2298 imxuart_kgdb_attach(bus_space_tag_t iot, paddr_t iobase, u_int rate, 2299 tcflag_t cflag) 2300 { 2301 int res; 2302 2303 if (iot == imxuconsregs.ur_iot && 2304 iobase == imxuconsregs.ur_iobase) { 2305 #if !defined(DDB) 2306 return (EBUSY); /* cannot share with console */ 2307 #else 2308 imxu_kgdb_regs.ur_iot = iot; 2309 imxu_kgdb_regs.ur_ioh = imxuconsregs.ur_ioh; 2310 imxu_kgdb_regs.ur_iobase = iobase; 2311 #endif 2312 } else { 2313 imxu_kgdb_regs.ur_iot = iot; 2314 imxu_kgdb_regs.ur_iobase = iobase; 2315 2316 res = imxuart_init(&imxu_kgdb_regs, rate, cflag, true); 2317 if (res) 2318 return (res); 2319 2320 /* 2321 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2322 * expects this to be initialized 2323 */ 2324 cn_init_magic(&imxuart_cnm_state); 2325 cn_set_magic("\047\001"); 2326 } 2327 2328 kgdb_attach(imxuart_kgdb_getc, imxuart_kgdb_putc, &imxu_kgdb_regs); 2329 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2330 2331 return (0); 2332 } 2333 2334 /* ARGSUSED */ 2335 int 2336 imxuart_kgdb_getc(void *arg) 2337 { 2338 struct imxuart_regs *regs = arg; 2339 2340 return (imxuart_common_getc(NODEV, regs)); 2341 } 2342 2343 /* ARGSUSED */ 2344 void 2345 imxuart_kgdb_putc(void *arg, int c) 2346 { 2347 struct imxuart_regs *regs = arg; 2348 2349 imxuart_common_putc(NODEV, regs, c); 2350 } 2351 #endif /* KGDB */ 2352 2353 /* helper function to identify the imxu ports used by 2354 console or KGDB (and not yet autoconf attached) */ 2355 int 2356 imxuart_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2357 { 2358 bus_space_handle_t help; 2359 2360 if (!imxuconsattached && 2361 iot == imxuconsregs.ur_iot && iobase == imxuconsregs.ur_iobase) 2362 help = imxuconsregs.ur_ioh; 2363 #ifdef KGDB 2364 else if (!imxu_kgdb_attached && 2365 iot == imxu_kgdb_regs.ur_iot && iobase == imxu_kgdb_regs.ur_iobase) 2366 help = imxu_kgdb_regs.ur_ioh; 2367 #endif 2368 else 2369 return (0); 2370 2371 if (ioh) 2372 *ioh = help; 2373 return (1); 2374 } 2375 2376 #ifdef notyet 2377 2378 bool 2379 imxuart_cleanup(device_t self, int how) 2380 { 2381 /* 2382 * this routine exists to serve as a shutdown hook for systems that 2383 * have firmware which doesn't interact properly with a imxuart device in 2384 * FIFO mode. 2385 */ 2386 struct imxuart_softc *sc = device_private(self); 2387 2388 if (ISSET(sc->sc_hwflags, IMXUART_HW_FIFO)) 2389 UR_WRITE_1(&sc->sc_regs, IMXUART_REG_FIFO, 0); 2390 2391 return true; 2392 } 2393 #endif 2394 2395 #ifdef notyet 2396 bool 2397 imxuart_suspend(device_t self PMF_FN_ARGS) 2398 { 2399 struct imxuart_softc *sc = device_private(self); 2400 2401 UR_WRITE_1(&sc->sc_regs, IMXUART_REG_IER, 0); 2402 (void)CSR_READ_1(&sc->sc_regs, IMXUART_REG_IIR); 2403 2404 return true; 2405 } 2406 #endif 2407 2408 #ifdef notyet 2409 bool 2410 imxuart_resume(device_t self PMF_FN_ARGS) 2411 { 2412 struct imxuart_softc *sc = device_private(self); 2413 2414 mutex_spin_enter(&sc->sc_lock); 2415 imxuart_loadchannelregs(sc); 2416 mutex_spin_exit(&sc->sc_lock); 2417 2418 return true; 2419 } 2420 #endif 2421 2422 static void 2423 imxuart_enable_debugport(struct imxuart_softc *sc) 2424 { 2425 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2426 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2427 2428 if (sc->sc_hwflags & (IMXUART_HW_CONSOLE|IMXUART_HW_KGDB)) { 2429 2430 /* Turn on line break interrupt, set carrier. */ 2431 2432 sc->sc_ucr3 |= IMX_UCR3_DSR; 2433 bus_space_write_4(iot, ioh, IMX_UCR3, sc->sc_ucr3); 2434 2435 sc->sc_ucr4 |= IMX_UCR4_BKEN; 2436 bus_space_write_4(iot, ioh, IMX_UCR4, sc->sc_ucr4); 2437 2438 sc->sc_ucr2 |= IMX_UCR2_TXEN|IMX_UCR2_RXEN| 2439 IMX_UCR2_CTS; 2440 bus_space_write_4(iot, ioh, IMX_UCR2, sc->sc_ucr2); 2441 2442 sc->sc_ucr1 |= IMX_UCR1_UARTEN; 2443 bus_space_write_4(iot, ioh, IMX_UCR1, sc->sc_ucr1); 2444 } 2445 } 2446 2447 2448 void 2449 imxuart_set_frequency(u_int freq, u_int div) 2450 { 2451 imxuart_freq = freq; 2452 imxuart_freqdiv = div; 2453 } 2454
Indexes created Mon Sep 29 21:09:56 GMT 2025