imxuart.c revision 1.21.2.1
1 /* $NetBSD: imxuart.c,v 1.21.2.1 2020/04/08 14:07:29 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2009, 2010 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* 31 * derived from sys/dev/ic/com.c 32 */ 33 34 /*- 35 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to The NetBSD Foundation 39 * by Charles M. Hannum. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 51 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 52 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 53 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 60 * POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Copyright (c) 1991 The Regents of the University of California. 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 3. Neither the name of the University nor the names of its contributors 76 * may be used to endorse or promote products derived from this software 77 * without specific prior written permission. 78 * 79 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 80 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 82 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 85 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 86 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 87 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 88 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 89 * SUCH DAMAGE. 90 * 91 * @(#)com.c 7.5 (Berkeley) 5/16/91 92 */ 93 94 /* 95 * driver for UART in i.MX SoC. 96 */ 97 98 #include <sys/cdefs.h> 99 __KERNEL_RCSID(0, "$NetBSD: imxuart.c,v 1.21.2.1 2020/04/08 14:07:29 martin Exp $"); 100 101 #include "opt_imxuart.h" 102 #include "opt_ddb.h" 103 #include "opt_ddbparam.h" 104 #include "opt_kgdb.h" 105 #include "opt_lockdebug.h" 106 #include "opt_multiprocessor.h" 107 #include "opt_ntp.h" 108 #include "opt_imxuart.h" 109 110 #ifdef RND_COM 111 #include <sys/rndsource.h> 112 #endif 113 114 #ifndef IMXUART_TOLERANCE 115 #define IMXUART_TOLERANCE 30 /* baud rate tolerance, in 0.1% units */ 116 #endif 117 118 #ifndef IMXUART_FREQDIV 119 #define IMXUART_FREQDIV 2 /* XXX */ 120 #endif 121 122 #ifndef IMXUART_FREQ 123 #define IMXUART_FREQ (56900000) 124 #endif 125 126 /* 127 * Override cnmagic(9) macro before including <sys/systm.h>. 128 * We need to know if cn_check_magic triggered debugger, so set a flag. 129 * Callers of cn_check_magic must declare int cn_trapped = 0; 130 * XXX: this is *ugly*! 131 */ 132 #define cn_trap() \ 133 do { \ 134 console_debugger(); \ 135 cn_trapped = 1; \ 136 } while (/* CONSTCOND */ 0) 137 138 #include <sys/param.h> 139 #include <sys/systm.h> 140 #include <sys/ioctl.h> 141 #include <sys/select.h> 142 #include <sys/poll.h> 143 #include <sys/tty.h> 144 #include <sys/proc.h> 145 #include <sys/conf.h> 146 #include <sys/file.h> 147 #include <sys/uio.h> 148 #include <sys/kernel.h> 149 #include <sys/syslog.h> 150 #include <sys/device.h> 151 #include <sys/malloc.h> 152 #include <sys/timepps.h> 153 #include <sys/vnode.h> 154 #include <sys/kauth.h> 155 #include <sys/intr.h> 156 157 #include <sys/bus.h> 158 159 #include <arm/imx/imxuartreg.h> 160 #include <arm/imx/imxuartvar.h> 161 #include <dev/cons.h> 162 163 #ifndef IMXUART_RING_SIZE 164 #define IMXUART_RING_SIZE 2048 165 #endif 166 167 int imxuspeed(long, struct imxuart_baudrate_ratio *); 168 int imxuparam(struct tty *, struct termios *); 169 void imxustart(struct tty *); 170 int imxuhwiflow(struct tty *, int); 171 172 void imxuart_shutdown(struct imxuart_softc *); 173 void imxuart_loadchannelregs(struct imxuart_softc *); 174 void imxuart_hwiflow(struct imxuart_softc *); 175 void imxuart_break(struct imxuart_softc *, bool); 176 void imxuart_modem(struct imxuart_softc *, int); 177 void tiocm_to_imxu(struct imxuart_softc *, u_long, int); 178 int imxuart_to_tiocm(struct imxuart_softc *); 179 void imxuart_iflush(struct imxuart_softc *); 180 int imxuintr(void *); 181 182 int imxuart_common_getc(dev_t, struct imxuart_regs *); 183 void imxuart_common_putc(dev_t, struct imxuart_regs *, int); 184 185 186 int imxuart_init(struct imxuart_regs *, int, tcflag_t, int); 187 188 int imxucngetc(dev_t); 189 void imxucnputc(dev_t, int); 190 void imxucnpollc(dev_t, int); 191 192 static void imxuintr_read(struct imxuart_softc *); 193 static void imxuintr_send(struct imxuart_softc *); 194 195 static void imxuart_enable_debugport(struct imxuart_softc *); 196 static void imxuart_disable_all_interrupts(struct imxuart_softc *); 197 static void imxuart_control_rxint(struct imxuart_softc *, bool); 198 static void imxuart_control_txint(struct imxuart_softc *, bool); 199 static u_int imxuart_txfifo_space(struct imxuart_softc *sc); 200 201 static uint32_t cflag_to_ucr2(tcflag_t, uint32_t); 202 203 #define integrate static inline 204 void imxusoft(void *); 205 integrate void imxuart_rxsoft(struct imxuart_softc *, struct tty *); 206 integrate void imxuart_txsoft(struct imxuart_softc *, struct tty *); 207 integrate void imxuart_stsoft(struct imxuart_softc *, struct tty *); 208 integrate void imxuart_schedrx(struct imxuart_softc *); 209 void imxudiag(void *); 210 static void imxuart_load_speed(struct imxuart_softc *); 211 static void imxuart_load_params(struct imxuart_softc *); 212 integrate void imxuart_load_pendings(struct imxuart_softc *); 213 214 215 extern struct cfdriver imxuart_cd; 216 217 dev_type_open(imxuopen); 218 dev_type_close(imxuclose); 219 dev_type_read(imxuread); 220 dev_type_write(imxuwrite); 221 dev_type_ioctl(imxuioctl); 222 dev_type_stop(imxustop); 223 dev_type_tty(imxutty); 224 dev_type_poll(imxupoll); 225 226 const struct cdevsw imxcom_cdevsw = { 227 .d_open = imxuopen, 228 .d_close = imxuclose, 229 .d_read = imxuread, 230 .d_write = imxuwrite, 231 .d_ioctl = imxuioctl, 232 .d_stop = imxustop, 233 .d_tty = imxutty, 234 .d_poll = imxupoll, 235 .d_mmap = nommap, 236 .d_kqfilter = ttykqfilter, 237 .d_discard = nodiscard, 238 .d_flag = D_TTY 239 }; 240 241 /* 242 * Make this an option variable one can patch. 243 * But be warned: this must be a power of 2! 244 */ 245 u_int imxuart_rbuf_size = IMXUART_RING_SIZE; 246 247 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 248 u_int imxuart_rbuf_hiwat = (IMXUART_RING_SIZE * 1) / 4; 249 u_int imxuart_rbuf_lowat = (IMXUART_RING_SIZE * 3) / 4; 250 251 static struct imxuart_regs imxuconsregs; 252 static int imxuconsattached; 253 static int imxuconsrate; 254 static tcflag_t imxuconscflag; 255 static struct cnm_state imxuart_cnm_state; 256 257 u_int imxuart_freq = IMXUART_FREQ; 258 u_int imxuart_freqdiv = IMXUART_FREQDIV; 259 260 #ifdef KGDB 261 #include <sys/kgdb.h> 262 263 static struct imxuart_regs imxu_kgdb_regs; 264 static int imxu_kgdb_attached; 265 266 int imxuart_kgdb_getc(void *); 267 void imxuart_kgdb_putc(void *, int); 268 #endif /* KGDB */ 269 270 #define IMXUART_DIALOUT_MASK TTDIALOUT_MASK 271 272 #define IMXUART_UNIT(x) TTUNIT(x) 273 #define IMXUART_DIALOUT(x) TTDIALOUT(x) 274 275 #define IMXUART_ISALIVE(sc) ((sc)->enabled != 0 && \ 276 device_is_active((sc)->sc_dev)) 277 278 #define BR BUS_SPACE_BARRIER_READ 279 #define BW BUS_SPACE_BARRIER_WRITE 280 #define IMXUART_BARRIER(r, f) \ 281 bus_space_barrier((r)->ur_iot, (r)->ur_ioh, 0, IMX_UART_SIZE, (f)) 282 283 284 void 285 imxuart_attach_common(device_t parent, device_t self, 286 bus_space_tag_t iot, paddr_t iobase, size_t size, int intr, int flags) 287 { 288 struct imxuart_softc *sc = device_private(self); 289 struct imxuart_regs *regsp = &sc->sc_regs; 290 bus_space_handle_t ioh; 291 292 aprint_naive("\n"); 293 aprint_normal("\n"); 294 295 sc->sc_dev = self; 296 297 if (size <= 0) 298 size = IMX_UART_SIZE; 299 300 sc->sc_intr = intr; 301 regsp->ur_iot = iot; 302 regsp->ur_iobase = iobase; 303 304 if (bus_space_map(iot, regsp->ur_iobase, size, 0, &ioh)) { 305 return; 306 } 307 regsp->ur_ioh = ioh; 308 309 sc->sc_ih = intr_establish(sc->sc_intr, IPL_SERIAL, IST_LEVEL, 310 imxuintr, sc); 311 if (sc->sc_ih == NULL) { 312 aprint_error_dev(sc->sc_dev, "intr_establish failed\n"); 313 return; 314 } 315 316 imxuart_attach_subr(sc); 317 } 318 319 void 320 imxuart_attach_subr(struct imxuart_softc *sc) 321 { 322 struct imxuart_regs *regsp = &sc->sc_regs; 323 bus_space_tag_t iot = regsp->ur_iot; 324 bus_space_handle_t ioh = regsp->ur_ioh; 325 struct tty *tp; 326 327 callout_init(&sc->sc_diag_callout, 0); 328 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 329 330 if (regsp->ur_iobase != imxuconsregs.ur_iobase) 331 imxuart_init(&sc->sc_regs, TTYDEF_SPEED, TTYDEF_CFLAG, false); 332 333 bus_space_read_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 4); 334 sc->sc_ucr2_d = sc->sc_ucr2; 335 336 /* Disable interrupts before configuring the device. */ 337 imxuart_disable_all_interrupts(sc); 338 339 if (regsp->ur_iobase == imxuconsregs.ur_iobase) { 340 imxuconsattached = 1; 341 342 /* Make sure the console is always "hardwired". */ 343 #if 0 344 delay(10000); /* wait for output to finish */ 345 #endif 346 SET(sc->sc_hwflags, IMXUART_HW_CONSOLE); 347 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 348 } 349 350 351 tp = tty_alloc(); 352 tp->t_oproc = imxustart; 353 tp->t_param = imxuparam; 354 tp->t_hwiflow = imxuhwiflow; 355 356 sc->sc_tty = tp; 357 sc->sc_rbuf = malloc(sizeof (*sc->sc_rbuf) * imxuart_rbuf_size, 358 M_DEVBUF, M_NOWAIT); 359 sc->sc_rbuf_size = imxuart_rbuf_size; 360 sc->sc_rbuf_in = sc->sc_rbuf_out = 0; 361 if (sc->sc_rbuf == NULL) { 362 aprint_error_dev(sc->sc_dev, 363 "unable to allocate ring buffer\n"); 364 return; 365 } 366 367 sc->sc_txfifo_len = 32; 368 sc->sc_txfifo_thresh = 16; /* when USR1.TRDY, fifo has space 369 * for this many characters */ 370 371 tty_attach(tp); 372 373 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 374 int maj; 375 376 /* locate the major number */ 377 maj = cdevsw_lookup_major(&imxcom_cdevsw); 378 379 if (maj != NODEVMAJOR) { 380 tp->t_dev = cn_tab->cn_dev = makedev(maj, 381 device_unit(sc->sc_dev)); 382 383 aprint_normal_dev(sc->sc_dev, "console\n"); 384 } 385 } 386 387 #ifdef KGDB 388 /* 389 * Allow kgdb to "take over" this port. If this is 390 * not the console and is the kgdb device, it has 391 * exclusive use. If it's the console _and_ the 392 * kgdb device, it doesn't. 393 */ 394 if (regsp->ur_iobase == imxu_kgdb_regs.ur_iobase) { 395 if (!ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 396 imxu_kgdb_attached = 1; 397 398 SET(sc->sc_hwflags, IMXUART_HW_KGDB); 399 } 400 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 401 } 402 #endif 403 404 sc->sc_si = softint_establish(SOFTINT_SERIAL, imxusoft, sc); 405 406 #ifdef RND_COM 407 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 408 RND_TYPE_TTY, RND_FLAG_COLLECT_TIME | 409 RND_FLAG_ESTIMATE_TIME); 410 #endif 411 412 /* if there are no enable/disable functions, assume the device 413 is always enabled */ 414 if (!sc->enable) 415 sc->enabled = 1; 416 417 imxuart_enable_debugport(sc); 418 419 SET(sc->sc_hwflags, IMXUART_HW_DEV_OK); 420 421 //shutdownhook_establish(imxuart_shutdownhook, sc); 422 423 424 #if 0 425 { 426 uint32_t reg; 427 reg = bus_space_read_4(iot, ioh, IMX_UCR1); 428 reg |= IMX_UCR1_TXDMAEN | IMX_UCR1_RXDMAEN; 429 bus_space_write_4(iot, ioh, IMX_UCR1, reg); 430 } 431 #endif 432 } 433 434 /* 435 * baudrate = RefFreq / (16 * (UMBR + 1)/(UBIR + 1)) 436 * 437 * (UBIR + 1) / (UBMR + 1) = (16 * BaurdRate) / RefFreq 438 */ 439 440 static long 441 gcd(long m, long n) 442 { 443 444 if (m < n) 445 return gcd(n, m); 446 447 if (n <= 0) 448 return m; 449 return gcd(n, m % n); 450 } 451 452 int 453 imxuspeed(long speed, struct imxuart_baudrate_ratio *ratio) 454 { 455 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 456 long b = 16 * speed; 457 long f = imxuart_freq / imxuart_freqdiv; 458 long d; 459 int err = 0; 460 461 /* reduce b/f */ 462 while ((f > (1<<16) || b > (1<<16)) && (d = gcd(f, b)) > 1) { 463 f /= d; 464 b /= d; 465 } 466 467 468 while (f > (1<<16) || b > (1<<16)) { 469 f /= 2; 470 b /= 2; 471 } 472 if (f <= 0 || b <= 0) 473 return -1; 474 475 #ifdef DIAGNOSTIC 476 err = divrnd(((uint64_t)imxuart_freq) * 1000 / imxuart_freqdiv, 477 (uint64_t)speed * 16 * f / b) - 1000; 478 if (err < 0) 479 err = -err; 480 #endif 481 482 ratio->numerator = b-1; 483 ratio->modulator = f-1; 484 485 if (err > IMXUART_TOLERANCE) 486 return -1; 487 488 return 0; 489 #undef divrnd 490 } 491 492 #ifdef IMXUART_DEBUG 493 int imxuart_debug = 0; 494 495 void imxustatus(struct imxuart_softc *, const char *); 496 void 497 imxustatus(struct imxuart_softc *sc, const char *str) 498 { 499 struct tty *tp = sc->sc_tty; 500 501 aprint_normal_dev(sc->sc_dev, 502 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 503 str, 504 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 505 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 506 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 507 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 508 sc->sc_tx_stopped ? '+' : '-'); 509 510 aprint_normal_dev(sc->sc_dev, 511 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 512 str, 513 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 514 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 515 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 516 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 517 sc->sc_rx_flags); 518 } 519 #endif 520 521 #if 0 522 int 523 imxuart_detach(device_t self, int flags) 524 { 525 struct imxuart_softc *sc = device_private(self); 526 int maj, mn; 527 528 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) 529 return EBUSY; 530 531 /* locate the major number */ 532 maj = cdevsw_lookup_major(&imxcom_cdevsw); 533 534 /* Nuke the vnodes for any open instances. */ 535 mn = device_unit(self); 536 vdevgone(maj, mn, mn, VCHR); 537 538 mn |= IMXUART_DIALOUT_MASK; 539 vdevgone(maj, mn, mn, VCHR); 540 541 if (sc->sc_rbuf == NULL) { 542 /* 543 * Ring buffer allocation failed in the imxuart_attach_subr, 544 * only the tty is allocated, and nothing else. 545 */ 546 tty_free(sc->sc_tty); 547 return 0; 548 } 549 550 /* Free the receive buffer. */ 551 free(sc->sc_rbuf, M_DEVBUF); 552 553 /* Detach and free the tty. */ 554 tty_detach(sc->sc_tty); 555 tty_free(sc->sc_tty); 556 557 /* Unhook the soft interrupt handler. */ 558 softint_disestablish(sc->sc_si); 559 560 #ifdef RND_COM 561 /* Unhook the entropy source. */ 562 rnd_detach_source(&sc->rnd_source); 563 #endif 564 callout_destroy(&sc->sc_diag_callout); 565 566 /* Destroy the lock. */ 567 mutex_destroy(&sc->sc_lock); 568 569 return (0); 570 } 571 #endif 572 573 #ifdef notyet 574 int 575 imxuart_activate(device_t self, enum devact act) 576 { 577 struct imxuart_softc *sc = device_private(self); 578 int rv = 0; 579 580 switch (act) { 581 case DVACT_ACTIVATE: 582 rv = EOPNOTSUPP; 583 break; 584 585 case DVACT_DEACTIVATE: 586 if (sc->sc_hwflags & (IMXUART_HW_CONSOLE|IMXUART_HW_KGDB)) { 587 rv = EBUSY; 588 break; 589 } 590 591 if (sc->disable != NULL && sc->enabled != 0) { 592 (*sc->disable)(sc); 593 sc->enabled = 0; 594 } 595 break; 596 } 597 598 return (rv); 599 } 600 #endif 601 602 void 603 imxuart_shutdown(struct imxuart_softc *sc) 604 { 605 struct tty *tp = sc->sc_tty; 606 607 mutex_spin_enter(&sc->sc_lock); 608 609 /* If we were asserting flow control, then deassert it. */ 610 SET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED); 611 imxuart_hwiflow(sc); 612 613 /* Clear any break condition set with TIOCSBRK. */ 614 imxuart_break(sc, false); 615 616 /* 617 * Hang up if necessary. Wait a bit, so the other side has time to 618 * notice even if we immediately open the port again. 619 * Avoid tsleeping above splhigh(). 620 */ 621 if (ISSET(tp->t_cflag, HUPCL)) { 622 imxuart_modem(sc, 0); 623 mutex_spin_exit(&sc->sc_lock); 624 /* XXX will only timeout */ 625 (void) kpause(ttclos, false, hz, NULL); 626 mutex_spin_enter(&sc->sc_lock); 627 } 628 629 /* Turn off interrupts. */ 630 imxuart_disable_all_interrupts(sc); 631 /* re-enable recv interrupt for console or kgdb port */ 632 imxuart_enable_debugport(sc); 633 634 mutex_spin_exit(&sc->sc_lock); 635 636 #ifdef notyet 637 if (sc->disable) { 638 #ifdef DIAGNOSTIC 639 if (!sc->enabled) 640 panic("imxuart_shutdown: not enabled?"); 641 #endif 642 (*sc->disable)(sc); 643 sc->enabled = 0; 644 } 645 #endif 646 } 647 648 int 649 imxuopen(dev_t dev, int flag, int mode, struct lwp *l) 650 { 651 struct imxuart_softc *sc; 652 struct tty *tp; 653 int s; 654 int error; 655 656 sc = device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 657 if (sc == NULL || !ISSET(sc->sc_hwflags, IMXUART_HW_DEV_OK) || 658 sc->sc_rbuf == NULL) 659 return (ENXIO); 660 661 if (!device_is_active(sc->sc_dev)) 662 return (ENXIO); 663 664 #ifdef KGDB 665 /* 666 * If this is the kgdb port, no other use is permitted. 667 */ 668 if (ISSET(sc->sc_hwflags, IMXUART_HW_KGDB)) 669 return (EBUSY); 670 #endif 671 672 tp = sc->sc_tty; 673 674 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 675 return (EBUSY); 676 677 s = spltty(); 678 679 /* 680 * Do the following iff this is a first open. 681 */ 682 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 683 struct termios t; 684 685 tp->t_dev = dev; 686 687 688 #ifdef notyet 689 if (sc->enable) { 690 if ((*sc->enable)(sc)) { 691 splx(s); 692 aprint_error_dev(sc->sc_dev, 693 "device enable failed\n"); 694 return (EIO); 695 } 696 sc->enabled = 1; 697 } 698 #endif 699 700 mutex_spin_enter(&sc->sc_lock); 701 702 imxuart_disable_all_interrupts(sc); 703 704 /* Fetch the current modem control status, needed later. */ 705 706 #ifdef IMXUART_PPS 707 /* Clear PPS capture state on first open. */ 708 mutex_spin_enter(&timecounter_lock); 709 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 710 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 711 pps_init(&sc->sc_pps_state); 712 mutex_spin_exit(&timecounter_lock); 713 #endif 714 715 mutex_spin_exit(&sc->sc_lock); 716 717 /* 718 * Initialize the termios status to the defaults. Add in the 719 * sticky bits from TIOCSFLAGS. 720 */ 721 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 722 t.c_ospeed = imxuconsrate; 723 t.c_cflag = imxuconscflag; 724 } else { 725 t.c_ospeed = TTYDEF_SPEED; 726 t.c_cflag = TTYDEF_CFLAG; 727 } 728 t.c_ispeed = t.c_ospeed; 729 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 730 SET(t.c_cflag, CLOCAL); 731 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 732 SET(t.c_cflag, CRTSCTS); 733 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 734 SET(t.c_cflag, MDMBUF); 735 /* Make sure imxuparam() will do something. */ 736 tp->t_ospeed = 0; 737 (void) imxuparam(tp, &t); 738 tp->t_iflag = TTYDEF_IFLAG; 739 tp->t_oflag = TTYDEF_OFLAG; 740 tp->t_lflag = TTYDEF_LFLAG; 741 ttychars(tp); 742 ttsetwater(tp); 743 744 mutex_spin_enter(&sc->sc_lock); 745 746 /* 747 * Turn on DTR. We must always do this, even if carrier is not 748 * present, because otherwise we'd have to use TIOCSDTR 749 * immediately after setting CLOCAL, which applications do not 750 * expect. We always assert DTR while the device is open 751 * unless explicitly requested to deassert it. 752 */ 753 imxuart_modem(sc, 1); 754 755 /* Clear the input ring, and unblock. */ 756 sc->sc_rbuf_in = sc->sc_rbuf_out = 0; 757 imxuart_iflush(sc); 758 CLR(sc->sc_rx_flags, IMXUART_RX_ANY_BLOCK); 759 imxuart_hwiflow(sc); 760 761 /* Turn on interrupts. */ 762 imxuart_control_rxint(sc, true); 763 764 #ifdef IMXUART_DEBUG 765 if (imxuart_debug) 766 imxustatus(sc, "imxuopen "); 767 #endif 768 769 mutex_spin_exit(&sc->sc_lock); 770 } 771 772 splx(s); 773 774 #if 0 775 error = ttyopen(tp, IMXUART_DIALOUT(dev), ISSET(flag, O_NONBLOCK)); 776 #else 777 error = ttyopen(tp, 1, ISSET(flag, O_NONBLOCK)); 778 #endif 779 if (error) 780 goto bad; 781 782 error = (*tp->t_linesw->l_open)(dev, tp); 783 if (error) 784 goto bad; 785 786 return (0); 787 788 bad: 789 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 790 /* 791 * We failed to open the device, and nobody else had it opened. 792 * Clean up the state as appropriate. 793 */ 794 imxuart_shutdown(sc); 795 } 796 797 return (error); 798 } 799 800 int 801 imxuclose(dev_t dev, int flag, int mode, struct lwp *l) 802 { 803 struct imxuart_softc *sc = 804 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 805 struct tty *tp = sc->sc_tty; 806 807 /* XXX This is for cons.c. */ 808 if (!ISSET(tp->t_state, TS_ISOPEN)) 809 return (0); 810 811 (*tp->t_linesw->l_close)(tp, flag); 812 ttyclose(tp); 813 814 if (IMXUART_ISALIVE(sc) == 0) 815 return (0); 816 817 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 818 /* 819 * Although we got a last close, the device may still be in 820 * use; e.g. if this was the dialout node, and there are still 821 * processes waiting for carrier on the non-dialout node. 822 */ 823 imxuart_shutdown(sc); 824 } 825 826 return (0); 827 } 828 829 int 830 imxuread(dev_t dev, struct uio *uio, int flag) 831 { 832 struct imxuart_softc *sc = 833 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 834 struct tty *tp = sc->sc_tty; 835 836 if (IMXUART_ISALIVE(sc) == 0) 837 return (EIO); 838 839 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 840 } 841 842 int 843 imxuwrite(dev_t dev, struct uio *uio, int flag) 844 { 845 struct imxuart_softc *sc = 846 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 847 struct tty *tp = sc->sc_tty; 848 849 if (IMXUART_ISALIVE(sc) == 0) 850 return (EIO); 851 852 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 853 } 854 855 int 856 imxupoll(dev_t dev, int events, struct lwp *l) 857 { 858 struct imxuart_softc *sc = 859 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 860 struct tty *tp = sc->sc_tty; 861 862 if (IMXUART_ISALIVE(sc) == 0) 863 return (POLLHUP); 864 865 return ((*tp->t_linesw->l_poll)(tp, events, l)); 866 } 867 868 struct tty * 869 imxutty(dev_t dev) 870 { 871 struct imxuart_softc *sc = 872 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 873 struct tty *tp = sc->sc_tty; 874 875 return (tp); 876 } 877 878 int 879 imxuioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 880 { 881 struct imxuart_softc *sc; 882 struct tty *tp; 883 int error; 884 885 sc = device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 886 if (sc == NULL) 887 return ENXIO; 888 if (IMXUART_ISALIVE(sc) == 0) 889 return (EIO); 890 891 tp = sc->sc_tty; 892 893 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 894 if (error != EPASSTHROUGH) 895 return (error); 896 897 error = ttioctl(tp, cmd, data, flag, l); 898 if (error != EPASSTHROUGH) 899 return (error); 900 901 error = 0; 902 switch (cmd) { 903 case TIOCSFLAGS: 904 error = kauth_authorize_device_tty(l->l_cred, 905 KAUTH_DEVICE_TTY_PRIVSET, tp); 906 break; 907 default: 908 /* nothing */ 909 break; 910 } 911 if (error) { 912 return error; 913 } 914 915 mutex_spin_enter(&sc->sc_lock); 916 917 switch (cmd) { 918 case TIOCSBRK: 919 imxuart_break(sc, true); 920 break; 921 922 case TIOCCBRK: 923 imxuart_break(sc, false); 924 break; 925 926 case TIOCSDTR: 927 imxuart_modem(sc, 1); 928 break; 929 930 case TIOCCDTR: 931 imxuart_modem(sc, 0); 932 break; 933 934 case TIOCGFLAGS: 935 *(int *)data = sc->sc_swflags; 936 break; 937 938 case TIOCSFLAGS: 939 sc->sc_swflags = *(int *)data; 940 break; 941 942 case TIOCMSET: 943 case TIOCMBIS: 944 case TIOCMBIC: 945 tiocm_to_imxu(sc, cmd, *(int *)data); 946 break; 947 948 case TIOCMGET: 949 *(int *)data = imxuart_to_tiocm(sc); 950 break; 951 952 #ifdef notyet 953 case PPS_IOC_CREATE: 954 case PPS_IOC_DESTROY: 955 case PPS_IOC_GETPARAMS: 956 case PPS_IOC_SETPARAMS: 957 case PPS_IOC_GETCAP: 958 case PPS_IOC_FETCH: 959 #ifdef PPS_SYNC 960 case PPS_IOC_KCBIND: 961 #endif 962 mutex_spin_enter(&timecounter_lock); 963 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 964 mutex_spin_exit(&timecounter_lock); 965 break; 966 967 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 968 mutex_spin_enter(&timecounter_lock); 969 #ifndef PPS_TRAILING_EDGE 970 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 971 &sc->sc_pps_state.ppsinfo.assert_timestamp); 972 #else 973 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 974 &sc->sc_pps_state.ppsinfo.clear_timestamp); 975 #endif 976 mutex_spin_exit(&timecounter_lock); 977 break; 978 #endif 979 980 default: 981 error = EPASSTHROUGH; 982 break; 983 } 984 985 mutex_spin_exit(&sc->sc_lock); 986 987 #ifdef IMXUART_DEBUG 988 if (imxuart_debug) 989 imxustatus(sc, "imxuioctl "); 990 #endif 991 992 return (error); 993 } 994 995 integrate void 996 imxuart_schedrx(struct imxuart_softc *sc) 997 { 998 sc->sc_rx_ready = 1; 999 1000 /* Wake up the poller. */ 1001 softint_schedule(sc->sc_si); 1002 } 1003 1004 void 1005 imxuart_break(struct imxuart_softc *sc, bool onoff) 1006 { 1007 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1008 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1009 1010 if (onoff) 1011 SET(sc->sc_ucr1, IMX_UCR1_SNDBRK); 1012 else 1013 CLR(sc->sc_ucr1, IMX_UCR1_SNDBRK); 1014 1015 bus_space_write_4(iot, ioh, IMX_UCR1, sc->sc_ucr1); 1016 } 1017 1018 void 1019 imxuart_modem(struct imxuart_softc *sc, int onoff) 1020 { 1021 #ifdef notyet 1022 if (sc->sc_mcr_dtr == 0) 1023 return; 1024 1025 if (onoff) 1026 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1027 else 1028 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1029 1030 if (!sc->sc_heldchange) { 1031 if (sc->sc_tx_busy) { 1032 sc->sc_heldtbc = sc->sc_tbc; 1033 sc->sc_tbc = 0; 1034 sc->sc_heldchange = 1; 1035 } else 1036 imxuart_loadchannelregs(sc); 1037 } 1038 #endif 1039 } 1040 1041 /* 1042 * RTS output is controlled by UCR2.CTS bit. 1043 * DTR output is controlled by UCR3.DSR bit. 1044 * (i.MX reference manual uses names in DCE mode) 1045 * 1046 * note: if UCR2.CTSC == 1 for automatic HW flow control, UCR2.CTS is ignored. 1047 */ 1048 void 1049 tiocm_to_imxu(struct imxuart_softc *sc, u_long how, int ttybits) 1050 { 1051 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1052 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1053 1054 uint32_t ucr2 = sc->sc_ucr2_d; 1055 uint32_t ucr3 = sc->sc_ucr3; 1056 1057 uint32_t ucr2_mask = 0; 1058 uint32_t ucr3_mask = 0; 1059 1060 1061 if (ISSET(ttybits, TIOCM_DTR)) 1062 ucr3_mask = IMX_UCR3_DSR; 1063 if (ISSET(ttybits, TIOCM_RTS)) 1064 ucr2_mask = IMX_UCR2_CTS; 1065 1066 switch (how) { 1067 case TIOCMBIC: 1068 CLR(ucr2, ucr2_mask); 1069 CLR(ucr3, ucr3_mask); 1070 break; 1071 1072 case TIOCMBIS: 1073 SET(ucr2, ucr2_mask); 1074 SET(ucr3, ucr3_mask); 1075 break; 1076 1077 case TIOCMSET: 1078 CLR(ucr2, ucr2_mask); 1079 CLR(ucr3, ucr3_mask); 1080 SET(ucr2, ucr2_mask); 1081 SET(ucr3, ucr3_mask); 1082 break; 1083 } 1084 1085 if (ucr3 != sc->sc_ucr3) { 1086 bus_space_write_4(iot, ioh, IMX_UCR3, ucr3); 1087 sc->sc_ucr3 = ucr3; 1088 } 1089 1090 if (ucr2 == sc->sc_ucr2_d) 1091 return; 1092 1093 sc->sc_ucr2_d = ucr2; 1094 /* update CTS bit only */ 1095 ucr2 = (sc->sc_ucr2 & ~IMX_UCR2_CTS) | 1096 (ucr2 & IMX_UCR2_CTS); 1097 1098 bus_space_write_4(iot, ioh, IMX_UCR2, ucr2); 1099 sc->sc_ucr2 = ucr2; 1100 } 1101 1102 int 1103 imxuart_to_tiocm(struct imxuart_softc *sc) 1104 { 1105 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1106 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1107 int ttybits = 0; 1108 uint32_t usr[2]; 1109 1110 if (ISSET(sc->sc_ucr3, IMX_UCR3_DSR)) 1111 SET(ttybits, TIOCM_DTR); 1112 if (ISSET(sc->sc_ucr2, IMX_UCR2_CTS)) 1113 SET(ttybits, TIOCM_RTS); 1114 1115 bus_space_read_region_4(iot, ioh, IMX_USR1, usr, 2); 1116 1117 if (ISSET(usr[0], IMX_USR1_RTSS)) 1118 SET(ttybits, TIOCM_CTS); 1119 1120 if (ISSET(usr[1], IMX_USR2_DCDIN)) 1121 SET(ttybits, TIOCM_CD); 1122 1123 #if 0 1124 /* XXXbsh: I couldn't find the way to read ipp_uart_dsr_dte_i signal, 1125 although there are bits in UART registers to detect delta of DSR. 1126 */ 1127 if (ISSET(imxubits, MSR_DSR)) 1128 SET(ttybits, TIOCM_DSR); 1129 #endif 1130 1131 if (ISSET(usr[1], IMX_USR2_RIIN)) 1132 SET(ttybits, TIOCM_RI); 1133 1134 1135 #ifdef notyet 1136 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1137 SET(ttybits, TIOCM_LE); 1138 #endif 1139 1140 return (ttybits); 1141 } 1142 1143 static uint32_t 1144 cflag_to_ucr2(tcflag_t cflag, uint32_t oldval) 1145 { 1146 uint32_t val = oldval; 1147 1148 CLR(val,IMX_UCR2_WS|IMX_UCR2_PREN|IMX_UCR2_PROE|IMX_UCR2_STPB); 1149 1150 switch (cflag & CSIZE) { 1151 case CS5: 1152 case CS6: 1153 /* not suppreted. use 7-bits */ 1154 case CS7: 1155 break; 1156 case CS8: 1157 SET(val, IMX_UCR2_WS); 1158 break; 1159 } 1160 1161 1162 if (ISSET(cflag, PARENB)) { 1163 SET(val, IMX_UCR2_PREN); 1164 1165 /* odd parity */ 1166 if (!ISSET(cflag, PARODD)) 1167 SET(val, IMX_UCR2_PROE); 1168 } 1169 1170 if (ISSET(cflag, CSTOPB)) 1171 SET(val, IMX_UCR2_STPB); 1172 1173 val |= IMX_UCR2_TXEN| IMX_UCR2_RXEN|IMX_UCR2_SRST; 1174 1175 return val; 1176 } 1177 1178 int 1179 imxuparam(struct tty *tp, struct termios *t) 1180 { 1181 struct imxuart_softc *sc = 1182 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1183 struct imxuart_baudrate_ratio ratio; 1184 uint32_t ucr2; 1185 bool change_speed = tp->t_ospeed != t->c_ospeed; 1186 1187 if (IMXUART_ISALIVE(sc) == 0) 1188 return (EIO); 1189 1190 /* Check requested parameters. */ 1191 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1192 return (EINVAL); 1193 1194 /* 1195 * For the console, always force CLOCAL and !HUPCL, so that the port 1196 * is always active. 1197 */ 1198 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1199 ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 1200 SET(t->c_cflag, CLOCAL); 1201 CLR(t->c_cflag, HUPCL); 1202 } 1203 1204 /* 1205 * If there were no changes, don't do anything. This avoids dropping 1206 * input and improves performance when all we did was frob things like 1207 * VMIN and VTIME. 1208 */ 1209 if ( !change_speed && tp->t_cflag == t->c_cflag) 1210 return (0); 1211 1212 if (change_speed) { 1213 /* calculate baudrate modulator value */ 1214 if (imxuspeed(t->c_ospeed, &ratio) < 0) 1215 return (EINVAL); 1216 sc->sc_ratio = ratio; 1217 } 1218 1219 ucr2 = cflag_to_ucr2(t->c_cflag, sc->sc_ucr2_d); 1220 1221 mutex_spin_enter(&sc->sc_lock); 1222 1223 #if 0 /* flow control stuff. not yet */ 1224 /* 1225 * If we're not in a mode that assumes a connection is present, then 1226 * ignore carrier changes. 1227 */ 1228 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1229 sc->sc_msr_dcd = 0; 1230 else 1231 sc->sc_msr_dcd = MSR_DCD; 1232 /* 1233 * Set the flow control pins depending on the current flow control 1234 * mode. 1235 */ 1236 if (ISSET(t->c_cflag, CRTSCTS)) { 1237 sc->sc_mcr_dtr = MCR_DTR; 1238 sc->sc_mcr_rts = MCR_RTS; 1239 sc->sc_msr_cts = MSR_CTS; 1240 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1241 } else if (ISSET(t->c_cflag, MDMBUF)) { 1242 /* 1243 * For DTR/DCD flow control, make sure we don't toggle DTR for 1244 * carrier detection. 1245 */ 1246 sc->sc_mcr_dtr = 0; 1247 sc->sc_mcr_rts = MCR_DTR; 1248 sc->sc_msr_cts = MSR_DCD; 1249 sc->sc_efr = 0; 1250 } else { 1251 /* 1252 * If no flow control, then always set RTS. This will make 1253 * the other side happy if it mistakenly thinks we're doing 1254 * RTS/CTS flow control. 1255 */ 1256 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1257 sc->sc_mcr_rts = 0; 1258 sc->sc_msr_cts = 0; 1259 sc->sc_efr = 0; 1260 if (ISSET(sc->sc_mcr, MCR_DTR)) 1261 SET(sc->sc_mcr, MCR_RTS); 1262 else 1263 CLR(sc->sc_mcr, MCR_RTS); 1264 } 1265 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1266 #endif 1267 1268 /* And copy to tty. */ 1269 tp->t_ispeed = t->c_ospeed; 1270 tp->t_ospeed = t->c_ospeed; 1271 tp->t_cflag = t->c_cflag; 1272 1273 if (!change_speed && ucr2 == sc->sc_ucr2_d) { 1274 /* noop */ 1275 } 1276 else if (!sc->sc_pending && !sc->sc_tx_busy) { 1277 if (ucr2 != sc->sc_ucr2_d) { 1278 sc->sc_ucr2_d = ucr2; 1279 imxuart_load_params(sc); 1280 } 1281 if (change_speed) 1282 imxuart_load_speed(sc); 1283 } 1284 else { 1285 if (!sc->sc_pending) { 1286 sc->sc_heldtbc = sc->sc_tbc; 1287 sc->sc_tbc = 0; 1288 } 1289 sc->sc_pending |= 1290 (ucr2 == sc->sc_ucr2_d ? 0 : IMXUART_PEND_PARAM) | 1291 (change_speed ? 0 : IMXUART_PEND_SPEED); 1292 sc->sc_ucr2_d = ucr2; 1293 } 1294 1295 if (!ISSET(t->c_cflag, CHWFLOW)) { 1296 /* Disable the high water mark. */ 1297 sc->sc_r_hiwat = 0; 1298 sc->sc_r_lowat = 0; 1299 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED)) { 1300 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED); 1301 imxuart_schedrx(sc); 1302 } 1303 if (ISSET(sc->sc_rx_flags, 1304 IMXUART_RX_TTY_BLOCKED|IMXUART_RX_IBUF_BLOCKED)) { 1305 CLR(sc->sc_rx_flags, 1306 IMXUART_RX_TTY_BLOCKED|IMXUART_RX_IBUF_BLOCKED); 1307 imxuart_hwiflow(sc); 1308 } 1309 } else { 1310 sc->sc_r_hiwat = imxuart_rbuf_hiwat; 1311 sc->sc_r_lowat = imxuart_rbuf_lowat; 1312 } 1313 1314 mutex_spin_exit(&sc->sc_lock); 1315 1316 #if 0 1317 /* 1318 * Update the tty layer's idea of the carrier bit, in case we changed 1319 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1320 * explicit request. 1321 */ 1322 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1323 #else 1324 /* XXX: always report that we have DCD */ 1325 (void) (*tp->t_linesw->l_modem)(tp, 1); 1326 #endif 1327 1328 #ifdef IMXUART_DEBUG 1329 if (imxuart_debug) 1330 imxustatus(sc, "imxuparam "); 1331 #endif 1332 1333 if (!ISSET(t->c_cflag, CHWFLOW)) { 1334 if (sc->sc_tx_stopped) { 1335 sc->sc_tx_stopped = 0; 1336 imxustart(tp); 1337 } 1338 } 1339 1340 return (0); 1341 } 1342 1343 void 1344 imxuart_iflush(struct imxuart_softc *sc) 1345 { 1346 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1347 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1348 #ifdef DIAGNOSTIC 1349 uint32_t reg = 0xffff; 1350 #endif 1351 int timo; 1352 1353 timo = 50000; 1354 /* flush any pending I/O */ 1355 while (ISSET(bus_space_read_4(iot, ioh, IMX_USR2), IMX_USR2_RDR) 1356 && --timo) 1357 #ifdef DIAGNOSTIC 1358 reg = 1359 #else 1360 (void) 1361 #endif 1362 bus_space_read_4(iot, ioh, IMX_URXD); 1363 #ifdef DIAGNOSTIC 1364 if (!timo) 1365 aprint_error_dev(sc->sc_dev, "imxuart_iflush timeout %02x\n", reg); 1366 #endif 1367 } 1368 1369 int 1370 imxuhwiflow(struct tty *tp, int block) 1371 { 1372 struct imxuart_softc *sc = 1373 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1374 1375 if (IMXUART_ISALIVE(sc) == 0) 1376 return (0); 1377 1378 #ifdef notyet 1379 if (sc->sc_mcr_rts == 0) 1380 return (0); 1381 #endif 1382 1383 mutex_spin_enter(&sc->sc_lock); 1384 1385 if (block) { 1386 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) { 1387 SET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED); 1388 imxuart_hwiflow(sc); 1389 } 1390 } else { 1391 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED)) { 1392 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED); 1393 imxuart_schedrx(sc); 1394 } 1395 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) { 1396 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED); 1397 imxuart_hwiflow(sc); 1398 } 1399 } 1400 1401 mutex_spin_exit(&sc->sc_lock); 1402 return (1); 1403 } 1404 1405 /* 1406 * (un)block input via hw flowcontrol 1407 */ 1408 void 1409 imxuart_hwiflow(struct imxuart_softc *sc) 1410 { 1411 #ifdef notyet 1412 struct imxuart_regs *regsp= &sc->sc_regs; 1413 1414 if (sc->sc_mcr_rts == 0) 1415 return; 1416 1417 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1418 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1419 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1420 } else { 1421 SET(sc->sc_mcr, sc->sc_mcr_rts); 1422 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1423 } 1424 UR_WRITE_1(regsp, IMXUART_REG_MCR, sc->sc_mcr_active); 1425 #endif 1426 } 1427 1428 1429 void 1430 imxustart(struct tty *tp) 1431 { 1432 struct imxuart_softc *sc = 1433 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1434 int s; 1435 u_char *tba; 1436 int tbc; 1437 u_int n; 1438 u_int space; 1439 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1440 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1441 1442 if (IMXUART_ISALIVE(sc) == 0) 1443 return; 1444 1445 s = spltty(); 1446 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1447 goto out; 1448 if (sc->sc_tx_stopped) 1449 goto out; 1450 if (!ttypull(tp)) 1451 goto out; 1452 1453 /* Grab the first contiguous region of buffer space. */ 1454 tba = tp->t_outq.c_cf; 1455 tbc = ndqb(&tp->t_outq, 0); 1456 1457 mutex_spin_enter(&sc->sc_lock); 1458 1459 sc->sc_tba = tba; 1460 sc->sc_tbc = tbc; 1461 1462 SET(tp->t_state, TS_BUSY); 1463 sc->sc_tx_busy = 1; 1464 1465 space = imxuart_txfifo_space(sc); 1466 n = MIN(sc->sc_tbc, space); 1467 1468 if (n > 0) { 1469 bus_space_write_multi_1(iot, ioh, IMX_UTXD, sc->sc_tba, n); 1470 sc->sc_tbc -= n; 1471 sc->sc_tba += n; 1472 } 1473 1474 /* Enable transmit completion interrupts */ 1475 imxuart_control_txint(sc, true); 1476 1477 mutex_spin_exit(&sc->sc_lock); 1478 out: 1479 splx(s); 1480 return; 1481 } 1482 1483 /* 1484 * Stop output on a line. 1485 */ 1486 void 1487 imxustop(struct tty *tp, int flag) 1488 { 1489 struct imxuart_softc *sc = 1490 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1491 1492 mutex_spin_enter(&sc->sc_lock); 1493 if (ISSET(tp->t_state, TS_BUSY)) { 1494 /* Stop transmitting at the next chunk. */ 1495 sc->sc_tbc = 0; 1496 sc->sc_heldtbc = 0; 1497 if (!ISSET(tp->t_state, TS_TTSTOP)) 1498 SET(tp->t_state, TS_FLUSH); 1499 } 1500 mutex_spin_exit(&sc->sc_lock); 1501 } 1502 1503 void 1504 imxudiag(void *arg) 1505 { 1506 #ifdef notyet 1507 struct imxuart_softc *sc = arg; 1508 int overflows, floods; 1509 1510 mutex_spin_enter(&sc->sc_lock); 1511 overflows = sc->sc_overflows; 1512 sc->sc_overflows = 0; 1513 floods = sc->sc_floods; 1514 sc->sc_floods = 0; 1515 sc->sc_errors = 0; 1516 mutex_spin_exit(&sc->sc_lock); 1517 1518 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1519 device_xname(sc->sc_dev), 1520 overflows, overflows == 1 ? "" : "s", 1521 floods, floods == 1 ? "" : "s"); 1522 #endif 1523 } 1524 1525 integrate void 1526 imxuart_rxsoft(struct imxuart_softc *sc, struct tty *tp) 1527 { 1528 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1529 u_int cc, scc, outp; 1530 uint16_t data; 1531 u_int code; 1532 1533 scc = cc = IMXUART_RBUF_AVAIL(sc); 1534 1535 #if 0 1536 if (cc == imxuart_rbuf_size-1) { 1537 sc->sc_floods++; 1538 if (sc->sc_errors++ == 0) 1539 callout_reset(&sc->sc_diag_callout, 60 * hz, 1540 imxudiag, sc); 1541 } 1542 #endif 1543 1544 /* If not yet open, drop the entire buffer content here */ 1545 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1546 sc->sc_rbuf_out = sc->sc_rbuf_in; 1547 cc = 0; 1548 } 1549 1550 outp = sc->sc_rbuf_out; 1551 1552 #define ERRBITS (IMX_URXD_PRERR|IMX_URXD_BRK|IMX_URXD_FRMERR|IMX_URXD_OVRRUN) 1553 1554 while (cc) { 1555 data = sc->sc_rbuf[outp]; 1556 code = data & IMX_URXD_RX_DATA; 1557 if (ISSET(data, ERRBITS)) { 1558 if (sc->sc_errors.err == 0) 1559 callout_reset(&sc->sc_diag_callout, 1560 60 * hz, imxudiag, sc); 1561 if (ISSET(data, IMX_URXD_OVRRUN)) 1562 sc->sc_errors.ovrrun++; 1563 if (ISSET(data, IMX_URXD_BRK)) { 1564 sc->sc_errors.brk++; 1565 SET(code, TTY_FE); 1566 } 1567 if (ISSET(data, IMX_URXD_FRMERR)) { 1568 sc->sc_errors.frmerr++; 1569 SET(code, TTY_FE); 1570 } 1571 if (ISSET(data, IMX_URXD_PRERR)) { 1572 sc->sc_errors.prerr++; 1573 SET(code, TTY_PE); 1574 } 1575 } 1576 if ((*rint)(code, tp) == -1) { 1577 /* 1578 * The line discipline's buffer is out of space. 1579 */ 1580 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) { 1581 /* 1582 * We're either not using flow control, or the 1583 * line discipline didn't tell us to block for 1584 * some reason. Either way, we have no way to 1585 * know when there's more space available, so 1586 * just drop the rest of the data. 1587 */ 1588 sc->sc_rbuf_out = sc->sc_rbuf_in; 1589 cc = 0; 1590 } else { 1591 /* 1592 * Don't schedule any more receive processing 1593 * until the line discipline tells us there's 1594 * space available (through imxuhwiflow()). 1595 * Leave the rest of the data in the input 1596 * buffer. 1597 */ 1598 SET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED); 1599 } 1600 break; 1601 } 1602 outp = IMXUART_RBUF_INC(sc, outp, 1); 1603 cc--; 1604 } 1605 1606 if (cc != scc) { 1607 sc->sc_rbuf_out = outp; 1608 mutex_spin_enter(&sc->sc_lock); 1609 1610 cc = IMXUART_RBUF_SPACE(sc); 1611 1612 /* Buffers should be ok again, release possible block. */ 1613 if (cc >= sc->sc_r_lowat) { 1614 if (ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_OVERFLOWED)) { 1615 CLR(sc->sc_rx_flags, IMXUART_RX_IBUF_OVERFLOWED); 1616 imxuart_control_rxint(sc, true); 1617 } 1618 if (ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED)) { 1619 CLR(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED); 1620 imxuart_hwiflow(sc); 1621 } 1622 } 1623 mutex_spin_exit(&sc->sc_lock); 1624 } 1625 } 1626 1627 integrate void 1628 imxuart_txsoft(struct imxuart_softc *sc, struct tty *tp) 1629 { 1630 1631 CLR(tp->t_state, TS_BUSY); 1632 if (ISSET(tp->t_state, TS_FLUSH)) 1633 CLR(tp->t_state, TS_FLUSH); 1634 else 1635 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1636 (*tp->t_linesw->l_start)(tp); 1637 } 1638 1639 integrate void 1640 imxuart_stsoft(struct imxuart_softc *sc, struct tty *tp) 1641 { 1642 #ifdef notyet 1643 u_char msr, delta; 1644 1645 mutex_spin_enter(&sc->sc_lock); 1646 msr = sc->sc_msr; 1647 delta = sc->sc_msr_delta; 1648 sc->sc_msr_delta = 0; 1649 mutex_spin_exit(&sc->sc_lock); 1650 1651 if (ISSET(delta, sc->sc_msr_dcd)) { 1652 /* 1653 * Inform the tty layer that carrier detect changed. 1654 */ 1655 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1656 } 1657 1658 if (ISSET(delta, sc->sc_msr_cts)) { 1659 /* Block or unblock output according to flow control. */ 1660 if (ISSET(msr, sc->sc_msr_cts)) { 1661 sc->sc_tx_stopped = 0; 1662 (*tp->t_linesw->l_start)(tp); 1663 } else { 1664 sc->sc_tx_stopped = 1; 1665 } 1666 } 1667 1668 #endif 1669 #ifdef IMXUART_DEBUG 1670 if (imxuart_debug) 1671 imxustatus(sc, "imxuart_stsoft"); 1672 #endif 1673 } 1674 1675 void 1676 imxusoft(void *arg) 1677 { 1678 struct imxuart_softc *sc = arg; 1679 struct tty *tp; 1680 1681 if (IMXUART_ISALIVE(sc) == 0) 1682 return; 1683 1684 tp = sc->sc_tty; 1685 1686 if (sc->sc_rx_ready) { 1687 sc->sc_rx_ready = 0; 1688 imxuart_rxsoft(sc, tp); 1689 } 1690 1691 if (sc->sc_st_check) { 1692 sc->sc_st_check = 0; 1693 imxuart_stsoft(sc, tp); 1694 } 1695 1696 if (sc->sc_tx_done) { 1697 sc->sc_tx_done = 0; 1698 imxuart_txsoft(sc, tp); 1699 } 1700 } 1701 1702 int 1703 imxuintr(void *arg) 1704 { 1705 struct imxuart_softc *sc = arg; 1706 uint32_t usr1, usr2; 1707 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1708 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1709 1710 1711 if (IMXUART_ISALIVE(sc) == 0) 1712 return (0); 1713 1714 mutex_spin_enter(&sc->sc_lock); 1715 1716 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1717 1718 1719 do { 1720 bus_space_write_4(iot, ioh, IMX_USR2, 1721 usr2 & (IMX_USR2_BRCD|IMX_USR2_ORE)); 1722 if (usr2 & IMX_USR2_BRCD) { 1723 /* Break signal detected */ 1724 int cn_trapped = 0; 1725 1726 cn_check_magic(sc->sc_tty->t_dev, 1727 CNC_BREAK, imxuart_cnm_state); 1728 if (cn_trapped) 1729 continue; 1730 #if defined(KGDB) && !defined(DDB) 1731 if (ISSET(sc->sc_hwflags, IMXUART_HW_KGDB)) { 1732 kgdb_connect(1); 1733 continue; 1734 } 1735 #endif 1736 } 1737 1738 if (usr2 & IMX_USR2_RDR) 1739 imxuintr_read(sc); 1740 1741 #ifdef IMXUART_PPS 1742 { 1743 u_char msr, delta; 1744 1745 msr = CSR_READ_1(regsp, IMXUART_REG_MSR); 1746 delta = msr ^ sc->sc_msr; 1747 sc->sc_msr = msr; 1748 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 1749 (delta & MSR_DCD)) { 1750 mutex_spin_enter(&timecounter_lock); 1751 pps_capture(&sc->sc_pps_state); 1752 pps_event(&sc->sc_pps_state, 1753 (msr & MSR_DCD) ? 1754 PPS_CAPTUREASSERT : 1755 PPS_CAPTURECLEAR); 1756 mutex_spin_exit(&timecounter_lock); 1757 } 1758 } 1759 #endif 1760 1761 #ifdef notyet 1762 /* 1763 * Process normal status changes 1764 */ 1765 if (ISSET(delta, sc->sc_msr_mask)) { 1766 SET(sc->sc_msr_delta, delta); 1767 1768 /* 1769 * Stop output immediately if we lose the output 1770 * flow control signal or carrier detect. 1771 */ 1772 if (ISSET(~msr, sc->sc_msr_mask)) { 1773 sc->sc_tbc = 0; 1774 sc->sc_heldtbc = 0; 1775 #ifdef IMXUART_DEBUG 1776 if (imxuart_debug) 1777 imxustatus(sc, "imxuintr "); 1778 #endif 1779 } 1780 1781 sc->sc_st_check = 1; 1782 } 1783 #endif 1784 1785 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1786 } while (usr2 & (IMX_USR2_RDR|IMX_USR2_BRCD)); 1787 1788 usr1 = bus_space_read_4(iot, ioh, IMX_USR1); 1789 if (usr1 & IMX_USR1_TRDY) 1790 imxuintr_send(sc); 1791 1792 mutex_spin_exit(&sc->sc_lock); 1793 1794 /* Wake up the poller. */ 1795 softint_schedule(sc->sc_si); 1796 1797 #ifdef RND_COM 1798 rnd_add_uint32(&sc->rnd_source, iir | lsr); 1799 #endif 1800 1801 return (1); 1802 } 1803 1804 1805 /* 1806 * called when there is least one character in rxfifo 1807 * 1808 */ 1809 1810 static void 1811 imxuintr_read(struct imxuart_softc *sc) 1812 { 1813 int cc; 1814 uint16_t rd; 1815 uint32_t usr2; 1816 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1817 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1818 1819 cc = IMXUART_RBUF_SPACE(sc); 1820 1821 /* clear aging timer interrupt */ 1822 bus_space_write_4(iot, ioh, IMX_USR1, IMX_USR1_AGTIM); 1823 1824 while (cc > 0) { 1825 int cn_trapped = 0; 1826 1827 1828 sc->sc_rbuf[sc->sc_rbuf_in] = rd = 1829 bus_space_read_4(iot, ioh, IMX_URXD); 1830 1831 cn_check_magic(sc->sc_tty->t_dev, 1832 rd & 0xff, imxuart_cnm_state); 1833 1834 if (!cn_trapped) { 1835 #if defined(DDB) && defined(DDB_KEYCODE) 1836 /* 1837 * Temporary hack so that I can force the kernel into 1838 * the debugger via the serial port 1839 */ 1840 if ((rd & 0xff) == DDB_KEYCODE) 1841 Debugger(); 1842 #endif 1843 sc->sc_rbuf_in = IMXUART_RBUF_INC(sc, sc->sc_rbuf_in, 1); 1844 cc--; 1845 } 1846 1847 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1848 if (!(usr2 & IMX_USR2_RDR)) 1849 break; 1850 } 1851 1852 /* 1853 * Current string of incoming characters ended because 1854 * no more data was available or we ran out of space. 1855 * Schedule a receive event if any data was received. 1856 * If we're out of space, turn off receive interrupts. 1857 */ 1858 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED)) 1859 sc->sc_rx_ready = 1; 1860 /* 1861 * See if we are in danger of overflowing a buffer. If 1862 * so, use hardware flow control to ease the pressure. 1863 */ 1864 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED) && 1865 cc < sc->sc_r_hiwat) { 1866 sc->sc_rx_flags |= IMXUART_RX_IBUF_BLOCKED; 1867 imxuart_hwiflow(sc); 1868 } 1869 1870 /* 1871 * If we're out of space, disable receive interrupts 1872 * until the queue has drained a bit. 1873 */ 1874 if (!cc) { 1875 sc->sc_rx_flags |= IMXUART_RX_IBUF_OVERFLOWED; 1876 imxuart_control_rxint(sc, false); 1877 } 1878 } 1879 1880 1881 1882 /* 1883 * find how many chars we can put into tx-fifo 1884 */ 1885 static u_int 1886 imxuart_txfifo_space(struct imxuart_softc *sc) 1887 { 1888 uint32_t usr1, usr2; 1889 u_int cc; 1890 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1891 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1892 1893 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1894 if (usr2 & IMX_USR2_TXFE) 1895 cc = sc->sc_txfifo_len; 1896 else { 1897 usr1 = bus_space_read_4(iot, ioh, IMX_USR1); 1898 if (usr1 & IMX_USR1_TRDY) 1899 cc = sc->sc_txfifo_thresh; 1900 else 1901 cc = 0; 1902 } 1903 1904 return cc; 1905 } 1906 1907 void 1908 imxuintr_send(struct imxuart_softc *sc) 1909 { 1910 uint32_t usr2; 1911 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1912 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1913 int cc = 0; 1914 1915 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1916 1917 if (sc->sc_pending) { 1918 if (usr2 & IMX_USR2_TXFE) { 1919 imxuart_load_pendings(sc); 1920 sc->sc_tbc = sc->sc_heldtbc; 1921 sc->sc_heldtbc = 0; 1922 } 1923 else { 1924 /* wait for TX fifo empty */ 1925 imxuart_control_txint(sc, true); 1926 return; 1927 } 1928 } 1929 1930 cc = imxuart_txfifo_space(sc); 1931 cc = MIN(cc, sc->sc_tbc); 1932 1933 if (cc > 0) { 1934 bus_space_write_multi_1(iot, ioh, IMX_UTXD, sc->sc_tba, cc); 1935 sc->sc_tbc -= cc; 1936 sc->sc_tba += cc; 1937 } 1938 1939 if (sc->sc_tbc > 0) 1940 imxuart_control_txint(sc, true); 1941 else { 1942 /* no more chars to send. 1943 we don't need tx interrupt any more. */ 1944 imxuart_control_txint(sc, false); 1945 if (sc->sc_tx_busy) { 1946 sc->sc_tx_busy = 0; 1947 sc->sc_tx_done = 1; 1948 } 1949 } 1950 } 1951 1952 static void 1953 imxuart_disable_all_interrupts(struct imxuart_softc *sc) 1954 { 1955 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1956 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1957 1958 sc->sc_ucr1 &= ~IMXUART_INTRS_UCR1; 1959 sc->sc_ucr2 &= ~IMXUART_INTRS_UCR2; 1960 sc->sc_ucr3 &= ~IMXUART_INTRS_UCR3; 1961 sc->sc_ucr4 &= ~IMXUART_INTRS_UCR4; 1962 1963 1964 bus_space_write_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 4); 1965 } 1966 1967 static void 1968 imxuart_control_rxint(struct imxuart_softc *sc, bool enable) 1969 { 1970 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1971 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1972 uint32_t ucr1, ucr2; 1973 1974 ucr1 = sc->sc_ucr1; 1975 ucr2 = sc->sc_ucr2; 1976 1977 if (enable) { 1978 ucr1 |= IMX_UCR1_RRDYEN; 1979 ucr2 |= IMX_UCR2_ATEN; 1980 } 1981 else { 1982 ucr1 &= ~IMX_UCR1_RRDYEN; 1983 ucr2 &= ~IMX_UCR2_ATEN; 1984 } 1985 1986 if (ucr1 != sc->sc_ucr1 || ucr2 != sc->sc_ucr2) { 1987 sc->sc_ucr1 = ucr1; 1988 sc->sc_ucr2 = ucr2; 1989 bus_space_write_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 2); 1990 } 1991 } 1992 1993 static void 1994 imxuart_control_txint(struct imxuart_softc *sc, bool enable) 1995 { 1996 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1997 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1998 uint32_t ucr1; 1999 uint32_t mask; 2000 2001 /* if parameter change is pending, get interrupt when Tx fifo 2002 is completely empty. otherwise, get interrupt when txfifo 2003 has less characters than threshold */ 2004 mask = sc->sc_pending ? IMX_UCR1_TXMPTYEN : IMX_UCR1_TRDYEN; 2005 2006 ucr1 = sc->sc_ucr1; 2007 2008 CLR(ucr1, IMX_UCR1_TXMPTYEN|IMX_UCR1_TRDYEN); 2009 if (enable) 2010 SET(ucr1, mask); 2011 2012 if (ucr1 != sc->sc_ucr1) { 2013 bus_space_write_4(iot, ioh, IMX_UCR1, ucr1); 2014 sc->sc_ucr1 = ucr1; 2015 } 2016 } 2017 2018 2019 static void 2020 imxuart_load_params(struct imxuart_softc *sc) 2021 { 2022 uint32_t ucr2; 2023 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2024 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2025 2026 ucr2 = (sc->sc_ucr2_d & ~IMX_UCR2_ATEN) | 2027 (sc->sc_ucr2 & IMX_UCR2_ATEN); 2028 2029 bus_space_write_4(iot, ioh, IMX_UCR2, ucr2); 2030 sc->sc_ucr2 = ucr2; 2031 } 2032 2033 static void 2034 imxuart_load_speed(struct imxuart_softc *sc) 2035 { 2036 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2037 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2038 int n, rfdiv, ufcr; 2039 2040 #ifdef notyet 2041 /* 2042 * Set the FIFO threshold based on the receive speed. 2043 * 2044 * * If it's a low speed, it's probably a mouse or some other 2045 * interactive device, so set the threshold low. 2046 * * If it's a high speed, trim the trigger level down to prevent 2047 * overflows. 2048 * * Otherwise set it a bit higher. 2049 */ 2050 if (t->c_ospeed <= 1200) 2051 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 2052 else if (t->c_ospeed <= 38400) 2053 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 2054 else 2055 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 2056 #endif 2057 2058 n = 32 - sc->sc_txfifo_thresh; 2059 n = MAX(2, n); 2060 2061 rfdiv = IMX_UFCR_DIVIDER_TO_RFDIV(imxuart_freqdiv); 2062 2063 ufcr = (n << IMX_UFCR_TXTL_SHIFT) | 2064 (rfdiv << IMX_UFCR_RFDIV_SHIFT) | 2065 (16 << IMX_UFCR_RXTL_SHIFT); 2066 2067 /* keep DCE/DTE bit */ 2068 ufcr |= bus_space_read_4(iot, ioh, IMX_UFCR) & IMX_UFCR_DCEDTE; 2069 2070 bus_space_write_4(iot, ioh, IMX_UFCR, ufcr); 2071 2072 /* UBIR must updated before UBMR */ 2073 bus_space_write_4(iot, ioh, 2074 IMX_UBIR, sc->sc_ratio.numerator); 2075 bus_space_write_4(iot, ioh, 2076 IMX_UBMR, sc->sc_ratio.modulator); 2077 2078 2079 } 2080 2081 2082 static void 2083 imxuart_load_pendings(struct imxuart_softc *sc) 2084 { 2085 if (sc->sc_pending & IMXUART_PEND_PARAM) 2086 imxuart_load_params(sc); 2087 if (sc->sc_pending & IMXUART_PEND_SPEED) 2088 imxuart_load_speed(sc); 2089 sc->sc_pending = 0; 2090 } 2091 2092 #if defined(IMXUARTCONSOLE) || defined(KGDB) 2093 2094 /* 2095 * The following functions are polled getc and putc routines, shared 2096 * by the console and kgdb glue. 2097 * 2098 * The read-ahead code is so that you can detect pending in-band 2099 * cn_magic in polled mode while doing output rather than having to 2100 * wait until the kernel decides it needs input. 2101 */ 2102 2103 #define READAHEAD_RING_LEN 16 2104 static int imxuart_readahead[READAHEAD_RING_LEN]; 2105 static int imxuart_readahead_in = 0; 2106 static int imxuart_readahead_out = 0; 2107 #define READAHEAD_IS_EMPTY() (imxuart_readahead_in==imxuart_readahead_out) 2108 #define READAHEAD_IS_FULL() \ 2109 (((imxuart_readahead_in+1) & (READAHEAD_RING_LEN-1)) ==imxuart_readahead_out) 2110 2111 int 2112 imxuart_common_getc(dev_t dev, struct imxuart_regs *regsp) 2113 { 2114 int s = splserial(); 2115 u_char c; 2116 bus_space_tag_t iot = regsp->ur_iot; 2117 bus_space_handle_t ioh = regsp->ur_ioh; 2118 uint32_t usr2; 2119 2120 /* got a character from reading things earlier */ 2121 if (imxuart_readahead_in != imxuart_readahead_out) { 2122 2123 c = imxuart_readahead[imxuart_readahead_out]; 2124 imxuart_readahead_out = (imxuart_readahead_out + 1) & 2125 (READAHEAD_RING_LEN-1); 2126 splx(s); 2127 return (c); 2128 } 2129 2130 /* block until a character becomes available */ 2131 while (!((usr2 = bus_space_read_4(iot, ioh, IMX_USR2)) & IMX_USR2_RDR)) 2132 ; 2133 2134 c = 0xff & bus_space_read_4(iot, ioh, IMX_URXD); 2135 2136 { 2137 int __attribute__((__unused__))cn_trapped = 0; /* unused */ 2138 #ifdef DDB 2139 extern int db_active; 2140 if (!db_active) 2141 #endif 2142 cn_check_magic(dev, c, imxuart_cnm_state); 2143 } 2144 splx(s); 2145 return (c); 2146 } 2147 2148 void 2149 imxuart_common_putc(dev_t dev, struct imxuart_regs *regsp, int c) 2150 { 2151 int s = splserial(); 2152 int cin, timo; 2153 bus_space_tag_t iot = regsp->ur_iot; 2154 bus_space_handle_t ioh = regsp->ur_ioh; 2155 uint32_t usr2; 2156 2157 if (!READAHEAD_IS_FULL() && 2158 ((usr2 = bus_space_read_4(iot, ioh, IMX_USR2)) & IMX_USR2_RDR)) { 2159 2160 int __attribute__((__unused__))cn_trapped = 0; 2161 cin = bus_space_read_4(iot, ioh, IMX_URXD); 2162 cn_check_magic(dev, cin & 0xff, imxuart_cnm_state); 2163 imxuart_readahead_in = (imxuart_readahead_in + 1) & 2164 (READAHEAD_RING_LEN-1); 2165 } 2166 2167 /* wait for any pending transmission to finish */ 2168 timo = 150000; 2169 do { 2170 if (bus_space_read_4(iot, ioh, IMX_USR1) & IMX_USR1_TRDY) { 2171 bus_space_write_4(iot, ioh, IMX_UTXD, c); 2172 break; 2173 } 2174 } while(--timo > 0); 2175 2176 IMXUART_BARRIER(regsp, BR | BW); 2177 2178 splx(s); 2179 } 2180 #endif /* defined(IMXUARTCONSOLE) || defined(KGDB) */ 2181 2182 /* 2183 * Initialize UART 2184 */ 2185 int 2186 imxuart_init(struct imxuart_regs *regsp, int rate, tcflag_t cflag, int domap) 2187 { 2188 struct imxuart_baudrate_ratio ratio; 2189 int rfdiv = IMX_UFCR_DIVIDER_TO_RFDIV(imxuart_freqdiv); 2190 uint32_t ufcr; 2191 int error; 2192 2193 if (domap && (error = bus_space_map(regsp->ur_iot, regsp->ur_iobase, 2194 IMX_UART_SIZE, 0, ®sp->ur_ioh)) != 0) 2195 return error; 2196 2197 if (imxuart_freq != 0) { 2198 if (imxuspeed(rate, &ratio) < 0) 2199 return EINVAL; 2200 2201 /* UBIR must updated before UBMR */ 2202 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, 2203 IMX_UBIR, ratio.numerator); 2204 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, 2205 IMX_UBMR, ratio.modulator); 2206 } 2207 2208 /* XXX: DTREN, DPEC */ 2209 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR3, 2210 IMX_UCR3_DSR|IMX_UCR3_RXDMUXSEL); 2211 2212 ufcr = bus_space_read_4(regsp->ur_iot, regsp->ur_ioh, IMX_UFCR); 2213 ufcr &= ~IMX_UFCR_TXTL; 2214 ufcr |= (8 << IMX_UFCR_TXTL_SHIFT); 2215 ufcr &= ~IMX_UFCR_RXTL; 2216 ufcr |= (1 << IMX_UFCR_RXTL_SHIFT); 2217 if (imxuart_freq != 0) { 2218 ufcr &= ~IMX_UFCR_RFDIV; 2219 ufcr |= (rfdiv << IMX_UFCR_RFDIV_SHIFT); 2220 } 2221 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UFCR, ufcr); 2222 2223 if (imxuart_freq != 0) { 2224 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_ONEMS, 2225 imxuart_freq / imxuart_freqdiv / 1000); 2226 } 2227 2228 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR2, 2229 IMX_UCR2_IRTS| 2230 IMX_UCR2_CTSC| 2231 IMX_UCR2_WS|IMX_UCR2_TXEN| 2232 IMX_UCR2_RXEN|IMX_UCR2_SRST); 2233 /* clear status registers */ 2234 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_USR1, 0xffff); 2235 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_USR2, 0xffff); 2236 2237 2238 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR1, 2239 IMX_UCR1_UARTEN); 2240 2241 return (0); 2242 } 2243 2244 2245 #ifdef IMXUARTCONSOLE 2246 /* 2247 * Following are all routines needed for UART to act as console 2248 */ 2249 struct consdev imxucons = { 2250 NULL, NULL, imxucngetc, imxucnputc, imxucnpollc, NULL, NULL, NULL, 2251 NODEV, CN_NORMAL 2252 }; 2253 2254 2255 int 2256 imxuart_cnattach(bus_space_tag_t iot, paddr_t iobase, u_int rate, 2257 tcflag_t cflag) 2258 { 2259 struct imxuart_regs regs; 2260 int res; 2261 2262 regs.ur_iot = iot; 2263 regs.ur_iobase = iobase; 2264 2265 res = imxuart_init(®s, rate, cflag, true); 2266 if (res) 2267 return (res); 2268 2269 cn_tab = &imxucons; 2270 cn_init_magic(&imxuart_cnm_state); 2271 cn_set_magic("\047\001"); /* default magic is BREAK */ 2272 2273 imxuconsrate = rate; 2274 imxuconscflag = cflag; 2275 2276 imxuconsregs = regs; 2277 2278 return 0; 2279 } 2280 2281 int 2282 imxucngetc(dev_t dev) 2283 { 2284 return (imxuart_common_getc(dev, &imxuconsregs)); 2285 } 2286 2287 /* 2288 * Console kernel output character routine. 2289 */ 2290 void 2291 imxucnputc(dev_t dev, int c) 2292 { 2293 imxuart_common_putc(dev, &imxuconsregs, c); 2294 } 2295 2296 void 2297 imxucnpollc(dev_t dev, int on) 2298 { 2299 2300 imxuart_readahead_in = 0; 2301 imxuart_readahead_out = 0; 2302 } 2303 2304 #endif /* IMXUARTCONSOLE */ 2305 2306 #ifdef KGDB 2307 int 2308 imxuart_kgdb_attach(bus_space_tag_t iot, paddr_t iobase, u_int rate, 2309 tcflag_t cflag) 2310 { 2311 int res; 2312 2313 if (iot == imxuconsregs.ur_iot && 2314 iobase == imxuconsregs.ur_iobase) { 2315 #if !defined(DDB) 2316 return (EBUSY); /* cannot share with console */ 2317 #else 2318 imxu_kgdb_regs.ur_iot = iot; 2319 imxu_kgdb_regs.ur_ioh = imxuconsregs.ur_ioh; 2320 imxu_kgdb_regs.ur_iobase = iobase; 2321 #endif 2322 } else { 2323 imxu_kgdb_regs.ur_iot = iot; 2324 imxu_kgdb_regs.ur_iobase = iobase; 2325 2326 res = imxuart_init(&imxu_kgdb_regs, rate, cflag, true); 2327 if (res) 2328 return (res); 2329 2330 /* 2331 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2332 * expects this to be initialized 2333 */ 2334 cn_init_magic(&imxuart_cnm_state); 2335 cn_set_magic("\047\001"); 2336 } 2337 2338 kgdb_attach(imxuart_kgdb_getc, imxuart_kgdb_putc, &imxu_kgdb_regs); 2339 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2340 2341 return (0); 2342 } 2343 2344 /* ARGSUSED */ 2345 int 2346 imxuart_kgdb_getc(void *arg) 2347 { 2348 struct imxuart_regs *regs = arg; 2349 2350 return (imxuart_common_getc(NODEV, regs)); 2351 } 2352 2353 /* ARGSUSED */ 2354 void 2355 imxuart_kgdb_putc(void *arg, int c) 2356 { 2357 struct imxuart_regs *regs = arg; 2358 2359 imxuart_common_putc(NODEV, regs, c); 2360 } 2361 #endif /* KGDB */ 2362 2363 /* helper function to identify the imxu ports used by 2364 console or KGDB (and not yet autoconf attached) */ 2365 int 2366 imxuart_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2367 { 2368 bus_space_handle_t help; 2369 2370 if (!imxuconsattached && 2371 iot == imxuconsregs.ur_iot && iobase == imxuconsregs.ur_iobase) 2372 help = imxuconsregs.ur_ioh; 2373 #ifdef KGDB 2374 else if (!imxu_kgdb_attached && 2375 iot == imxu_kgdb_regs.ur_iot && iobase == imxu_kgdb_regs.ur_iobase) 2376 help = imxu_kgdb_regs.ur_ioh; 2377 #endif 2378 else 2379 return (0); 2380 2381 if (ioh) 2382 *ioh = help; 2383 return (1); 2384 } 2385 2386 #ifdef notyet 2387 2388 bool 2389 imxuart_cleanup(device_t self, int how) 2390 { 2391 /* 2392 * this routine exists to serve as a shutdown hook for systems that 2393 * have firmware which doesn't interact properly with a imxuart device in 2394 * FIFO mode. 2395 */ 2396 struct imxuart_softc *sc = device_private(self); 2397 2398 if (ISSET(sc->sc_hwflags, IMXUART_HW_FIFO)) 2399 UR_WRITE_1(&sc->sc_regs, IMXUART_REG_FIFO, 0); 2400 2401 return true; 2402 } 2403 #endif 2404 2405 #ifdef notyet 2406 bool 2407 imxuart_suspend(device_t self PMF_FN_ARGS) 2408 { 2409 struct imxuart_softc *sc = device_private(self); 2410 2411 UR_WRITE_1(&sc->sc_regs, IMXUART_REG_IER, 0); 2412 (void)CSR_READ_1(&sc->sc_regs, IMXUART_REG_IIR); 2413 2414 return true; 2415 } 2416 #endif 2417 2418 #ifdef notyet 2419 bool 2420 imxuart_resume(device_t self PMF_FN_ARGS) 2421 { 2422 struct imxuart_softc *sc = device_private(self); 2423 2424 mutex_spin_enter(&sc->sc_lock); 2425 imxuart_loadchannelregs(sc); 2426 mutex_spin_exit(&sc->sc_lock); 2427 2428 return true; 2429 } 2430 #endif 2431 2432 static void 2433 imxuart_enable_debugport(struct imxuart_softc *sc) 2434 { 2435 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2436 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2437 2438 if (sc->sc_hwflags & (IMXUART_HW_CONSOLE|IMXUART_HW_KGDB)) { 2439 2440 /* Turn on line break interrupt, set carrier. */ 2441 2442 sc->sc_ucr3 |= IMX_UCR3_DSR; 2443 bus_space_write_4(iot, ioh, IMX_UCR3, sc->sc_ucr3); 2444 2445 sc->sc_ucr4 |= IMX_UCR4_BKEN; 2446 bus_space_write_4(iot, ioh, IMX_UCR4, sc->sc_ucr4); 2447 2448 sc->sc_ucr2 |= IMX_UCR2_TXEN|IMX_UCR2_RXEN| 2449 IMX_UCR2_CTS; 2450 bus_space_write_4(iot, ioh, IMX_UCR2, sc->sc_ucr2); 2451 2452 sc->sc_ucr1 |= IMX_UCR1_UARTEN; 2453 bus_space_write_4(iot, ioh, IMX_UCR1, sc->sc_ucr1); 2454 } 2455 } 2456 2457 2458 void 2459 imxuart_set_frequency(u_int freq, u_int div) 2460 { 2461 imxuart_freq = freq; 2462 imxuart_freqdiv = div; 2463 } 2464
Indexes created Mon Sep 29 21:09:56 GMT 2025