imxuart.c revision 1.5
1 /* $NetBSD: imxuart.c,v 1.5 2010/11/13 06:12:17 bsh Exp $ */ 2 3 /* 4 * Copyright (c) 2009, 2010 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* 31 * derived from sys/dev/ic/com.c 32 */ 33 34 /*- 35 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to The NetBSD Foundation 39 * by Charles M. Hannum. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 51 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 52 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 53 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 60 * POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Copyright (c) 1991 The Regents of the University of California. 65 * All rights reserved. 66 * 67 * Redistribution and use in source and binary forms, with or without 68 * modification, are permitted provided that the following conditions 69 * are met: 70 * 1. Redistributions of source code must retain the above copyright 71 * notice, this list of conditions and the following disclaimer. 72 * 2. Redistributions in binary form must reproduce the above copyright 73 * notice, this list of conditions and the following disclaimer in the 74 * documentation and/or other materials provided with the distribution. 75 * 3. Neither the name of the University nor the names of its contributors 76 * may be used to endorse or promote products derived from this software 77 * without specific prior written permission. 78 * 79 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 80 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 82 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 85 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 86 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 87 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 88 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 89 * SUCH DAMAGE. 90 * 91 * @(#)com.c 7.5 (Berkeley) 5/16/91 92 */ 93 94 /* 95 * driver for UART in i.MX SoC. 96 */ 97 98 #include <sys/cdefs.h> 99 __KERNEL_RCSID(0, "$NetBSD: imxuart.c,v 1.5 2010/11/13 06:12:17 bsh Exp $"); 100 101 #include "opt_imxuart.h" 102 #include "opt_ddb.h" 103 #include "opt_kgdb.h" 104 #include "opt_lockdebug.h" 105 #include "opt_multiprocessor.h" 106 #include "opt_ntp.h" 107 #include "opt_imxuart.h" 108 #include "opt_imx.h" 109 110 #include "rnd.h" 111 #if NRND > 0 && defined(RND_COM) 112 #include <sys/rnd.h> 113 #endif 114 115 #ifndef IMXUART_TOLERANCE 116 #define IMXUART_TOLERANCE 30 /* baud rate tolerance, in 0.1% units */ 117 #endif 118 119 #ifndef IMXUART_FREQDIV 120 #define IMXUART_FREQDIV 2 /* XXX */ 121 #endif 122 123 #ifndef IMXUART_FREQ 124 #define IMXUART_FREQ (56900000) 125 #endif 126 127 /* 128 * Override cnmagic(9) macro before including <sys/systm.h>. 129 * We need to know if cn_check_magic triggered debugger, so set a flag. 130 * Callers of cn_check_magic must declare int cn_trapped = 0; 131 * XXX: this is *ugly*! 132 */ 133 #define cn_trap() \ 134 do { \ 135 console_debugger(); \ 136 cn_trapped = 1; \ 137 } while (/* CONSTCOND */ 0) 138 139 #include <sys/param.h> 140 #include <sys/systm.h> 141 #include <sys/ioctl.h> 142 #include <sys/select.h> 143 #include <sys/poll.h> 144 #include <sys/tty.h> 145 #include <sys/proc.h> 146 #include <sys/user.h> 147 #include <sys/conf.h> 148 #include <sys/file.h> 149 #include <sys/uio.h> 150 #include <sys/kernel.h> 151 #include <sys/syslog.h> 152 #include <sys/device.h> 153 #include <sys/malloc.h> 154 #include <sys/timepps.h> 155 #include <sys/vnode.h> 156 #include <sys/kauth.h> 157 #include <sys/intr.h> 158 159 #include <sys/bus.h> 160 161 #include <arm/imx/imxuartreg.h> 162 #include <arm/imx/imxuartvar.h> 163 #include <dev/cons.h> 164 165 #ifndef IMXUART_RING_SIZE 166 #define IMXUART_RING_SIZE 2048 167 #endif 168 169 typedef struct imxuart_softc { 170 device_t sc_dev; 171 172 struct imxuart_regs { 173 bus_space_tag_t ur_iot; 174 bus_space_handle_t ur_ioh; 175 bus_addr_t ur_iobase; 176 #if 0 177 bus_size_t ur_nports; 178 bus_size_t ur_map[16]; 179 #endif 180 } sc_regs; 181 182 #define sc_bt sc_regs.ur_iot 183 #define sc_bh sc_regs.ur_ioh 184 185 uint32_t sc_intrspec_enb; 186 uint32_t sc_ucr2_d; /* target value for UCR2 */ 187 uint32_t sc_ucr[4]; /* cached value of UCRn */ 188 #define sc_ucr1 sc_ucr[0] 189 #define sc_ucr2 sc_ucr[1] 190 #define sc_ucr3 sc_ucr[2] 191 #define sc_ucr4 sc_ucr[3] 192 193 uint sc_init_cnt; 194 195 bus_addr_t sc_addr; 196 bus_size_t sc_size; 197 int sc_intr; 198 199 u_char sc_hwflags; 200 /* Hardware flag masks */ 201 #define IMXUART_HW_FLOW __BIT(0) 202 #define IMXUART_HW_DEV_OK __BIT(1) 203 #define IMXUART_HW_CONSOLE __BIT(2) 204 #define IMXUART_HW_KGDB __BIT(3) 205 206 207 bool enabled; 208 209 u_char sc_swflags; 210 211 u_char sc_rx_flags; 212 #define IMXUART_RX_TTY_BLOCKED __BIT(0) 213 #define IMXUART_RX_TTY_OVERFLOWED __BIT(1) 214 #define IMXUART_RX_IBUF_BLOCKED __BIT(2) 215 #define IMXUART_RX_IBUF_OVERFLOWED __BIT(3) 216 #define IMXUART_RX_ANY_BLOCK \ 217 (IMXUART_RX_TTY_BLOCKED|IMXUART_RX_TTY_OVERFLOWED| \ 218 IMXUART_RX_IBUF_BLOCKED|IMXUART_RX_IBUF_OVERFLOWED) 219 220 bool sc_tx_busy, sc_tx_done, sc_tx_stopped; 221 bool sc_rx_ready,sc_st_check; 222 u_short sc_txfifo_len, sc_txfifo_thresh; 223 224 uint16_t *sc_rbuf; 225 u_int sc_rbuf_size; 226 u_int sc_rbuf_in; 227 u_int sc_rbuf_out; 228 #define IMXUART_RBUF_AVAIL(sc) \ 229 ((sc->sc_rbuf_out <= sc->sc_rbuf_in) ? \ 230 (sc->sc_rbuf_in - sc->sc_rbuf_out) : \ 231 (sc->sc_rbuf_size - (sc->sc_rbuf_out - sc->sc_rbuf_in))) 232 233 #define IMXUART_RBUF_SPACE(sc) \ 234 ((sc->sc_rbuf_in <= sc->sc_rbuf_out ? \ 235 sc->sc_rbuf_size - (sc->sc_rbuf_out - sc->sc_rbuf_in) : \ 236 sc->sc_rbuf_in - sc->sc_rbuf_out) - 1) 237 /* increment ringbuffer pointer */ 238 #define IMXUART_RBUF_INC(sc,v,i) (((v) + (i))&((sc->sc_rbuf_size)-1)) 239 u_int sc_r_lowat; 240 u_int sc_r_hiwat; 241 242 /* output chunk */ 243 u_char *sc_tba; 244 u_int sc_tbc; 245 u_int sc_heldtbc; 246 /* pending parameter changes */ 247 u_char sc_pending; 248 #define IMXUART_PEND_PARAM __BIT(0) 249 #define IMXUART_PEND_SPEED __BIT(1) 250 251 252 struct callout sc_diag_callout; 253 kmutex_t sc_lock; 254 void *sc_ih; /* interrupt handler */ 255 void *sc_si; /* soft interrupt */ 256 struct tty *sc_tty; 257 258 /* power management hooks */ 259 int (*enable)(struct imxuart_softc *); 260 void (*disable)(struct imxuart_softc *); 261 262 struct { 263 ulong err; 264 ulong brk; 265 ulong prerr; 266 ulong frmerr; 267 ulong ovrrun; 268 } sc_errors; 269 270 struct imxuart_baudrate_ratio { 271 uint16_t numerator; /* UBIR */ 272 uint16_t modulator; /* UBMR */ 273 } sc_ratio; 274 275 } imxuart_softc_t; 276 277 278 int imxuspeed(long, struct imxuart_baudrate_ratio *); 279 int imxuparam(struct tty *, struct termios *); 280 void imxustart(struct tty *); 281 int imxuhwiflow(struct tty *, int); 282 283 void imxuart_shutdown(struct imxuart_softc *); 284 void imxuart_loadchannelregs(struct imxuart_softc *); 285 void imxuart_hwiflow(struct imxuart_softc *); 286 void imxuart_break(struct imxuart_softc *, bool); 287 void imxuart_modem(struct imxuart_softc *, int); 288 void tiocm_to_imxu(struct imxuart_softc *, u_long, int); 289 int imxuart_to_tiocm(struct imxuart_softc *); 290 void imxuart_iflush(struct imxuart_softc *); 291 int imxuintr(void *); 292 293 int imxuart_common_getc(dev_t, struct imxuart_regs *); 294 void imxuart_common_putc(dev_t, struct imxuart_regs *, int); 295 296 297 int imxuart_init(struct imxuart_regs *, int, tcflag_t); 298 299 int imxucngetc(dev_t); 300 void imxucnputc(dev_t, int); 301 void imxucnpollc(dev_t, int); 302 303 static void imxuintr_read(struct imxuart_softc *); 304 static void imxuintr_send(struct imxuart_softc *); 305 306 static void imxuart_enable_debugport(struct imxuart_softc *); 307 static void imxuart_disable_all_interrupts(struct imxuart_softc *); 308 static void imxuart_control_rxint(struct imxuart_softc *, bool); 309 static void imxuart_control_txint(struct imxuart_softc *, bool); 310 static u_int imxuart_txfifo_space(struct imxuart_softc *sc); 311 312 static uint32_t cflag_to_ucr2(tcflag_t, uint32_t); 313 314 CFATTACH_DECL_NEW(imxuart, sizeof(struct imxuart_softc), 315 imxuart_match, imxuart_attach, NULL, NULL); 316 317 318 #define integrate static inline 319 void imxusoft(void *); 320 integrate void imxuart_rxsoft(struct imxuart_softc *, struct tty *); 321 integrate void imxuart_txsoft(struct imxuart_softc *, struct tty *); 322 integrate void imxuart_stsoft(struct imxuart_softc *, struct tty *); 323 integrate void imxuart_schedrx(struct imxuart_softc *); 324 void imxudiag(void *); 325 static void imxuart_load_speed(struct imxuart_softc *); 326 static void imxuart_load_params(struct imxuart_softc *); 327 integrate void imxuart_load_pendings(struct imxuart_softc *); 328 329 330 extern struct cfdriver imxuart_cd; 331 332 dev_type_open(imxuopen); 333 dev_type_close(imxuclose); 334 dev_type_read(imxuread); 335 dev_type_write(imxuwrite); 336 dev_type_ioctl(imxuioctl); 337 dev_type_stop(imxustop); 338 dev_type_tty(imxutty); 339 dev_type_poll(imxupoll); 340 341 const struct cdevsw imxcom_cdevsw = { 342 imxuopen, imxuclose, imxuread, imxuwrite, imxuioctl, 343 imxustop, imxutty, imxupoll, nommap, ttykqfilter, D_TTY 344 }; 345 346 /* 347 * Make this an option variable one can patch. 348 * But be warned: this must be a power of 2! 349 */ 350 u_int imxuart_rbuf_size = IMXUART_RING_SIZE; 351 352 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 353 u_int imxuart_rbuf_hiwat = (IMXUART_RING_SIZE * 1) / 4; 354 u_int imxuart_rbuf_lowat = (IMXUART_RING_SIZE * 3) / 4; 355 356 static struct imxuart_regs imxuconsregs; 357 static int imxuconsattached; 358 static int imxuconsrate; 359 static tcflag_t imxuconscflag; 360 static struct cnm_state imxuart_cnm_state; 361 362 u_int imxuart_freq = IMXUART_FREQ; 363 u_int imxuart_freqdiv = IMXUART_FREQDIV; 364 365 #ifdef KGDB 366 #include <sys/kgdb.h> 367 368 static struct imxuart_regs imxu_kgdb_regs; 369 static int imxu_kgdb_attached; 370 371 int imxuart_kgdb_getc(void *); 372 void imxuart_kgdb_putc(void *, int); 373 #endif /* KGDB */ 374 375 #define IMXUART_UNIT_MASK 0x7ffff 376 #define IMXUART_DIALOUT_MASK 0x80000 377 378 #define IMXUART_UNIT(x) (minor(x) & IMXUART_UNIT_MASK) 379 #define IMXUART_DIALOUT(x) (minor(x) & IMXUART_DIALOUT_MASK) 380 381 #define IMXUART_ISALIVE(sc) ((sc)->enabled != 0 && \ 382 device_is_active((sc)->sc_dev)) 383 384 #define BR BUS_SPACE_BARRIER_READ 385 #define BW BUS_SPACE_BARRIER_WRITE 386 #define IMXUART_BARRIER(r, f) \ 387 bus_space_barrier((r)->ur_iot, (r)->ur_ioh, 0, IMX_UART_SIZE, (f)) 388 389 390 void 391 imxuart_attach_common(struct device *parent, struct device *self, 392 bus_space_tag_t iot, paddr_t iobase, size_t size, int intr, int flags) 393 { 394 imxuart_softc_t *sc = device_private(self); 395 struct imxuart_regs *regsp = &sc->sc_regs; 396 struct tty *tp; 397 bus_space_handle_t ioh; 398 399 aprint_naive("\n"); 400 aprint_normal("\n"); 401 402 sc->sc_dev = self; 403 404 if (size <= 0) 405 size = IMX_UART_SIZE; 406 407 sc->sc_intr = intr; 408 regsp->ur_iot = iot; 409 regsp->ur_iobase = iobase; 410 411 if (bus_space_map(iot, regsp->ur_iobase, size, 0, &ioh)) { 412 return; 413 } 414 regsp->ur_ioh = ioh; 415 416 callout_init(&sc->sc_diag_callout, 0); 417 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 418 419 bus_space_read_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 4); 420 sc->sc_ucr2_d = sc->sc_ucr2; 421 422 /* Disable interrupts before configuring the device. */ 423 imxuart_disable_all_interrupts(sc); 424 425 if (regsp->ur_iobase == imxuconsregs.ur_iobase) { 426 imxuconsattached = 1; 427 428 /* Make sure the console is always "hardwired". */ 429 #if 0 430 delay(10000); /* wait for output to finish */ 431 #endif 432 SET(sc->sc_hwflags, IMXUART_HW_CONSOLE); 433 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 434 } 435 436 437 tp = ttymalloc(); 438 tp->t_oproc = imxustart; 439 tp->t_param = imxuparam; 440 tp->t_hwiflow = imxuhwiflow; 441 442 sc->sc_tty = tp; 443 sc->sc_rbuf = malloc(sizeof (*sc->sc_rbuf) * imxuart_rbuf_size, 444 M_DEVBUF, M_NOWAIT); 445 sc->sc_rbuf_size = imxuart_rbuf_size; 446 sc->sc_rbuf_in = sc->sc_rbuf_out = 0; 447 if (sc->sc_rbuf == NULL) { 448 aprint_error_dev(sc->sc_dev, 449 "unable to allocate ring buffer\n"); 450 return; 451 } 452 453 sc->sc_txfifo_len = 32; 454 sc->sc_txfifo_thresh = 16; /* when USR1.TRDY, fifo has space 455 * for this many characters */ 456 457 tty_attach(tp); 458 459 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 460 int maj; 461 462 /* locate the major number */ 463 maj = cdevsw_lookup_major(&imxcom_cdevsw); 464 465 if (maj != NODEVMAJOR) { 466 tp->t_dev = cn_tab->cn_dev = makedev(maj, 467 device_unit(sc->sc_dev)); 468 469 aprint_normal_dev(sc->sc_dev, "console\n"); 470 } 471 } 472 473 sc->sc_ih = intr_establish(sc->sc_intr, IPL_SERIAL, IST_LEVEL, 474 imxuintr, sc); 475 if (sc->sc_ih == NULL) 476 aprint_error_dev(sc->sc_dev, "intr_establish failed\n"); 477 478 #ifdef KGDB 479 /* 480 * Allow kgdb to "take over" this port. If this is 481 * not the console and is the kgdb device, it has 482 * exclusive use. If it's the console _and_ the 483 * kgdb device, it doesn't. 484 */ 485 if (regsp->ur_iobase == imxu_kgdb_regs.ur_iobase) { 486 if (!ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 487 imxu_kgdb_attached = 1; 488 489 SET(sc->sc_hwflags, IMXUART_HW_KGDB); 490 } 491 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 492 } 493 #endif 494 495 sc->sc_si = softint_establish(SOFTINT_SERIAL, imxusoft, sc); 496 497 #if NRND > 0 && defined(RND_IMXUART) 498 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 499 RND_TYPE_TTY, 0); 500 #endif 501 502 /* if there are no enable/disable functions, assume the device 503 is always enabled */ 504 if (!sc->enable) 505 sc->enabled = 1; 506 507 imxuart_enable_debugport(sc); 508 509 SET(sc->sc_hwflags, IMXUART_HW_DEV_OK); 510 511 //shutdownhook_establish(imxuart_shutdownhook, sc); 512 513 514 #if 0 515 { 516 uint32_t reg; 517 reg = bus_space_read_4(iot, ioh, IMX_UCR1); 518 reg |= IMX_UCR1_TXDMAEN | IMX_UCR1_RXDMAEN; 519 bus_space_write_4(iot, ioh, IMX_UCR1, reg); 520 } 521 #endif 522 } 523 524 /* 525 * baudrate = RefFreq / (16 * (UMBR + 1)/(UBIR + 1)) 526 * 527 * (UBIR + 1) / (UBMR + 1) = (16 * BaurdRate) / RefFreq 528 */ 529 530 static long 531 gcd(long m, long n) 532 { 533 534 if (m < n) 535 return gcd(n, m); 536 537 if (n <= 0) 538 return m; 539 return gcd(n, m % n); 540 } 541 542 543 int 544 imxuspeed(long speed, struct imxuart_baudrate_ratio *ratio) 545 { 546 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 547 long b = 16 * speed; 548 long f = imxuart_freq / imxuart_freqdiv; 549 long d; 550 int err = 0; 551 552 /* reduce b/f */ 553 while ((f > (1<<16) || b > (1<<16)) && (d = gcd(f, b)) > 1) { 554 f /= d; 555 b /= d; 556 } 557 558 559 while (f > (1<<16) || b > (1<<16)) { 560 f /= 2; 561 b /= 2; 562 } 563 if (f <= 0 || b <= 0) 564 return -1; 565 566 #ifdef DIAGNOSTIC 567 err = divrnd(((uint64_t)imxuart_freq) * 1000 / imxuart_freqdiv, 568 (uint64_t)speed * 16 * f / b) - 1000; 569 if (err < 0) 570 err = -err; 571 #endif 572 573 ratio->numerator = b-1; 574 ratio->modulator = f-1; 575 576 if (err > IMXUART_TOLERANCE) 577 return -1; 578 579 return 0; 580 #undef divrnd 581 } 582 583 #ifdef IMXUART_DEBUG 584 int imxuart_debug = 0; 585 586 void imxustatus(struct imxuart_softc *, const char *); 587 void 588 imxustatus(struct imxuart_softc *sc, const char *str) 589 { 590 struct tty *tp = sc->sc_tty; 591 592 aprint_normal_dev(sc->sc_dev, 593 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 594 str, 595 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 596 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 597 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 598 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 599 sc->sc_tx_stopped ? '+' : '-'); 600 601 aprint_normal_dev(sc->sc_dev, 602 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 603 str, 604 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 605 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 606 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 607 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 608 sc->sc_rx_flags); 609 } 610 #endif 611 612 #if 0 613 int 614 imxuart_detach(device_t self, int flags) 615 { 616 struct imxuart_softc *sc = device_private(self); 617 int maj, mn; 618 619 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) 620 return EBUSY; 621 622 /* locate the major number */ 623 maj = cdevsw_lookup_major(&imxcom_cdevsw); 624 625 /* Nuke the vnodes for any open instances. */ 626 mn = device_unit(self); 627 vdevgone(maj, mn, mn, VCHR); 628 629 mn |= IMXUART_DIALOUT_MASK; 630 vdevgone(maj, mn, mn, VCHR); 631 632 if (sc->sc_rbuf == NULL) { 633 /* 634 * Ring buffer allocation failed in the imxuart_attach_subr, 635 * only the tty is allocated, and nothing else. 636 */ 637 ttyfree(sc->sc_tty); 638 return 0; 639 } 640 641 /* Free the receive buffer. */ 642 free(sc->sc_rbuf, M_DEVBUF); 643 644 /* Detach and free the tty. */ 645 tty_detach(sc->sc_tty); 646 ttyfree(sc->sc_tty); 647 648 /* Unhook the soft interrupt handler. */ 649 softint_disestablish(sc->sc_si); 650 651 #if NRND > 0 && defined(RND_IMXU) 652 /* Unhook the entropy source. */ 653 rnd_detach_source(&sc->rnd_source); 654 #endif 655 callout_destroy(&sc->sc_diag_callout); 656 657 /* Destroy the lock. */ 658 mutex_destroy(&sc->sc_lock); 659 660 return (0); 661 } 662 #endif 663 664 #ifdef notyet 665 int 666 imxuart_activate(device_t self, enum devact act) 667 { 668 struct imxuart_softc *sc = device_private(self); 669 int rv = 0; 670 671 switch (act) { 672 case DVACT_ACTIVATE: 673 rv = EOPNOTSUPP; 674 break; 675 676 case DVACT_DEACTIVATE: 677 if (sc->sc_hwflags & (IMXUART_HW_CONSOLE|IMXUART_HW_KGDB)) { 678 rv = EBUSY; 679 break; 680 } 681 682 if (sc->disable != NULL && sc->enabled != 0) { 683 (*sc->disable)(sc); 684 sc->enabled = 0; 685 } 686 break; 687 } 688 689 return (rv); 690 } 691 #endif 692 693 void 694 imxuart_shutdown(struct imxuart_softc *sc) 695 { 696 struct tty *tp = sc->sc_tty; 697 698 mutex_spin_enter(&sc->sc_lock); 699 700 /* If we were asserting flow control, then deassert it. */ 701 SET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED); 702 imxuart_hwiflow(sc); 703 704 /* Clear any break condition set with TIOCSBRK. */ 705 imxuart_break(sc, false); 706 707 /* 708 * Hang up if necessary. Wait a bit, so the other side has time to 709 * notice even if we immediately open the port again. 710 * Avoid tsleeping above splhigh(). 711 */ 712 if (ISSET(tp->t_cflag, HUPCL)) { 713 imxuart_modem(sc, 0); 714 mutex_spin_exit(&sc->sc_lock); 715 /* XXX will only timeout */ 716 (void) kpause(ttclos, false, hz, NULL); 717 mutex_spin_enter(&sc->sc_lock); 718 } 719 720 /* Turn off interrupts. */ 721 imxuart_disable_all_interrupts(sc); 722 /* re-enable recv interrupt for console or kgdb port */ 723 imxuart_enable_debugport(sc); 724 725 mutex_spin_exit(&sc->sc_lock); 726 727 #ifdef notyet 728 if (sc->disable) { 729 #ifdef DIAGNOSTIC 730 if (!sc->enabled) 731 panic("imxuart_shutdown: not enabled?"); 732 #endif 733 (*sc->disable)(sc); 734 sc->enabled = 0; 735 } 736 #endif 737 } 738 739 int 740 imxuopen(dev_t dev, int flag, int mode, struct lwp *l) 741 { 742 struct imxuart_softc *sc; 743 struct tty *tp; 744 int s; 745 int error; 746 747 sc = device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 748 if (sc == NULL || !ISSET(sc->sc_hwflags, IMXUART_HW_DEV_OK) || 749 sc->sc_rbuf == NULL) 750 return (ENXIO); 751 752 if (!device_is_active(sc->sc_dev)) 753 return (ENXIO); 754 755 #ifdef KGDB 756 /* 757 * If this is the kgdb port, no other use is permitted. 758 */ 759 if (ISSET(sc->sc_hwflags, IMXUART_HW_KGDB)) 760 return (EBUSY); 761 #endif 762 763 tp = sc->sc_tty; 764 765 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 766 return (EBUSY); 767 768 s = spltty(); 769 770 /* 771 * Do the following iff this is a first open. 772 */ 773 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 774 struct termios t; 775 776 tp->t_dev = dev; 777 778 779 #ifdef notyet 780 if (sc->enable) { 781 if ((*sc->enable)(sc)) { 782 splx(s); 783 aprint_error_dev(sc->sc_dev, 784 "device enable failed\n"); 785 return (EIO); 786 } 787 sc->enabled = 1; 788 } 789 #endif 790 791 mutex_spin_enter(&sc->sc_lock); 792 793 imxuart_disable_all_interrupts(sc); 794 795 /* Fetch the current modem control status, needed later. */ 796 797 #ifdef IMXUART_PPS 798 /* Clear PPS capture state on first open. */ 799 mutex_spin_enter(&timecounter_lock); 800 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 801 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 802 pps_init(&sc->sc_pps_state); 803 mutex_spin_exit(&timecounter_lock); 804 #endif 805 806 mutex_spin_exit(&sc->sc_lock); 807 808 /* 809 * Initialize the termios status to the defaults. Add in the 810 * sticky bits from TIOCSFLAGS. 811 */ 812 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 813 t.c_ospeed = imxuconsrate; 814 t.c_cflag = imxuconscflag; 815 } else { 816 t.c_ospeed = TTYDEF_SPEED; 817 t.c_cflag = TTYDEF_CFLAG; 818 } 819 t.c_ispeed = t.c_ospeed; 820 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 821 SET(t.c_cflag, CLOCAL); 822 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 823 SET(t.c_cflag, CRTSCTS); 824 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 825 SET(t.c_cflag, MDMBUF); 826 /* Make sure imxuparam() will do something. */ 827 tp->t_ospeed = 0; 828 (void) imxuparam(tp, &t); 829 tp->t_iflag = TTYDEF_IFLAG; 830 tp->t_oflag = TTYDEF_OFLAG; 831 tp->t_lflag = TTYDEF_LFLAG; 832 ttychars(tp); 833 ttsetwater(tp); 834 835 mutex_spin_enter(&sc->sc_lock); 836 837 /* 838 * Turn on DTR. We must always do this, even if carrier is not 839 * present, because otherwise we'd have to use TIOCSDTR 840 * immediately after setting CLOCAL, which applications do not 841 * expect. We always assert DTR while the device is open 842 * unless explicitly requested to deassert it. 843 */ 844 imxuart_modem(sc, 1); 845 846 /* Clear the input ring, and unblock. */ 847 sc->sc_rbuf_in = sc->sc_rbuf_out = 0; 848 imxuart_iflush(sc); 849 CLR(sc->sc_rx_flags, IMXUART_RX_ANY_BLOCK); 850 imxuart_hwiflow(sc); 851 852 /* Turn on interrupts. */ 853 imxuart_control_rxint(sc, true); 854 855 #ifdef IMXUART_DEBUG 856 if (imxuart_debug) 857 imxustatus(sc, "imxuopen "); 858 #endif 859 860 mutex_spin_exit(&sc->sc_lock); 861 } 862 863 splx(s); 864 865 #if 0 866 error = ttyopen(tp, IMXUART_DIALOUT(dev), ISSET(flag, O_NONBLOCK)); 867 #else 868 error = ttyopen(tp, 1, ISSET(flag, O_NONBLOCK)); 869 #endif 870 if (error) 871 goto bad; 872 873 error = (*tp->t_linesw->l_open)(dev, tp); 874 if (error) 875 goto bad; 876 877 return (0); 878 879 bad: 880 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 881 /* 882 * We failed to open the device, and nobody else had it opened. 883 * Clean up the state as appropriate. 884 */ 885 imxuart_shutdown(sc); 886 } 887 888 return (error); 889 } 890 891 int 892 imxuclose(dev_t dev, int flag, int mode, struct lwp *l) 893 { 894 struct imxuart_softc *sc = 895 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 896 struct tty *tp = sc->sc_tty; 897 898 /* XXX This is for cons.c. */ 899 if (!ISSET(tp->t_state, TS_ISOPEN)) 900 return (0); 901 902 (*tp->t_linesw->l_close)(tp, flag); 903 ttyclose(tp); 904 905 if (IMXUART_ISALIVE(sc) == 0) 906 return (0); 907 908 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 909 /* 910 * Although we got a last close, the device may still be in 911 * use; e.g. if this was the dialout node, and there are still 912 * processes waiting for carrier on the non-dialout node. 913 */ 914 imxuart_shutdown(sc); 915 } 916 917 return (0); 918 } 919 920 int 921 imxuread(dev_t dev, struct uio *uio, int flag) 922 { 923 struct imxuart_softc *sc = 924 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 925 struct tty *tp = sc->sc_tty; 926 927 if (IMXUART_ISALIVE(sc) == 0) 928 return (EIO); 929 930 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 931 } 932 933 int 934 imxuwrite(dev_t dev, struct uio *uio, int flag) 935 { 936 struct imxuart_softc *sc = 937 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 938 struct tty *tp = sc->sc_tty; 939 940 if (IMXUART_ISALIVE(sc) == 0) 941 return (EIO); 942 943 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 944 } 945 946 int 947 imxupoll(dev_t dev, int events, struct lwp *l) 948 { 949 struct imxuart_softc *sc = 950 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 951 struct tty *tp = sc->sc_tty; 952 953 if (IMXUART_ISALIVE(sc) == 0) 954 return (POLLHUP); 955 956 return ((*tp->t_linesw->l_poll)(tp, events, l)); 957 } 958 959 struct tty * 960 imxutty(dev_t dev) 961 { 962 struct imxuart_softc *sc = 963 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 964 struct tty *tp = sc->sc_tty; 965 966 return (tp); 967 } 968 969 int 970 imxuioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 971 { 972 struct imxuart_softc *sc; 973 struct tty *tp; 974 int error; 975 976 sc = device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev)); 977 if (sc == NULL) 978 return ENXIO; 979 if (IMXUART_ISALIVE(sc) == 0) 980 return (EIO); 981 982 tp = sc->sc_tty; 983 984 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 985 if (error != EPASSTHROUGH) 986 return (error); 987 988 error = ttioctl(tp, cmd, data, flag, l); 989 if (error != EPASSTHROUGH) 990 return (error); 991 992 error = 0; 993 switch (cmd) { 994 case TIOCSFLAGS: 995 error = kauth_authorize_device_tty(l->l_cred, 996 KAUTH_DEVICE_TTY_PRIVSET, tp); 997 break; 998 default: 999 /* nothing */ 1000 break; 1001 } 1002 if (error) { 1003 return error; 1004 } 1005 1006 mutex_spin_enter(&sc->sc_lock); 1007 1008 switch (cmd) { 1009 case TIOCSBRK: 1010 imxuart_break(sc, true); 1011 break; 1012 1013 case TIOCCBRK: 1014 imxuart_break(sc, false); 1015 break; 1016 1017 case TIOCSDTR: 1018 imxuart_modem(sc, 1); 1019 break; 1020 1021 case TIOCCDTR: 1022 imxuart_modem(sc, 0); 1023 break; 1024 1025 case TIOCGFLAGS: 1026 *(int *)data = sc->sc_swflags; 1027 break; 1028 1029 case TIOCSFLAGS: 1030 sc->sc_swflags = *(int *)data; 1031 break; 1032 1033 case TIOCMSET: 1034 case TIOCMBIS: 1035 case TIOCMBIC: 1036 tiocm_to_imxu(sc, cmd, *(int *)data); 1037 break; 1038 1039 case TIOCMGET: 1040 *(int *)data = imxuart_to_tiocm(sc); 1041 break; 1042 1043 #ifdef notyet 1044 case PPS_IOC_CREATE: 1045 case PPS_IOC_DESTROY: 1046 case PPS_IOC_GETPARAMS: 1047 case PPS_IOC_SETPARAMS: 1048 case PPS_IOC_GETCAP: 1049 case PPS_IOC_FETCH: 1050 #ifdef PPS_SYNC 1051 case PPS_IOC_KCBIND: 1052 #endif 1053 mutex_spin_enter(&timecounter_lock); 1054 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1055 mutex_spin_exit(&timecounter_lock); 1056 break; 1057 1058 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1059 mutex_spin_enter(&timecounter_lock); 1060 #ifndef PPS_TRAILING_EDGE 1061 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1062 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1063 #else 1064 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1065 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1066 #endif 1067 mutex_spin_exit(&timecounter_lock); 1068 break; 1069 #endif 1070 1071 default: 1072 error = EPASSTHROUGH; 1073 break; 1074 } 1075 1076 mutex_spin_exit(&sc->sc_lock); 1077 1078 #ifdef IMXUART_DEBUG 1079 if (imxuart_debug) 1080 imxustatus(sc, "imxuioctl "); 1081 #endif 1082 1083 return (error); 1084 } 1085 1086 integrate void 1087 imxuart_schedrx(struct imxuart_softc *sc) 1088 { 1089 sc->sc_rx_ready = 1; 1090 1091 /* Wake up the poller. */ 1092 softint_schedule(sc->sc_si); 1093 } 1094 1095 void 1096 imxuart_break(struct imxuart_softc *sc, bool onoff) 1097 { 1098 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1099 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1100 1101 if (onoff) 1102 SET(sc->sc_ucr1, IMX_UCR1_SNDBRK); 1103 else 1104 CLR(sc->sc_ucr1, IMX_UCR1_SNDBRK); 1105 1106 bus_space_write_4(iot, ioh, IMX_UCR1, sc->sc_ucr1); 1107 } 1108 1109 void 1110 imxuart_modem(struct imxuart_softc *sc, int onoff) 1111 { 1112 #ifdef notyet 1113 if (sc->sc_mcr_dtr == 0) 1114 return; 1115 1116 if (onoff) 1117 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1118 else 1119 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1120 1121 if (!sc->sc_heldchange) { 1122 if (sc->sc_tx_busy) { 1123 sc->sc_heldtbc = sc->sc_tbc; 1124 sc->sc_tbc = 0; 1125 sc->sc_heldchange = 1; 1126 } else 1127 imxuart_loadchannelregs(sc); 1128 } 1129 #endif 1130 } 1131 1132 /* 1133 * RTS output is controlled by UCR2.CTS bit. 1134 * DTR output is controlled by UCR3.DSR bit. 1135 * (i.MX reference manual uses names in DCE mode) 1136 * 1137 * note: if UCR2.CTSC == 1 for automatic HW flow control, UCR2.CTS is ignored. 1138 */ 1139 void 1140 tiocm_to_imxu(struct imxuart_softc *sc, u_long how, int ttybits) 1141 { 1142 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1143 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1144 1145 uint32_t ucr2 = sc->sc_ucr2_d; 1146 uint32_t ucr3 = sc->sc_ucr3; 1147 1148 uint32_t ucr2_mask = 0; 1149 uint32_t ucr3_mask = 0; 1150 1151 1152 if (ISSET(ttybits, TIOCM_DTR)) 1153 ucr3_mask = IMX_UCR3_DSR; 1154 if (ISSET(ttybits, TIOCM_RTS)) 1155 ucr2_mask = IMX_UCR2_CTS; 1156 1157 switch (how) { 1158 case TIOCMBIC: 1159 CLR(ucr2, ucr2_mask); 1160 CLR(ucr3, ucr3_mask); 1161 break; 1162 1163 case TIOCMBIS: 1164 SET(ucr2, ucr2_mask); 1165 SET(ucr3, ucr3_mask); 1166 break; 1167 1168 case TIOCMSET: 1169 CLR(ucr2, ucr2_mask); 1170 CLR(ucr3, ucr3_mask); 1171 SET(ucr2, ucr2_mask); 1172 SET(ucr3, ucr3_mask); 1173 break; 1174 } 1175 1176 if (ucr3 != sc->sc_ucr3) { 1177 bus_space_write_4(iot, ioh, IMX_UCR3, ucr3); 1178 sc->sc_ucr3 = ucr3; 1179 } 1180 1181 if (ucr2 == sc->sc_ucr2_d) 1182 return; 1183 1184 sc->sc_ucr2_d = ucr2; 1185 /* update CTS bit only */ 1186 ucr2 = (sc->sc_ucr2 & ~IMX_UCR2_CTS) | 1187 (ucr2 & IMX_UCR2_CTS); 1188 1189 bus_space_write_4(iot, ioh, IMX_UCR2, ucr2); 1190 sc->sc_ucr2 = ucr2; 1191 } 1192 1193 int 1194 imxuart_to_tiocm(struct imxuart_softc *sc) 1195 { 1196 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1197 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1198 int ttybits = 0; 1199 uint32_t usr[2]; 1200 1201 if (ISSET(sc->sc_ucr3, IMX_UCR3_DSR)) 1202 SET(ttybits, TIOCM_DTR); 1203 if (ISSET(sc->sc_ucr2, IMX_UCR2_CTS)) 1204 SET(ttybits, TIOCM_RTS); 1205 1206 bus_space_read_region_4(iot, ioh, IMX_USR1, usr, 2); 1207 1208 if (ISSET(usr[0], IMX_USR1_RTSS)) 1209 SET(ttybits, TIOCM_CTS); 1210 1211 if (ISSET(usr[1], IMX_USR2_DCDIN)) 1212 SET(ttybits, TIOCM_CD); 1213 1214 #if 0 1215 /* XXXbsh: I couldn't find the way to read ipp_uart_dsr_dte_i signal, 1216 although there are bits in UART registers to detect delta of DSR. 1217 */ 1218 if (ISSET(imxubits, MSR_DSR)) 1219 SET(ttybits, TIOCM_DSR); 1220 #endif 1221 1222 if (ISSET(usr[1], IMX_USR2_RIIN)) 1223 SET(ttybits, TIOCM_RI); 1224 1225 1226 #ifdef notyet 1227 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1228 SET(ttybits, TIOCM_LE); 1229 #endif 1230 1231 return (ttybits); 1232 } 1233 1234 static uint32_t 1235 cflag_to_ucr2(tcflag_t cflag, uint32_t oldval) 1236 { 1237 uint32_t val = oldval; 1238 1239 CLR(val,IMX_UCR2_WS|IMX_UCR2_PREN|IMX_UCR2_PROE|IMX_UCR2_STPB); 1240 1241 switch (cflag & CSIZE) { 1242 case CS5: 1243 case CS6: 1244 /* not suppreted. use 7-bits */ 1245 case CS7: 1246 break; 1247 case CS8: 1248 SET(val, IMX_UCR2_WS); 1249 break; 1250 } 1251 1252 1253 if (ISSET(cflag, PARENB)) { 1254 SET(val, IMX_UCR2_PREN); 1255 1256 /* odd parity */ 1257 if (!ISSET(cflag, PARODD)) 1258 SET(val, IMX_UCR2_PROE); 1259 } 1260 1261 if (ISSET(cflag, CSTOPB)) 1262 SET(val, IMX_UCR2_STPB); 1263 1264 val |= IMX_UCR2_TXEN| IMX_UCR2_RXEN|IMX_UCR2_SRST; 1265 1266 return val; 1267 } 1268 1269 int 1270 imxuparam(struct tty *tp, struct termios *t) 1271 { 1272 struct imxuart_softc *sc = 1273 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1274 struct imxuart_baudrate_ratio ratio; 1275 uint32_t ucr2; 1276 bool change_speed = tp->t_ospeed != t->c_ospeed; 1277 1278 if (IMXUART_ISALIVE(sc) == 0) 1279 return (EIO); 1280 1281 /* Check requested parameters. */ 1282 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1283 return (EINVAL); 1284 1285 /* 1286 * For the console, always force CLOCAL and !HUPCL, so that the port 1287 * is always active. 1288 */ 1289 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1290 ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) { 1291 SET(t->c_cflag, CLOCAL); 1292 CLR(t->c_cflag, HUPCL); 1293 } 1294 1295 /* 1296 * If there were no changes, don't do anything. This avoids dropping 1297 * input and improves performance when all we did was frob things like 1298 * VMIN and VTIME. 1299 */ 1300 if ( !change_speed && tp->t_cflag == t->c_cflag) 1301 return (0); 1302 1303 if (change_speed) { 1304 /* calculate baudrate modulator value */ 1305 if (imxuspeed(t->c_ospeed, &ratio) < 0) 1306 return (EINVAL); 1307 sc->sc_ratio = ratio; 1308 } 1309 1310 ucr2 = cflag_to_ucr2(t->c_cflag, sc->sc_ucr2_d); 1311 1312 mutex_spin_enter(&sc->sc_lock); 1313 1314 #if 0 /* flow control stuff. not yet */ 1315 /* 1316 * If we're not in a mode that assumes a connection is present, then 1317 * ignore carrier changes. 1318 */ 1319 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1320 sc->sc_msr_dcd = 0; 1321 else 1322 sc->sc_msr_dcd = MSR_DCD; 1323 /* 1324 * Set the flow control pins depending on the current flow control 1325 * mode. 1326 */ 1327 if (ISSET(t->c_cflag, CRTSCTS)) { 1328 sc->sc_mcr_dtr = MCR_DTR; 1329 sc->sc_mcr_rts = MCR_RTS; 1330 sc->sc_msr_cts = MSR_CTS; 1331 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1332 } else if (ISSET(t->c_cflag, MDMBUF)) { 1333 /* 1334 * For DTR/DCD flow control, make sure we don't toggle DTR for 1335 * carrier detection. 1336 */ 1337 sc->sc_mcr_dtr = 0; 1338 sc->sc_mcr_rts = MCR_DTR; 1339 sc->sc_msr_cts = MSR_DCD; 1340 sc->sc_efr = 0; 1341 } else { 1342 /* 1343 * If no flow control, then always set RTS. This will make 1344 * the other side happy if it mistakenly thinks we're doing 1345 * RTS/CTS flow control. 1346 */ 1347 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1348 sc->sc_mcr_rts = 0; 1349 sc->sc_msr_cts = 0; 1350 sc->sc_efr = 0; 1351 if (ISSET(sc->sc_mcr, MCR_DTR)) 1352 SET(sc->sc_mcr, MCR_RTS); 1353 else 1354 CLR(sc->sc_mcr, MCR_RTS); 1355 } 1356 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1357 #endif 1358 1359 /* And copy to tty. */ 1360 tp->t_ispeed = t->c_ospeed; 1361 tp->t_ospeed = t->c_ospeed; 1362 tp->t_cflag = t->c_cflag; 1363 1364 if (!change_speed && ucr2 == sc->sc_ucr2_d) { 1365 /* noop */ 1366 } 1367 else if (!sc->sc_pending && !sc->sc_tx_busy) { 1368 if (ucr2 != sc->sc_ucr2_d) { 1369 sc->sc_ucr2_d = ucr2; 1370 imxuart_load_params(sc); 1371 } 1372 if (change_speed) 1373 imxuart_load_speed(sc); 1374 } 1375 else { 1376 if (!sc->sc_pending) { 1377 sc->sc_heldtbc = sc->sc_tbc; 1378 sc->sc_tbc = 0; 1379 } 1380 sc->sc_pending |= 1381 (ucr2 == sc->sc_ucr2_d ? 0 : IMXUART_PEND_PARAM) | 1382 (change_speed ? 0 : IMXUART_PEND_SPEED); 1383 sc->sc_ucr2_d = ucr2; 1384 } 1385 1386 if (!ISSET(t->c_cflag, CHWFLOW)) { 1387 /* Disable the high water mark. */ 1388 sc->sc_r_hiwat = 0; 1389 sc->sc_r_lowat = 0; 1390 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED)) { 1391 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED); 1392 imxuart_schedrx(sc); 1393 } 1394 if (ISSET(sc->sc_rx_flags, 1395 IMXUART_RX_TTY_BLOCKED|IMXUART_RX_IBUF_BLOCKED)) { 1396 CLR(sc->sc_rx_flags, 1397 IMXUART_RX_TTY_BLOCKED|IMXUART_RX_IBUF_BLOCKED); 1398 imxuart_hwiflow(sc); 1399 } 1400 } else { 1401 sc->sc_r_hiwat = imxuart_rbuf_hiwat; 1402 sc->sc_r_lowat = imxuart_rbuf_lowat; 1403 } 1404 1405 mutex_spin_exit(&sc->sc_lock); 1406 1407 #if 0 1408 /* 1409 * Update the tty layer's idea of the carrier bit, in case we changed 1410 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1411 * explicit request. 1412 */ 1413 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1414 #else 1415 /* XXX: always report that we have DCD */ 1416 (void) (*tp->t_linesw->l_modem)(tp, 1); 1417 #endif 1418 1419 #ifdef IMXUART_DEBUG 1420 if (imxuart_debug) 1421 imxustatus(sc, "imxuparam "); 1422 #endif 1423 1424 if (!ISSET(t->c_cflag, CHWFLOW)) { 1425 if (sc->sc_tx_stopped) { 1426 sc->sc_tx_stopped = 0; 1427 imxustart(tp); 1428 } 1429 } 1430 1431 return (0); 1432 } 1433 1434 void 1435 imxuart_iflush(struct imxuart_softc *sc) 1436 { 1437 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1438 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1439 #ifdef DIAGNOSTIC 1440 uint32_t reg = 0xffff; 1441 #endif 1442 int timo; 1443 1444 timo = 50000; 1445 /* flush any pending I/O */ 1446 while (ISSET(bus_space_read_4(iot, ioh, IMX_USR2), IMX_USR2_RDR) 1447 && --timo) 1448 #ifdef DIAGNOSTIC 1449 reg = 1450 #else 1451 (void) 1452 #endif 1453 bus_space_read_4(iot, ioh, IMX_URXD); 1454 #ifdef DIAGNOSTIC 1455 if (!timo) 1456 aprint_error_dev(sc->sc_dev, "imxuart_iflush timeout %02x\n", reg); 1457 #endif 1458 } 1459 1460 int 1461 imxuhwiflow(struct tty *tp, int block) 1462 { 1463 struct imxuart_softc *sc = 1464 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1465 1466 if (IMXUART_ISALIVE(sc) == 0) 1467 return (0); 1468 1469 #ifdef notyet 1470 if (sc->sc_mcr_rts == 0) 1471 return (0); 1472 #endif 1473 1474 mutex_spin_enter(&sc->sc_lock); 1475 1476 if (block) { 1477 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) { 1478 SET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED); 1479 imxuart_hwiflow(sc); 1480 } 1481 } else { 1482 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED)) { 1483 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED); 1484 imxuart_schedrx(sc); 1485 } 1486 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) { 1487 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED); 1488 imxuart_hwiflow(sc); 1489 } 1490 } 1491 1492 mutex_spin_exit(&sc->sc_lock); 1493 return (1); 1494 } 1495 1496 /* 1497 * (un)block input via hw flowcontrol 1498 */ 1499 void 1500 imxuart_hwiflow(struct imxuart_softc *sc) 1501 { 1502 #ifdef notyet 1503 struct imxuart_regs *regsp= &sc->sc_regs; 1504 1505 if (sc->sc_mcr_rts == 0) 1506 return; 1507 1508 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1509 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1510 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1511 } else { 1512 SET(sc->sc_mcr, sc->sc_mcr_rts); 1513 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1514 } 1515 UR_WRITE_1(regsp, IMXUART_REG_MCR, sc->sc_mcr_active); 1516 #endif 1517 } 1518 1519 1520 void 1521 imxustart(struct tty *tp) 1522 { 1523 struct imxuart_softc *sc = 1524 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1525 int s; 1526 u_char *tba; 1527 int tbc; 1528 u_int n; 1529 u_int space; 1530 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1531 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1532 1533 if (IMXUART_ISALIVE(sc) == 0) 1534 return; 1535 1536 s = spltty(); 1537 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1538 goto out; 1539 if (sc->sc_tx_stopped) 1540 goto out; 1541 if (!ttypull(tp)) 1542 goto out; 1543 1544 /* Grab the first contiguous region of buffer space. */ 1545 tba = tp->t_outq.c_cf; 1546 tbc = ndqb(&tp->t_outq, 0); 1547 1548 mutex_spin_enter(&sc->sc_lock); 1549 1550 sc->sc_tba = tba; 1551 sc->sc_tbc = tbc; 1552 1553 SET(tp->t_state, TS_BUSY); 1554 sc->sc_tx_busy = 1; 1555 1556 space = imxuart_txfifo_space(sc); 1557 n = MIN(sc->sc_tbc, space); 1558 1559 bus_space_write_multi_1(iot, ioh, IMX_UTXD, sc->sc_tba, n); 1560 sc->sc_tbc -= n; 1561 sc->sc_tba += n; 1562 1563 /* Enable transmit completion interrupts */ 1564 imxuart_control_txint(sc, true); 1565 1566 mutex_spin_exit(&sc->sc_lock); 1567 out: 1568 splx(s); 1569 return; 1570 } 1571 1572 /* 1573 * Stop output on a line. 1574 */ 1575 void 1576 imxustop(struct tty *tp, int flag) 1577 { 1578 struct imxuart_softc *sc = 1579 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev)); 1580 1581 mutex_spin_enter(&sc->sc_lock); 1582 if (ISSET(tp->t_state, TS_BUSY)) { 1583 /* Stop transmitting at the next chunk. */ 1584 sc->sc_tbc = 0; 1585 sc->sc_heldtbc = 0; 1586 if (!ISSET(tp->t_state, TS_TTSTOP)) 1587 SET(tp->t_state, TS_FLUSH); 1588 } 1589 mutex_spin_exit(&sc->sc_lock); 1590 } 1591 1592 void 1593 imxudiag(void *arg) 1594 { 1595 #ifdef notyet 1596 struct imxuart_softc *sc = arg; 1597 int overflows, floods; 1598 1599 mutex_spin_enter(&sc->sc_lock); 1600 overflows = sc->sc_overflows; 1601 sc->sc_overflows = 0; 1602 floods = sc->sc_floods; 1603 sc->sc_floods = 0; 1604 sc->sc_errors = 0; 1605 mutex_spin_exit(&sc->sc_lock); 1606 1607 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1608 device_xname(sc->sc_dev), 1609 overflows, overflows == 1 ? "" : "s", 1610 floods, floods == 1 ? "" : "s"); 1611 #endif 1612 } 1613 1614 integrate void 1615 imxuart_rxsoft(struct imxuart_softc *sc, struct tty *tp) 1616 { 1617 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1618 u_int cc, scc, outp; 1619 uint16_t data; 1620 u_int code; 1621 1622 scc = cc = IMXUART_RBUF_AVAIL(sc); 1623 1624 #if 0 1625 if (cc == imxuart_rbuf_size-1) { 1626 sc->sc_floods++; 1627 if (sc->sc_errors++ == 0) 1628 callout_reset(&sc->sc_diag_callout, 60 * hz, 1629 imxudiag, sc); 1630 } 1631 #endif 1632 1633 /* If not yet open, drop the entire buffer content here */ 1634 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1635 sc->sc_rbuf_out = sc->sc_rbuf_in; 1636 cc = 0; 1637 } 1638 1639 outp = sc->sc_rbuf_out; 1640 1641 #define ERRBITS (IMX_URXD_PRERR|IMX_URXD_BRK|IMX_URXD_FRMERR|IMX_URXD_OVRRUN) 1642 1643 while (cc) { 1644 data = sc->sc_rbuf[outp]; 1645 code = data & IMX_URXD_RX_DATA; 1646 if (ISSET(data, ERRBITS)) { 1647 if (sc->sc_errors.err == 0) 1648 callout_reset(&sc->sc_diag_callout, 1649 60 * hz, imxudiag, sc); 1650 if (ISSET(data, IMX_URXD_OVRRUN)) 1651 sc->sc_errors.ovrrun++; 1652 if (ISSET(data, IMX_URXD_BRK)) { 1653 sc->sc_errors.brk++; 1654 SET(code, TTY_FE); 1655 } 1656 if (ISSET(data, IMX_URXD_FRMERR)) { 1657 sc->sc_errors.frmerr++; 1658 SET(code, TTY_FE); 1659 } 1660 if (ISSET(data, IMX_URXD_PRERR)) { 1661 sc->sc_errors.prerr++; 1662 SET(code, TTY_PE); 1663 } 1664 } 1665 if ((*rint)(code, tp) == -1) { 1666 /* 1667 * The line discipline's buffer is out of space. 1668 */ 1669 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) { 1670 /* 1671 * We're either not using flow control, or the 1672 * line discipline didn't tell us to block for 1673 * some reason. Either way, we have no way to 1674 * know when there's more space available, so 1675 * just drop the rest of the data. 1676 */ 1677 sc->sc_rbuf_out = sc->sc_rbuf_in; 1678 cc = 0; 1679 } else { 1680 /* 1681 * Don't schedule any more receive processing 1682 * until the line discipline tells us there's 1683 * space available (through imxuhwiflow()). 1684 * Leave the rest of the data in the input 1685 * buffer. 1686 */ 1687 SET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED); 1688 } 1689 break; 1690 } 1691 outp = IMXUART_RBUF_INC(sc, outp, 1); 1692 cc--; 1693 } 1694 1695 if (cc != scc) { 1696 sc->sc_rbuf_out = outp; 1697 mutex_spin_enter(&sc->sc_lock); 1698 1699 cc = IMXUART_RBUF_SPACE(sc); 1700 1701 /* Buffers should be ok again, release possible block. */ 1702 if (cc >= sc->sc_r_lowat) { 1703 if (ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_OVERFLOWED)) { 1704 CLR(sc->sc_rx_flags, IMXUART_RX_IBUF_OVERFLOWED); 1705 imxuart_control_rxint(sc, true); 1706 } 1707 if (ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED)) { 1708 CLR(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED); 1709 imxuart_hwiflow(sc); 1710 } 1711 } 1712 mutex_spin_exit(&sc->sc_lock); 1713 } 1714 } 1715 1716 integrate void 1717 imxuart_txsoft(struct imxuart_softc *sc, struct tty *tp) 1718 { 1719 1720 CLR(tp->t_state, TS_BUSY); 1721 if (ISSET(tp->t_state, TS_FLUSH)) 1722 CLR(tp->t_state, TS_FLUSH); 1723 else 1724 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1725 (*tp->t_linesw->l_start)(tp); 1726 } 1727 1728 integrate void 1729 imxuart_stsoft(struct imxuart_softc *sc, struct tty *tp) 1730 { 1731 #ifdef notyet 1732 u_char msr, delta; 1733 1734 mutex_spin_enter(&sc->sc_lock); 1735 msr = sc->sc_msr; 1736 delta = sc->sc_msr_delta; 1737 sc->sc_msr_delta = 0; 1738 mutex_spin_exit(&sc->sc_lock); 1739 1740 if (ISSET(delta, sc->sc_msr_dcd)) { 1741 /* 1742 * Inform the tty layer that carrier detect changed. 1743 */ 1744 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1745 } 1746 1747 if (ISSET(delta, sc->sc_msr_cts)) { 1748 /* Block or unblock output according to flow control. */ 1749 if (ISSET(msr, sc->sc_msr_cts)) { 1750 sc->sc_tx_stopped = 0; 1751 (*tp->t_linesw->l_start)(tp); 1752 } else { 1753 sc->sc_tx_stopped = 1; 1754 } 1755 } 1756 1757 #endif 1758 #ifdef IMXUART_DEBUG 1759 if (imxuart_debug) 1760 imxustatus(sc, "imxuart_stsoft"); 1761 #endif 1762 } 1763 1764 void 1765 imxusoft(void *arg) 1766 { 1767 struct imxuart_softc *sc = arg; 1768 struct tty *tp; 1769 1770 if (IMXUART_ISALIVE(sc) == 0) 1771 return; 1772 1773 tp = sc->sc_tty; 1774 1775 if (sc->sc_rx_ready) { 1776 sc->sc_rx_ready = 0; 1777 imxuart_rxsoft(sc, tp); 1778 } 1779 1780 if (sc->sc_st_check) { 1781 sc->sc_st_check = 0; 1782 imxuart_stsoft(sc, tp); 1783 } 1784 1785 if (sc->sc_tx_done) { 1786 sc->sc_tx_done = 0; 1787 imxuart_txsoft(sc, tp); 1788 } 1789 } 1790 1791 int 1792 imxuintr(void *arg) 1793 { 1794 struct imxuart_softc *sc = arg; 1795 uint32_t usr1, usr2; 1796 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1797 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1798 1799 1800 if (IMXUART_ISALIVE(sc) == 0) 1801 return (0); 1802 1803 mutex_spin_enter(&sc->sc_lock); 1804 1805 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1806 1807 1808 do { 1809 bus_space_write_4(iot, ioh, IMX_USR2, 1810 usr2 & (IMX_USR2_BRCD|IMX_USR2_ORE)); 1811 if (usr2 & IMX_USR2_BRCD) { 1812 /* Break signal detected */ 1813 int cn_trapped = 0; 1814 1815 cn_check_magic(sc->sc_tty->t_dev, 1816 CNC_BREAK, imxuart_cnm_state); 1817 if (cn_trapped) 1818 continue; 1819 #if defined(KGDB) && !defined(DDB) 1820 if (ISSET(sc->sc_hwflags, IMXUART_HW_KGDB)) { 1821 kgdb_connect(1); 1822 continue; 1823 } 1824 #endif 1825 } 1826 1827 if (usr2 & IMX_USR2_RDR) 1828 imxuintr_read(sc); 1829 1830 #ifdef IMXUART_PPS 1831 { 1832 u_char msr, delta; 1833 1834 msr = CSR_READ_1(regsp, IMXUART_REG_MSR); 1835 delta = msr ^ sc->sc_msr; 1836 sc->sc_msr = msr; 1837 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 1838 (delta & MSR_DCD)) { 1839 mutex_spin_enter(&timecounter_lock); 1840 pps_capture(&sc->sc_pps_state); 1841 pps_event(&sc->sc_pps_state, 1842 (msr & MSR_DCD) ? 1843 PPS_CAPTUREASSERT : 1844 PPS_CAPTURECLEAR); 1845 mutex_spin_exit(&timecounter_lock); 1846 } 1847 } 1848 #endif 1849 1850 #ifdef notyet 1851 /* 1852 * Process normal status changes 1853 */ 1854 if (ISSET(delta, sc->sc_msr_mask)) { 1855 SET(sc->sc_msr_delta, delta); 1856 1857 /* 1858 * Stop output immediately if we lose the output 1859 * flow control signal or carrier detect. 1860 */ 1861 if (ISSET(~msr, sc->sc_msr_mask)) { 1862 sc->sc_tbc = 0; 1863 sc->sc_heldtbc = 0; 1864 #ifdef IMXUART_DEBUG 1865 if (imxuart_debug) 1866 imxustatus(sc, "imxuintr "); 1867 #endif 1868 } 1869 1870 sc->sc_st_check = 1; 1871 } 1872 #endif 1873 1874 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1875 } while (usr2 & (IMX_USR2_RDR|IMX_USR2_BRCD)); 1876 1877 usr1 = bus_space_read_4(iot, ioh, IMX_USR1); 1878 if (usr1 & IMX_USR1_TRDY) 1879 imxuintr_send(sc); 1880 1881 mutex_spin_exit(&sc->sc_lock); 1882 1883 /* Wake up the poller. */ 1884 softint_schedule(sc->sc_si); 1885 1886 #if NRND > 0 && defined(RND_COM) 1887 rnd_add_uint32(&sc->rnd_source, iir | lsr); 1888 #endif 1889 1890 return (1); 1891 } 1892 1893 1894 /* 1895 * called when there is least one character in rxfifo 1896 * 1897 */ 1898 1899 static void 1900 imxuintr_read(struct imxuart_softc *sc) 1901 { 1902 int cc; 1903 uint16_t rd; 1904 uint32_t usr2; 1905 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1906 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1907 1908 cc = IMXUART_RBUF_SPACE(sc); 1909 1910 /* clear aging timer interrupt */ 1911 bus_space_write_4(iot, ioh, IMX_USR1, IMX_USR1_AGTIM); 1912 1913 while (cc > 0) { 1914 int cn_trapped = 0; 1915 1916 1917 sc->sc_rbuf[sc->sc_rbuf_in] = rd = 1918 bus_space_read_4(iot, ioh, IMX_URXD); 1919 1920 cn_check_magic(sc->sc_tty->t_dev, 1921 rd & 0xff, imxuart_cnm_state); 1922 1923 if (!cn_trapped) { 1924 sc->sc_rbuf_in = IMXUART_RBUF_INC(sc, sc->sc_rbuf_in, 1); 1925 cc--; 1926 } 1927 1928 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1929 if (!(usr2 & IMX_USR2_RDR)) 1930 break; 1931 } 1932 1933 /* 1934 * Current string of incoming characters ended because 1935 * no more data was available or we ran out of space. 1936 * Schedule a receive event if any data was received. 1937 * If we're out of space, turn off receive interrupts. 1938 */ 1939 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED)) 1940 sc->sc_rx_ready = 1; 1941 /* 1942 * See if we are in danger of overflowing a buffer. If 1943 * so, use hardware flow control to ease the pressure. 1944 */ 1945 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED) && 1946 cc < sc->sc_r_hiwat) { 1947 sc->sc_rx_flags |= IMXUART_RX_IBUF_BLOCKED; 1948 imxuart_hwiflow(sc); 1949 } 1950 1951 /* 1952 * If we're out of space, disable receive interrupts 1953 * until the queue has drained a bit. 1954 */ 1955 if (!cc) { 1956 sc->sc_rx_flags |= IMXUART_RX_IBUF_OVERFLOWED; 1957 imxuart_control_rxint(sc, false); 1958 } 1959 } 1960 1961 1962 1963 /* 1964 * find how many chars we can put into tx-fifo 1965 */ 1966 static u_int 1967 imxuart_txfifo_space(struct imxuart_softc *sc) 1968 { 1969 uint32_t usr1, usr2; 1970 u_int cc; 1971 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1972 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1973 1974 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1975 if (usr2 & IMX_USR2_TXFE) 1976 cc = sc->sc_txfifo_len; 1977 else { 1978 usr1 = bus_space_read_4(iot, ioh, IMX_USR1); 1979 if (usr1 & IMX_USR1_TRDY) 1980 cc = sc->sc_txfifo_thresh; 1981 else 1982 cc = 0; 1983 } 1984 1985 return cc; 1986 } 1987 1988 void 1989 imxuintr_send(struct imxuart_softc *sc) 1990 { 1991 uint32_t usr2; 1992 bus_space_tag_t iot = sc->sc_regs.ur_iot; 1993 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 1994 int cc = 0; 1995 1996 usr2 = bus_space_read_4(iot, ioh, IMX_USR2); 1997 1998 if (sc->sc_pending) { 1999 if (usr2 & IMX_USR2_TXFE) { 2000 imxuart_load_pendings(sc); 2001 sc->sc_tbc = sc->sc_heldtbc; 2002 sc->sc_heldtbc = 0; 2003 } 2004 else { 2005 /* wait for TX fifo empty */ 2006 imxuart_control_txint(sc, true); 2007 return; 2008 } 2009 } 2010 2011 cc = imxuart_txfifo_space(sc); 2012 cc = MIN(cc, sc->sc_tbc); 2013 2014 if (cc > 0) { 2015 bus_space_write_multi_1(iot, ioh, IMX_UTXD, sc->sc_tba, cc); 2016 sc->sc_tbc -= cc; 2017 sc->sc_tba += cc; 2018 } 2019 2020 if (sc->sc_tbc > 0) 2021 imxuart_control_txint(sc, true); 2022 else { 2023 /* no more chars to send. 2024 we don't need tx interrupt any more. */ 2025 imxuart_control_txint(sc, false); 2026 if (sc->sc_tx_busy) { 2027 sc->sc_tx_busy = 0; 2028 sc->sc_tx_done = 1; 2029 } 2030 } 2031 } 2032 2033 static void 2034 imxuart_disable_all_interrupts(struct imxuart_softc *sc) 2035 { 2036 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2037 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2038 2039 sc->sc_ucr1 &= ~IMXUART_INTRS_UCR1; 2040 sc->sc_ucr2 &= ~IMXUART_INTRS_UCR2; 2041 sc->sc_ucr3 &= ~IMXUART_INTRS_UCR3; 2042 sc->sc_ucr4 &= ~IMXUART_INTRS_UCR4; 2043 2044 2045 bus_space_write_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 4); 2046 } 2047 2048 static void 2049 imxuart_control_rxint(struct imxuart_softc *sc, bool enable) 2050 { 2051 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2052 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2053 uint32_t ucr1, ucr2; 2054 2055 ucr1 = sc->sc_ucr1; 2056 ucr2 = sc->sc_ucr2; 2057 2058 if (enable) { 2059 ucr1 |= IMX_UCR1_RRDYEN; 2060 ucr2 |= IMX_UCR2_ATEN; 2061 } 2062 else { 2063 ucr1 &= ~IMX_UCR1_RRDYEN; 2064 ucr2 &= ~IMX_UCR2_ATEN; 2065 } 2066 2067 if (ucr1 != sc->sc_ucr1 || ucr2 != sc->sc_ucr2) { 2068 sc->sc_ucr1 = ucr1; 2069 sc->sc_ucr2 = ucr2; 2070 bus_space_write_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 2); 2071 } 2072 } 2073 2074 static void 2075 imxuart_control_txint(struct imxuart_softc *sc, bool enable) 2076 { 2077 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2078 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2079 uint32_t ucr1; 2080 uint32_t mask; 2081 2082 /* if parameter change is pending, get interrupt when Tx fifo 2083 is completely empty. otherwise, get interrupt when txfifo 2084 has less characters than threshold */ 2085 mask = sc->sc_pending ? IMX_UCR1_TXMPTYEN : IMX_UCR1_TRDYEN; 2086 2087 ucr1 = sc->sc_ucr1; 2088 2089 CLR(ucr1, IMX_UCR1_TXMPTYEN|IMX_UCR1_TRDYEN); 2090 if (enable) 2091 SET(ucr1, mask); 2092 2093 if (ucr1 != sc->sc_ucr1) { 2094 bus_space_write_4(iot, ioh, IMX_UCR1, ucr1); 2095 sc->sc_ucr1 = ucr1; 2096 } 2097 } 2098 2099 2100 static void 2101 imxuart_load_params(struct imxuart_softc *sc) 2102 { 2103 uint32_t ucr2; 2104 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2105 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2106 2107 ucr2 = (sc->sc_ucr2_d & ~IMX_UCR2_ATEN) | 2108 (sc->sc_ucr2 & IMX_UCR2_ATEN); 2109 2110 bus_space_write_4(iot, ioh, IMX_UCR2, ucr2); 2111 sc->sc_ucr2 = ucr2; 2112 } 2113 2114 static void 2115 imxuart_load_speed(struct imxuart_softc *sc) 2116 { 2117 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2118 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2119 int n, rfdiv, ufcr; 2120 2121 #ifdef notyet 2122 /* 2123 * Set the FIFO threshold based on the receive speed. 2124 * 2125 * * If it's a low speed, it's probably a mouse or some other 2126 * interactive device, so set the threshold low. 2127 * * If it's a high speed, trim the trigger level down to prevent 2128 * overflows. 2129 * * Otherwise set it a bit higher. 2130 */ 2131 if (t->c_ospeed <= 1200) 2132 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 2133 else if (t->c_ospeed <= 38400) 2134 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 2135 else 2136 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 2137 #endif 2138 2139 n = 32 - sc->sc_txfifo_thresh; 2140 n = MAX(2, n); 2141 2142 rfdiv = IMX_UFCR_DIVIDER_TO_RFDIV(imxuart_freqdiv); 2143 2144 ufcr = (n << IMX_UFCR_TXTL_SHIFT) | 2145 (rfdiv << IMX_UFCR_RFDIV_SHIFT) | 2146 (16 << IMX_UFCR_RXTL_SHIFT); 2147 2148 /* keep DCE/DTE bit */ 2149 ufcr |= bus_space_read_4(iot, ioh, IMX_UFCR) & IMX_UFCR_DCEDTE; 2150 2151 bus_space_write_4(iot, ioh, IMX_UFCR, ufcr); 2152 2153 /* UBIR must updated before UBMR */ 2154 bus_space_write_4(iot, ioh, 2155 IMX_UBIR, sc->sc_ratio.numerator); 2156 bus_space_write_4(iot, ioh, 2157 IMX_UBMR, sc->sc_ratio.modulator); 2158 2159 2160 } 2161 2162 2163 static void 2164 imxuart_load_pendings(struct imxuart_softc *sc) 2165 { 2166 if (sc->sc_pending & IMXUART_PEND_PARAM) 2167 imxuart_load_params(sc); 2168 if (sc->sc_pending & IMXUART_PEND_SPEED) 2169 imxuart_load_speed(sc); 2170 sc->sc_pending = 0; 2171 } 2172 2173 #if defined(IMXUARTCONSOLE) || defined(KGDB) 2174 2175 /* 2176 * The following functions are polled getc and putc routines, shared 2177 * by the console and kgdb glue. 2178 * 2179 * The read-ahead code is so that you can detect pending in-band 2180 * cn_magic in polled mode while doing output rather than having to 2181 * wait until the kernel decides it needs input. 2182 */ 2183 2184 #define READAHEAD_RING_LEN 16 2185 static int imxuart_readahead[READAHEAD_RING_LEN]; 2186 static int imxuart_readahead_in = 0; 2187 static int imxuart_readahead_out = 0; 2188 #define READAHEAD_IS_EMPTY() (imxuart_readahead_in==imxuart_readahead_out) 2189 #define READAHEAD_IS_FULL() \ 2190 (((imxuart_readahead_in+1) & (READAHEAD_RING_LEN-1)) ==imxuart_readahead_out) 2191 2192 int 2193 imxuart_common_getc(dev_t dev, struct imxuart_regs *regsp) 2194 { 2195 int s = splserial(); 2196 u_char c; 2197 bus_space_tag_t iot = regsp->ur_iot; 2198 bus_space_handle_t ioh = regsp->ur_ioh; 2199 uint32_t usr2; 2200 2201 /* got a character from reading things earlier */ 2202 if (imxuart_readahead_in != imxuart_readahead_out) { 2203 2204 c = imxuart_readahead[imxuart_readahead_out]; 2205 imxuart_readahead_out = (imxuart_readahead_out + 1) & 2206 (READAHEAD_RING_LEN-1); 2207 splx(s); 2208 return (c); 2209 } 2210 2211 /* block until a character becomes available */ 2212 while (!((usr2 = bus_space_read_4(iot, ioh, IMX_USR2)) & IMX_USR2_RDR)) 2213 ; 2214 2215 c = 0xff & bus_space_read_4(iot, ioh, IMX_URXD); 2216 2217 { 2218 int cn_trapped = 0; /* unused */ 2219 #ifdef DDB 2220 extern int db_active; 2221 if (!db_active) 2222 #endif 2223 cn_check_magic(dev, c, imxuart_cnm_state); 2224 } 2225 splx(s); 2226 return (c); 2227 } 2228 2229 void 2230 imxuart_common_putc(dev_t dev, struct imxuart_regs *regsp, int c) 2231 { 2232 int s = splserial(); 2233 int cin, timo; 2234 bus_space_tag_t iot = regsp->ur_iot; 2235 bus_space_handle_t ioh = regsp->ur_ioh; 2236 uint32_t usr2; 2237 2238 if (!READAHEAD_IS_FULL() && 2239 ((usr2 = bus_space_read_4(iot, ioh, IMX_USR2)) & IMX_USR2_RDR)) { 2240 2241 int cn_trapped = 0; 2242 cin = bus_space_read_4(iot, ioh, IMX_URXD); 2243 cn_check_magic(dev, cin & 0xff, imxuart_cnm_state); 2244 imxuart_readahead_in = (imxuart_readahead_in + 1) & 2245 (READAHEAD_RING_LEN-1); 2246 } 2247 2248 /* wait for any pending transmission to finish */ 2249 timo = 150000; 2250 do { 2251 if (bus_space_read_4(iot, ioh, IMX_USR1) & IMX_USR1_TRDY) { 2252 bus_space_write_4(iot, ioh, IMX_UTXD, c); 2253 break; 2254 } 2255 } while(--timo > 0); 2256 2257 IMXUART_BARRIER(regsp, BR | BW); 2258 2259 splx(s); 2260 } 2261 2262 /* 2263 * Initialize UART for use as console or KGDB line. 2264 */ 2265 int 2266 imxuart_init(struct imxuart_regs *regsp, int rate, tcflag_t cflag) 2267 { 2268 struct imxuart_baudrate_ratio ratio; 2269 int rfdiv = IMX_UFCR_DIVIDER_TO_RFDIV(imxuart_freqdiv); 2270 uint32_t ufcr; 2271 2272 if (bus_space_map(regsp->ur_iot, regsp->ur_iobase, IMX_UART_SIZE, 0, 2273 ®sp->ur_ioh)) 2274 return ENOMEM; /* ??? */ 2275 2276 if (imxuspeed(rate, &ratio) < 0) 2277 return EINVAL; 2278 2279 /* UBIR must updated before UBMR */ 2280 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, 2281 IMX_UBIR, ratio.numerator); 2282 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, 2283 IMX_UBMR, ratio.modulator); 2284 2285 2286 /* XXX: DTREN, DPEC */ 2287 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR3, 2288 IMX_UCR3_DSR|IMX_UCR3_RXDMUXSEL); 2289 2290 ufcr = (8 << IMX_UFCR_TXTL_SHIFT) | (rfdiv << IMX_UFCR_RFDIV_SHIFT) | 2291 (1 << IMX_UFCR_RXTL_SHIFT); 2292 /* XXX: keep DCE/DTE bit */ 2293 ufcr |= bus_space_read_4(regsp->ur_iot, regsp->ur_ioh, IMX_UFCR) & 2294 IMX_UFCR_DCEDTE; 2295 2296 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UFCR, ufcr); 2297 2298 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_ONEMS, 2299 imxuart_freq / imxuart_freqdiv / 1000); 2300 2301 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR2, 2302 IMX_UCR2_IRTS| 2303 IMX_UCR2_CTSC| 2304 IMX_UCR2_WS|IMX_UCR2_TXEN| 2305 IMX_UCR2_RXEN|IMX_UCR2_SRST); 2306 /* clear status registers */ 2307 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_USR1, 0xffff); 2308 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_USR2, 0xffff); 2309 2310 2311 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR1, 2312 IMX_UCR1_UARTEN); 2313 2314 return (0); 2315 } 2316 2317 2318 #endif 2319 2320 2321 #ifdef IMXUARTCONSOLE 2322 /* 2323 * Following are all routines needed for UART to act as console 2324 */ 2325 struct consdev imxucons = { 2326 NULL, NULL, imxucngetc, imxucnputc, imxucnpollc, NULL, NULL, NULL, 2327 NODEV, CN_NORMAL 2328 }; 2329 2330 2331 int 2332 imxuart_cons_attach(bus_space_tag_t iot, paddr_t iobase, u_int rate, 2333 tcflag_t cflag) 2334 { 2335 struct imxuart_regs regs; 2336 int res; 2337 2338 regs.ur_iot = iot; 2339 regs.ur_iobase = iobase; 2340 2341 res = imxuart_init(®s, rate, cflag); 2342 if (res) 2343 return (res); 2344 2345 cn_tab = &imxucons; 2346 cn_init_magic(&imxuart_cnm_state); 2347 cn_set_magic("\047\001"); /* default magic is BREAK */ 2348 2349 imxuconsrate = rate; 2350 imxuconscflag = cflag; 2351 2352 imxuconsregs = regs; 2353 2354 return 0; 2355 } 2356 2357 int 2358 imxucngetc(dev_t dev) 2359 { 2360 return (imxuart_common_getc(dev, &imxuconsregs)); 2361 } 2362 2363 /* 2364 * Console kernel output character routine. 2365 */ 2366 void 2367 imxucnputc(dev_t dev, int c) 2368 { 2369 imxuart_common_putc(dev, &imxuconsregs, c); 2370 } 2371 2372 void 2373 imxucnpollc(dev_t dev, int on) 2374 { 2375 2376 } 2377 2378 #endif /* IMXUARTCONSOLE */ 2379 2380 #ifdef KGDB 2381 int 2382 imxuart_kgdb_attach(bus_space_tag_t iot, paddr_t iobase, u_int rate, 2383 tcflag_t cflag) 2384 { 2385 int res; 2386 2387 if (iot == imxuconsregs.ur_iot && 2388 iobase == imxuconsregs.ur_iobase) { 2389 #if !defined(DDB) 2390 return (EBUSY); /* cannot share with console */ 2391 #else 2392 imxu_kgdb_regs.ur_iot = iot; 2393 imxu_kgdb_regs.ur_ioh = imxuconsregs.ur_ioh; 2394 imxu_kgdb_regs.ur_iobase = iobase; 2395 #endif 2396 } else { 2397 imxu_kgdb_regs.ur_iot = iot; 2398 imxu_kgdb_regs.ur_iobase = iobase; 2399 2400 res = imxuart_init(&imxu_kgdb_regs, rate, cflag); 2401 if (res) 2402 return (res); 2403 2404 /* 2405 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2406 * expects this to be initialized 2407 */ 2408 cn_init_magic(&imxuart_cnm_state); 2409 cn_set_magic("\047\001"); 2410 } 2411 2412 kgdb_attach(imxuart_kgdb_getc, imxuart_kgdb_putc, &imxu_kgdb_regs); 2413 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2414 2415 return (0); 2416 } 2417 2418 /* ARGSUSED */ 2419 int 2420 imxuart_kgdb_getc(void *arg) 2421 { 2422 struct imxuart_regs *regs = arg; 2423 2424 return (imxuart_common_getc(NODEV, regs)); 2425 } 2426 2427 /* ARGSUSED */ 2428 void 2429 imxuart_kgdb_putc(void *arg, int c) 2430 { 2431 struct imxuart_regs *regs = arg; 2432 2433 imxuart_common_putc(NODEV, regs, c); 2434 } 2435 #endif /* KGDB */ 2436 2437 /* helper function to identify the imxu ports used by 2438 console or KGDB (and not yet autoconf attached) */ 2439 int 2440 imxuart_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2441 { 2442 bus_space_handle_t help; 2443 2444 if (!imxuconsattached && 2445 iot == imxuconsregs.ur_iot && iobase == imxuconsregs.ur_iobase) 2446 help = imxuconsregs.ur_ioh; 2447 #ifdef KGDB 2448 else if (!imxu_kgdb_attached && 2449 iot == imxu_kgdb_regs.ur_iot && iobase == imxu_kgdb_regs.ur_iobase) 2450 help = imxu_kgdb_regs.ur_ioh; 2451 #endif 2452 else 2453 return (0); 2454 2455 if (ioh) 2456 *ioh = help; 2457 return (1); 2458 } 2459 2460 #ifdef notyet 2461 2462 bool 2463 imxuart_cleanup(device_t self, int how) 2464 { 2465 /* 2466 * this routine exists to serve as a shutdown hook for systems that 2467 * have firmware which doesn't interact properly with a imxuart device in 2468 * FIFO mode. 2469 */ 2470 struct imxuart_softc *sc = device_private(self); 2471 2472 if (ISSET(sc->sc_hwflags, IMXUART_HW_FIFO)) 2473 UR_WRITE_1(&sc->sc_regs, IMXUART_REG_FIFO, 0); 2474 2475 return true; 2476 } 2477 #endif 2478 2479 #ifdef notyet 2480 bool 2481 imxuart_suspend(device_t self PMF_FN_ARGS) 2482 { 2483 struct imxuart_softc *sc = device_private(self); 2484 2485 UR_WRITE_1(&sc->sc_regs, IMXUART_REG_IER, 0); 2486 (void)CSR_READ_1(&sc->sc_regs, IMXUART_REG_IIR); 2487 2488 return true; 2489 } 2490 #endif 2491 2492 #ifdef notyet 2493 bool 2494 imxuart_resume(device_t self PMF_FN_ARGS) 2495 { 2496 struct imxuart_softc *sc = device_private(self); 2497 2498 mutex_spin_enter(&sc->sc_lock); 2499 imxuart_loadchannelregs(sc); 2500 mutex_spin_exit(&sc->sc_lock); 2501 2502 return true; 2503 } 2504 #endif 2505 2506 static void 2507 imxuart_enable_debugport(struct imxuart_softc *sc) 2508 { 2509 bus_space_tag_t iot = sc->sc_regs.ur_iot; 2510 bus_space_handle_t ioh = sc->sc_regs.ur_ioh; 2511 2512 if (sc->sc_hwflags & (IMXUART_HW_CONSOLE|IMXUART_HW_KGDB)) { 2513 2514 /* Turn on line break interrupt, set carrier. */ 2515 2516 sc->sc_ucr3 |= IMX_UCR3_DSR; 2517 bus_space_write_4(iot, ioh, IMX_UCR3, sc->sc_ucr3); 2518 2519 sc->sc_ucr4 |= IMX_UCR4_BKEN; 2520 bus_space_write_4(iot, ioh, IMX_UCR4, sc->sc_ucr4); 2521 2522 sc->sc_ucr2 |= IMX_UCR2_TXEN|IMX_UCR2_RXEN| 2523 IMX_UCR2_CTS; 2524 bus_space_write_4(iot, ioh, IMX_UCR2, sc->sc_ucr2); 2525 2526 sc->sc_ucr1 |= IMX_UCR1_UARTEN; 2527 bus_space_write_4(iot, ioh, IMX_UCR1, sc->sc_ucr1); 2528 } 2529 } 2530 2531 2532 void 2533 imxuart_set_frequency(u_int freq, u_int div) 2534 { 2535 imxuart_freq = freq; 2536 imxuart_freqdiv = div; 2537 } 2538
Indexes created Tue Sep 30 20:09:53 GMT 2025