imxuartreg.h revision 1.1.2.1
1 /* $Id: imxuartreg.h,v 1.1.2.1 2007/09/11 02:32:30 matt Exp $ */ 2 /* 3 * register definitions for Freescale i.MX31 and i.MX31L UARTs 4 * 5 * UART specification obtained from: 6 * MCIMX31 and MCIMX31L Application Processors 7 * Reference Manual 8 * MCIMC31RM 9 * Rev. 2.3 10 * 1/2007 11 */ 12 13 14 /* 15 * Registers are 32 bits wide; the 16 MSBs are unused -- 16 * they read as zeros and are ignored on write. 17 */ 18 #define BITS(hi,lo) ((uint32_t)(~((~0ULL)<<((hi)+1)))&((~0)<<(lo))) 19 #define BIT(n) ((uint32_t)(1 << (n))) 20 21 /* 22 * register base addrs 23 */ 24 #define IMX_UART1_BASE 0x43f90000 25 #define IMX_UART2_BASE 0x43f94000 26 #define IMX_UART3_BASE 0x5000C000 27 #define IMX_UART4_BASE 0x43fb0000 28 #define IMX_UART5_BASE 0x43fb4000 29 30 /* 31 * register offsets 32 */ 33 #define IMX_URXD 0x00 /* r */ /* UART Receiver Reg */ 34 #define IMX_UTXD 0x40 /* w */ /* UART Transmitter Reg */ 35 #define IMX_UCR1 0x80 /* rw */ /* UART Control Reg 1 */ 36 #define IMX_UCR2 0x84 /* rw */ /* UART Control Reg 2 */ 37 #define IMX_UCR3 0x88 /* rw */ /* UART Control Reg 3 */ 38 #define IMX_UCR4 0x8c /* rw */ /* UART Control Reg 4 */ 39 #define IMX_UCRn(n) (IMX_UCR1 + ((n) << 2)) 40 #define IMX_UFCR 0x90 /* rw */ /* UART FIFO Control Reg */ 41 #define IMX_USR1 0x94 /* rw */ /* UART Status Reg 1 */ 42 #define IMX_USR2 0x98 /* rw */ /* UART Status Reg 2 */ 43 #define IMX_USRn(n) (IMX_USR1 + ((n) << 2)) 44 #define IMX_UESC 0x9c /* rw */ /* UART Escape Character Reg */ 45 #define IMX_UTIM 0xa0 /* rw */ /* UART Escape Timer Reg */ 46 #define IMX_UBIR 0xa4 /* rw */ /* UART BRM Incremental Reg */ 47 #define IMX_UBMR 0xa8 /* rw */ /* UART BRM Modulator Reg */ 48 #define IMX_UBRC 0xac /* r */ /* UART Baud Rate Count Reg */ 49 #define IMX_ONEMS 0xb0 /* rw */ /* UART One Millisecond Reg */ 50 #define IMX_UTS 0xb4 /* rw */ /* UART Test Reg */ 51 52 /* 53 * bit attributes: 54 * ro read-only 55 * wo write-only 56 * rw read/write 57 * w1c write 1 to clear 58 * 59 * attrs defined but apparently unused for the UART: 60 * rwm rw bit that can be modified by HW (other than reset) 61 * scb self-clear: write 1 has some effect, always reads as 0 62 */ 63 64 /* 65 * IMX_URXD bits 66 */ 67 #define IMX_URXD_RX_DATA BITS(7,0) /* ro */ 68 #define IMX_URXD_RESV BITS(9,8) /* ro */ 69 #define IMX_URXD_PRERR BIT(10) /* ro */ 70 #define IMX_URXD_BRK BIT(11) /* ro */ 71 #define IMX_URXD_FRMERR BIT(12) /* ro */ 72 #define IMX_URXD_OVRRUN BIT(13) /* ro */ 73 #define IMX_URXD_ERR BIT(14) /* ro */ 74 #define IMX_URXD_CHARDY BIT(15) /* ro */ 75 76 /* 77 * IMX_UTXD bits 78 */ 79 #define IMX_UTXD_TX_DATA BITS(7,0) /* wo */ 80 #define IMX_UTXD_RESV BITS(15,8) 81 82 /* 83 * IMX_UCR1 bits 84 */ 85 #define IMX_UCR1_UARTEN BIT(0) /* rw */ 86 #define IMX_UCR1_DOZE BIT(1) /* rw */ 87 #define IMX_UCR1_ATDMAEN BIT(2) /* rw */ 88 #define IMX_UCR1_TXDMAEN BIT(3) /* rw */ 89 #define IMX_UCR1_SNDBRK BIT(4) /* rw */ 90 #define IMX_UCR1_RTSDEN BIT(5) /* rw */ 91 #define IMX_UCR1_TXMPTYEN BIT(6) /* rw */ 92 #define IMX_UCR1_IREN BIT(7) /* rw */ 93 #define IMX_UCR1_RXDMAEN BIT(8) /* rw */ 94 #define IMX_UCR1_RRDYEN BIT(9) /* rw */ 95 #define IMX_UCR1_ICD BITS(11,10) /* rw */ 96 #define IMX_UCR1_IDEN BIT(12) /* rw */ 97 #define IMX_UCR1_TRDYEN BIT(13) /* rw */ 98 #define IMX_UCR1_ADBR BIT(14) /* rw */ 99 #define IMX_UCR1_ADEN BIT(15) /* rw */ 100 101 /* 102 * IMX_UCR2 bits 103 */ 104 #define IMX_UCR2_SRST BIT(0) /* rw */ 105 #define IMX_UCR2_RXEN BIT(1) /* rw */ 106 #define IMX_UCR2_TXEN BIT(2) /* rw */ 107 #define IMX_UCR2_ATEN BIT(3) /* rw */ 108 #define IMX_UCR2_RTSEN BIT(4) /* rw */ 109 #define IMX_UCR2_WS BIT(5) /* rw */ 110 #define IMX_UCR2_STPB BIT(6) /* rw */ 111 #define IMX_UCR2_PRDE BIT(7) /* rw */ 112 #define IMX_UCR2_PREN BIT(8) /* rw */ 113 #define IMX_UCR2_RTEC BITS(10,9) /* rw */ 114 #define IMX_UCR2_ESCEN BIT(11) /* rw */ 115 #define IMX_UCR2_CTS BIT(12) /* rw */ 116 #define IMX_UCR2_CTSC BIT(13) /* rw */ 117 #define IMX_UCR2_IRTS BIT(14) /* rw */ 118 #define IMX_UCR2_ESCI BIT(15) /* rw */ 119 120 /* 121 * IMX_UCR3 bits 122 */ 123 #define IMX_UCR3_ACIEN BIT(0) /* rw */ 124 #define IMX_UCR3_INVT BIT(1) /* rw */ 125 #define IMX_UCR3_RXDMUXSEL BIT(2) /* rw */ 126 #define IMX_UCR3_DTRDEN BIT(3) /* rw */ 127 #define IMX_UCR3_AWAKEN BIT(4) /* rw */ 128 #define IMX_UCR3_AIRINTEN BIT(5) /* rw */ 129 #define IMX_UCR3_RXDSEN BIT(6) /* rw */ 130 #define IMX_UCR3_ADNIMP BIT(7) /* rw */ 131 #define IMX_UCR3_RI BIT(8) /* rw */ 132 #define IMX_UCR3_DCD BIT(9) /* rw */ 133 #define IMX_UCR3_DSR BIT(10) /* rw */ 134 #define IMX_UCR3_FRAERREN BIT(11) /* rw */ 135 #define IMX_UCR3_PARERREN BIT(12) /* rw */ 136 #define IMX_UCR3_DTREN BIT(13) /* rw */ 137 #define IMX_UCR3_DPEC BITS(15,14) /* rw */ 138 139 /* 140 * IMX_UCR4 bits 141 */ 142 #define IMX_UCR4_DREN BIT(0) /* rw */ 143 #define IMX_UCR4_OREN BIT(1) /* rw */ 144 #define IMX_UCR4_BKEN BIT(2) /* rw */ 145 #define IMX_UCR4_TCEN BIT(3) /* rw */ 146 #define IMX_UCR4_LPBYP BIT(4) /* rw */ 147 #define IMX_UCR4_IRSC BIT(5) /* rw */ 148 #define IMX_UCR4_IDDMAEN BIT(6) /* rw */ 149 #define IMX_UCR4_WKEN BIT(7) /* rw */ 150 #define IMX_UCR4_ENIRI BIT(8) /* rw */ 151 #define IMX_UCR4_INVR BIT(9) /* rw */ 152 #define IMX_UCR4_CTSTL BITS(15,10) /* rw */ 153 154 /* 155 * IMX_UFCR bits 156 */ 157 #define IMX_UFCR_RXTL BITS(5,0) /* rw */ 158 #define IMX_UFCR_DCEDTE BIT(6) /* rw */ 159 #define IMX_UFCR_RFDIV BITS(9,7) /* rw */ 160 #define IMX_UFCR_TXTL BITS(15,8) /* rw */ 161 162 /* 163 * IMX_USR1 bits 164 */ 165 #define IMX_USR1_RESV BITS(3,0) 166 #define IMX_USR1_AWAKE BIT(4) /* w1c */ 167 #define IMX_USR1_AIRINT BIT(5) /* w1c */ 168 #define IMX_USR1_RXDS BIT(6) /* ro */ 169 #define IMX_USR1_DTRD BIT(7) /* w1c */ 170 #define IMX_USR1_AGTIM BIT(8) /* w1c */ 171 #define IMX_USR1_RRDY BIT(9) /* ro */ 172 #define IMX_USR1_FRAMERR BIT(10) /* w1c */ 173 #define IMX_USR1_ESCF BIT(11) /* w1c */ 174 #define IMX_USR1_RTSD BIT(12) /* w1c */ 175 #define IMX_USR1_TRDY BIT(13) /* ro */ 176 #define IMX_USR1_RTSS BIT(14) /* ro */ 177 #define IMX_USR1_PARITYERR BIT(15) /* w1c */ 178 179 /* 180 * IMX_USR2 bits 181 */ 182 #define IMX_USR2_RDR BIT(0) 183 #define IMX_USR2_ORE BIT(1) /* w1c */ 184 #define IMX_USR2_BRCD BIT(2) /* w1c */ 185 #define IMX_USR2_TXDC BIT(3) /* ro */ 186 #define IMX_USR2_RTSF BIT(4) /* w1c */ 187 #define IMX_USR2_DCDIN BIT(5) /* ro */ 188 #define IMX_USR2_DCDDELT BIT(6) /* rw */ 189 #define IMX_USR2_WAKE BIT(7) /* w1c */ 190 #define IMX_USR2_IRINT BIT(8) /* rw */ 191 #define IMX_USR2_RIIN BIT(9) /* ro */ 192 #define IMX_USR2_RIDELT BIT(10) /* w1c */ 193 #define IMX_USR2_ACST BIT(11) /* rw */ 194 #define IMX_USR2_IDLE BIT(12) /* w1c */ 195 #define IMX_USR2_DTRF BIT(13) /* rw */ 196 #define IMX_USR2_TXFE BIT(14) /* ro */ 197 #define IMX_USR2_ADET BIT(15) /* w1c */ 198 199 /* 200 * IMX_UESC bits 201 */ 202 #define IMX_UESC_ESC_CHAR BITS(7,0) /* rw */ 203 #define IMX_UESC_RESV BITS(15,8) 204 205 /* 206 * IMX_UTIM bits 207 */ 208 #define IMX_UTIM_TIM BITS(11,0) /* rw */ 209 #define IMX_UTIM_RESV BITS(15,12) 210 211 /* 212 * IMX_UBIR bits 213 */ 214 #define IMX_UBIR_INC BITS(15,0) /* rw */ 215 216 /* 217 * IMX_UBMR bits 218 */ 219 #define IMX_UBMR_MOD BITS(15,0) /* rw */ 220 221 /* 222 * IMX_UBRC bits 223 */ 224 #define IMX_UBRC_BCNT BITS(15,0) /* ro */ 225 226 /* 227 * IMX_ONEMS bits 228 */ 229 #define IMX_ONEMS_ONEMS BITS(15,0) /* rw */ 230 231 /* 232 * IMX_UTS bits 233 */ 234 #define IMX_UTS_SOFTRST BIT(0) /* rw */ 235 #define IMX_UTS_RESVa BITS(2,1) 236 #define IMX_UTS_RXFULL BIT(3) /* rw */ 237 #define IMX_UTS_TXFUL BIT(4) /* rw */ 238 #define IMX_UTS_RXEMPTY BIT(5) /* rw */ 239 #define IMX_UTS_TXEMPTY BIT(5) /* rw */ 240 #define IMX_UTS_RESVb BITS(8,7) 241 #define IMX_UTS_RXDBG BIT(9) /* rw */ 242 #define IMX_UTS_LOOPIR BIT(10) /* rw */ 243 #define IMX_UTS_DBGEN BIT(11) /* rw */ 244 #define IMX_UTS_LOOP BIT(12) /* rw */ 245 #define IMX_UTS_FRCPERR BIT(13) /* rw */ 246 #define IMX_UTS_RESVc BITS(15,14) 247 #define IMX_UTS_RESV (IMX_UTS_RESVa|IMX_UTS_RESVb|IMX_UTS_RESVc) 248 249 /* 250 * interrupt specs 251 * see Table 31-25. "Interrupts an DMA" 252 */ 253 254 /* 255 * abstract interrupts spec indexing 256 */ 257 typedef enum { 258 RX_RRDY=0, 259 RX_ID, 260 RX_DR, 261 RX_RXDS, 262 RX_AT, 263 TX_TXMPTY, 264 TX_TRDY, 265 TX_TC, 266 MINT_OR, 267 MINT_BR, 268 MINT_WK, 269 MINT_AD, 270 MINT_ACI, 271 MINT_ESCI, 272 MINT_IRI, 273 MINT_AIRINT, 274 MINT_AWAK, 275 MINT_FRAERR, 276 MINT_PARERR, 277 MINT_RTSD, 278 MINT_RTS, 279 MINT_DCE_DTR, 280 MINT_DTE_RI, 281 MINT_DTE_DCE, 282 MINT_DTRD, 283 RX_DMAREQ_RXDMA, 284 RX_DMAREQ_ATDMA, 285 RX_DMAREQ_IDDMA, 286 RX_DMAREQ_TXDMA, 287 } imxuart_intrix_t; 288 289 /* 290 * abstract interrupts spec 291 */ 292 typedef struct { 293 const uint32_t enb_bit; 294 const uint enb_reg; 295 const uint32_t flg_bit; 296 const uint flg_reg; 297 const char * name; /* for debug */ 298 } imxuart_intrspec_t; 299 300 #define IMXUART_INTRSPEC(cv, cr, sv, sr) \ 301 { IMX_UCR##cr##_##cv, ((cr) - 1), IMX_USR##sr##_##sv, ((sr) - 1), #sv } 302 303 static const imxuart_intrspec_t imxuart_intrspec_tab[] = { 304 /* ipi_uart_rx */ 305 IMXUART_INTRSPEC(RRDYEN, 1, RRDY, 1), 306 IMXUART_INTRSPEC(IDEN, 1, IDLE, 2), 307 IMXUART_INTRSPEC(DREN, 4, RDR, 2), 308 IMXUART_INTRSPEC(RXDSEN, 3, RXDS, 1), 309 IMXUART_INTRSPEC(ATEN, 2, AGTIM, 1), 310 /* ipi_uart_tx */ 311 IMXUART_INTRSPEC(TXMPTYEN, 1, TXFE, 2), 312 IMXUART_INTRSPEC(TRDYEN, 1, TRDY, 1), 313 IMXUART_INTRSPEC(TCEN, 4, TXDC, 2), 314 /* ipi_uart_mint */ 315 IMXUART_INTRSPEC(OREN, 4, ORE, 2), 316 IMXUART_INTRSPEC(BKEN, 4, BRCD, 2), 317 IMXUART_INTRSPEC(WKEN, 4, WAKE, 2), 318 IMXUART_INTRSPEC(ADEN, 1, ADET, 2), 319 IMXUART_INTRSPEC(ACIEN, 3, ACST, 2), 320 IMXUART_INTRSPEC(ESCI, 2, ESCF, 1), 321 IMXUART_INTRSPEC(ENIRI, 4, IRINT, 2), 322 IMXUART_INTRSPEC(AIRINTEN, 3, AIRINT, 1), 323 IMXUART_INTRSPEC(AWAKEN, 3, AWAKE, 1), 324 IMXUART_INTRSPEC(FRAERREN, 3, FRAMERR, 1), 325 IMXUART_INTRSPEC(PARERREN, 3, PARITYERR, 1), 326 IMXUART_INTRSPEC(RTSDEN, 1, RTSD, 1), 327 IMXUART_INTRSPEC(RTSEN, 2, RTSF, 2), 328 IMXUART_INTRSPEC(DTREN, 3, DTRF, 2), 329 IMXUART_INTRSPEC(RI, 3, DTRF, 2), 330 IMXUART_INTRSPEC(DCD, 3, DCDDELT, 2), 331 IMXUART_INTRSPEC(DTRDEN, 3, DTRD, 1), 332 /* ipd_uart_rx_dmareq */ 333 IMXUART_INTRSPEC(RXDMAEN, 1, RRDY, 1), 334 IMXUART_INTRSPEC(ATDMAEN, 1, AGTIM, 1), 335 IMXUART_INTRSPEC(IDDMAEN, 4, IDLE, 2), 336 /* ipd_uart_tx_dmareq */ 337 IMXUART_INTRSPEC(TXDMAEN, 1, TRDY, 1), 338 }; 339 #define IMXUART_INTRSPEC_TAB_SZ \ 340 (sizeof(imxuart_intrspec_tab) / sizeof(imxuart_intrspec_tab[0])) 341 342 /* 343 * functional groupings of intr status flags by reg 344 */ 345 #define IMXUART_RXINTR_USR1 (IMX_USR1_RRDY|IMX_USR1_RXDS|IMX_USR1_AGTIM) 346 #define IMXUART_RXINTR_USR2 (IMX_USR2_IDLE|IMX_USR2_RDR) 347 #define IMXUART_TXINTR_USR1 (IMX_USR1_TRDY) 348 #define IMXUART_TXINTR_USR2 (IMX_USR2_TXFE|IMX_USR2_TXDC) 349 #define IMXUART_MINT_USR1 (IMX_USR1_ESCF|IMX_USR1_AIRINT||IMX_USR1_AWAKE \ 350 |IMX_USR1_FRAMERR|IMX_USR1_PARITYERR \ 351 |IMX_USR1_RTSD|IMX_USR1_DTRD) 352 #define IMXUART_MINT_USR2 (IMX_USR2_ORE|IMX_USR2_BRCD|IMX_USR2_WAKE \ 353 |IMX_USR2_ADET|IMX_USR2_ACST|IMX_USR2_IRINT \ 354 |IMX_USR2_RTSF|IMX_USR2_DTRF|IMX_USR2_DTRF \ 355 |IMX_USR2_DCDDELT) 356 #define IMXUART_RXDMA_USR1 (IMX_USR1_RRDY|IMX_USR1_AGTIM) 357 #define IMXUART_RXDMA_USR2 (IMX_USR2_IDLE) 358 #define IMXUART_TXDMA_USR1 (IMX_USR1_TRDY) 359 #define IMXUART_TXDMA_USR2 (0) 360 361 /* 362 * all intr status flags by reg 363 */ 364 #define IMXUART_INTRS_USR1 (IMXUART_RXINTR_USR1|IMXUART_TXINTR_USR1 \ 365 |IMXUART_MINT_USR1|IMXUART_RXDMA_USR1 \ 366 |IMXUART_TXDMA_USR1) 367 #define IMXUART_INTRS_USR2 (IMXUART_RXINTR_USR2|IMXUART_TXINTR_USR2 \ 368 |IMXUART_MINT_USR2|IMXUART_RXDMA_USR2 \ 369 |IMXUART_TXDMA_USR2) 370 371 /* 372 * all intr controls by reg 373 */ 374 #define IMXUART_INTRS_UCR1 (IMX_UCR1_RRDYEN|IMX_UCR1_IDEN \ 375 |IMX_UCR1_TXMPTYEN|IMX_UCR1_TRDYEN \ 376 |IMX_UCR1_ADEN|IMX_UCR1_RTSDEN \ 377 |IMX_UCR1_RXDMAEN|IMX_UCR1_RXDMAEN \ 378 |IMX_UCR1_ATDMAEN|IMX_UCR1_TXDMAEN) 379 #define IMXUART_INTRS_UCR2 (IMX_UCR2_ATEN|IMX_UCR2_ESCI|IMX_UCR2_RTSEN) 380 #define IMXUART_INTRS_UCR3 (IMX_UCR3_RXDSEN|IMX_UCR3_ACIEN \ 381 |IMX_UCR3_AIRINTEN|IMX_UCR3_AWAKEN \ 382 |IMX_UCR3_FRAERREN|IMX_UCR3_PARERREN \ 383 |IMX_UCR3_DTREN|IMX_UCR3_RI \ 384 |IMX_UCR3_DCD|IMX_UCR3_DTRDEN) 385 #define IMXUART_INTRS_UCR4 (IMX_UCR4_DREN|IMX_UCR4_TCEN|IMX_UCR4_OREN \ 386 |IMX_UCR4_BKEN|IMX_UCR4_WKEN \ 387 |IMX_UCR4_ENIRI|IMX_UCR4_IDDMAEN) 388 389 390
Indexes created Thu Oct 02 10:09:58 GMT 2025