imxuartreg.h revision 1.4
1 /* $NetBSD: imxuartreg.h,v 1.4 2010/11/13 06:12:17 bsh Exp $ */ 2 /* 3 * register definitions for Freescale i.MX31 and i.MX31L UARTs 4 * 5 * UART specification obtained from: 6 * MCIMX31 and MCIMX31L Application Processors 7 * Reference Manual 8 * MCIMC31RM 9 * Rev. 2.3 10 * 1/2007 11 * 12 * MCIMC51 Multimedia Application Processor 13 * Reference Manual 14 * MCMIMX51RM 15 * Rev.1 16 * 2/2010 17 */ 18 #ifndef _IMXUARTREG_H 19 #define _IMXUARTREG_H 20 21 #ifdef __ASSEMBLER__ 22 #define __BIT(n) (1<<(n)) 23 #define __BITS(hi,lo) ((~((~0)<<((hi)+1)))&((~0)<<(lo))) 24 #else 25 #include <sys/cdefs.h> 26 #endif 27 28 /* 29 * Registers are 32 bits wide; the 16 MSBs are unused -- 30 * they read as zeros and are ignored on write. 31 */ 32 33 34 /* 35 * register offsets 36 */ 37 #define IMX_URXD 0x00 /* r */ /* UART Receiver Reg */ 38 #define IMX_UTXD 0x40 /* w */ /* UART Transmitter Reg */ 39 #define IMX_UCR1 0x80 /* rw */ /* UART Control Reg 1 */ 40 #define IMX_UCR2 0x84 /* rw */ /* UART Control Reg 2 */ 41 #define IMX_UCR3 0x88 /* rw */ /* UART Control Reg 3 */ 42 #define IMX_UCR4 0x8c /* rw */ /* UART Control Reg 4 */ 43 #define IMX_UCRn(n) (IMX_UCR1 + ((n) << 2)) 44 #define IMX_UFCR 0x90 /* rw */ /* UART FIFO Control Reg */ 45 #define IMX_USR1 0x94 /* rw */ /* UART Status Reg 1 */ 46 #define IMX_USR2 0x98 /* rw */ /* UART Status Reg 2 */ 47 #define IMX_USRn(n) (IMX_USR1 + ((n) << 2)) 48 #define IMX_UESC 0x9c /* rw */ /* UART Escape Character Reg */ 49 #define IMX_UTIM 0xa0 /* rw */ /* UART Escape Timer Reg */ 50 #define IMX_UBIR 0xa4 /* rw */ /* UART BRM Incremental Reg */ 51 #define IMX_UBMR 0xa8 /* rw */ /* UART BRM Modulator Reg */ 52 #define IMX_UBRC 0xac /* r */ /* UART Baud Rate Count Reg */ 53 #define IMX_ONEMS 0xb0 /* rw */ /* UART One Millisecond Reg */ 54 #define IMX_UTS 0xb4 /* rw */ /* UART Test Reg */ 55 56 #define IMX_UART_SIZE 0xb8 57 58 /* 59 * bit attributes: 60 * ro read-only 61 * wo write-only 62 * rw read/write 63 * w1c write 1 to clear 64 * 65 * attrs defined but apparently unused for the UART: 66 * rwm rw bit that can be modified by HW (other than reset) 67 * scb self-clear: write 1 has some effect, always reads as 0 68 */ 69 70 /* 71 * IMX_URXD bits 72 */ 73 #define IMX_URXD_RX_DATA __BITS(7,0) /* ro */ 74 #define IMX_URXD_RESV __BITS(9,8) /* ro */ 75 #define IMX_URXD_PRERR __BIT(10) /* ro */ 76 #define IMX_URXD_BRK __BIT(11) /* ro */ 77 #define IMX_URXD_FRMERR __BIT(12) /* ro */ 78 #define IMX_URXD_OVRRUN __BIT(13) /* ro */ 79 #define IMX_URXD_ERR __BIT(14) /* ro */ 80 #define IMX_URXD_CHARDY __BIT(15) /* ro */ 81 82 /* 83 * IMX_UTXD bits 84 */ 85 #define IMX_UTXD_TX_DATA __BITS(7,0) /* wo */ 86 #define IMX_UTXD_RESV __BITS(15,8) 87 88 /* 89 * IMX_UCR1 bits 90 */ 91 #define IMX_UCR1_UARTEN __BIT(0) /* rw */ 92 #define IMX_UCR1_DOZE __BIT(1) /* rw */ 93 #define IMX_UCR1_ATDMAEN __BIT(2) /* rw */ 94 #define IMX_UCR1_TXDMAEN __BIT(3) /* rw */ 95 #define IMX_UCR1_SNDBRK __BIT(4) /* rw */ 96 #define IMX_UCR1_RTSDEN __BIT(5) /* rw */ 97 #define IMX_UCR1_TXMPTYEN __BIT(6) /* rw */ 98 #define IMX_UCR1_IREN __BIT(7) /* rw */ 99 #define IMX_UCR1_RXDMAEN __BIT(8) /* rw */ 100 #define IMX_UCR1_RRDYEN __BIT(9) /* rw */ 101 #define IMX_UCR1_ICD __BITS(11,10) /* rw */ 102 #define IMX_UCR1_IDEN __BIT(12) /* rw */ 103 #define IMX_UCR1_TRDYEN __BIT(13) /* rw */ 104 #define IMX_UCR1_ADBR __BIT(14) /* rw */ 105 #define IMX_UCR1_ADEN __BIT(15) /* rw */ 106 107 /* 108 * IMX_UCR2 bits 109 */ 110 #define IMX_UCR2_SRST __BIT(0) /* rw */ 111 #define IMX_UCR2_RXEN __BIT(1) /* rw */ 112 #define IMX_UCR2_TXEN __BIT(2) /* rw */ 113 #define IMX_UCR2_ATEN __BIT(3) /* rw */ 114 #define IMX_UCR2_RTSEN __BIT(4) /* rw */ 115 #define IMX_UCR2_WS __BIT(5) /* rw */ 116 #define IMX_UCR2_STPB __BIT(6) /* rw */ 117 #define IMX_UCR2_PROE __BIT(7) /* rw */ 118 #define IMX_UCR2_PREN __BIT(8) /* rw */ 119 #define IMX_UCR2_RTEC __BITS(10,9) /* rw */ 120 #define IMX_UCR2_ESCEN __BIT(11) /* rw */ 121 #define IMX_UCR2_CTS __BIT(12) /* rw */ 122 #define IMX_UCR2_CTSC __BIT(13) /* rw */ 123 #define IMX_UCR2_IRTS __BIT(14) /* rw */ 124 #define IMX_UCR2_ESCI __BIT(15) /* rw */ 125 126 /* 127 * IMX_UCR3 bits 128 */ 129 #define IMX_UCR3_ACIEN __BIT(0) /* rw */ 130 #define IMX_UCR3_INVT __BIT(1) /* rw */ 131 #define IMX_UCR3_RXDMUXSEL __BIT(2) /* rw */ 132 #define IMX_UCR3_DTRDEN __BIT(3) /* rw */ 133 #define IMX_UCR3_AWAKEN __BIT(4) /* rw */ 134 #define IMX_UCR3_AIRINTEN __BIT(5) /* rw */ 135 #define IMX_UCR3_RXDSEN __BIT(6) /* rw */ 136 #define IMX_UCR3_ADNIMP __BIT(7) /* rw */ 137 #define IMX_UCR3_RI __BIT(8) /* rw */ 138 #define IMX_UCR3_DCD __BIT(9) /* rw */ 139 #define IMX_UCR3_DSR __BIT(10) /* rw */ 140 #define IMX_UCR3_FRAERREN __BIT(11) /* rw */ 141 #define IMX_UCR3_PARERREN __BIT(12) /* rw */ 142 #define IMX_UCR3_DTREN __BIT(13) /* rw */ 143 #define IMX_UCR3_DPEC __BITS(15,14) /* rw */ 144 145 /* 146 * IMX_UCR4 bits 147 */ 148 #define IMX_UCR4_DREN __BIT(0) /* rw */ 149 #define IMX_UCR4_OREN __BIT(1) /* rw */ 150 #define IMX_UCR4_BKEN __BIT(2) /* rw */ 151 #define IMX_UCR4_TCEN __BIT(3) /* rw */ 152 #define IMX_UCR4_LPBYP __BIT(4) /* rw */ 153 #define IMX_UCR4_IRSC __BIT(5) /* rw */ 154 #define IMX_UCR4_IDDMAEN __BIT(6) /* rw */ 155 #define IMX_UCR4_WKEN __BIT(7) /* rw */ 156 #define IMX_UCR4_ENIRI __BIT(8) /* rw */ 157 #define IMX_UCR4_INVR __BIT(9) /* rw */ 158 #define IMX_UCR4_CTSTL __BITS(15,10) /* rw */ 159 160 /* 161 * IMX_UFCR bits 162 */ 163 #define IMX_UFCR_RXTL_SHIFT 0 164 #define IMX_UFCR_RXTL __BITS(5,IMX_UFCR_RXTL_SHIFT) /* rw */ 165 #define IMX_UFCR_DCEDTE __BIT(6) /* rw */ 166 #define IMX_UFCR_RFDIV_SHIFT 7 167 #define IMX_UFCR_RFDIV __BITS(9,IMX_UFCR_RFDIV_SHIFT) /* rw */ 168 #define IMX_UFCR_TXTL_SHIFT 10 169 #define IMX_UFCR_TXTL __BITS(15,IMX_UFCR_TXTL_SHIFT) /* rw */ 170 171 #define IMX_UFCR_DIVIDER_TO_RFDIV(div) \ 172 (((6 - div) % 7) & 0x7) 173 174 /* 175 * IMX_USR1 bits 176 */ 177 #define IMX_USR1_RESV __BITS(3,0) 178 #define IMX_USR1_AWAKE __BIT(4) /* w1c */ 179 #define IMX_USR1_AIRINT __BIT(5) /* w1c */ 180 #define IMX_USR1_RXDS __BIT(6) /* ro */ 181 #define IMX_USR1_DTRD __BIT(7) /* w1c */ 182 #define IMX_USR1_AGTIM __BIT(8) /* w1c */ 183 #define IMX_USR1_RRDY __BIT(9) /* ro */ 184 #define IMX_USR1_FRAMERR __BIT(10) /* w1c */ 185 #define IMX_USR1_ESCF __BIT(11) /* w1c */ 186 #define IMX_USR1_RTSD __BIT(12) /* w1c */ 187 #define IMX_USR1_TRDY __BIT(13) /* ro */ 188 #define IMX_USR1_RTSS __BIT(14) /* ro */ 189 #define IMX_USR1_PARITYERR __BIT(15) /* w1c */ 190 191 /* 192 * IMX_USR2 bits 193 */ 194 #define IMX_USR2_RDR __BIT(0) 195 #define IMX_USR2_ORE __BIT(1) /* w1c */ 196 #define IMX_USR2_BRCD __BIT(2) /* w1c */ 197 #define IMX_USR2_TXDC __BIT(3) /* ro */ 198 #define IMX_USR2_RTSF __BIT(4) /* w1c */ 199 #define IMX_USR2_DCDIN __BIT(5) /* ro */ 200 #define IMX_USR2_DCDDELT __BIT(6) /* rw */ 201 #define IMX_USR2_WAKE __BIT(7) /* w1c */ 202 #define IMX_USR2_IRINT __BIT(8) /* rw */ 203 #define IMX_USR2_RIIN __BIT(9) /* ro */ 204 #define IMX_USR2_RIDELT __BIT(10) /* w1c */ 205 #define IMX_USR2_ACST __BIT(11) /* rw */ 206 #define IMX_USR2_IDLE __BIT(12) /* w1c */ 207 #define IMX_USR2_DTRF __BIT(13) /* rw */ 208 #define IMX_USR2_TXFE __BIT(14) /* ro */ 209 #define IMX_USR2_ADET __BIT(15) /* w1c */ 210 211 /* 212 * IMX_UESC bits 213 */ 214 #define IMX_UESC_ESC_CHAR __BITS(7,0) /* rw */ 215 #define IMX_UESC_RESV __BITS(15,8) 216 217 /* 218 * IMX_UTIM bits 219 */ 220 #define IMX_UTIM_TIM __BITS(11,0) /* rw */ 221 #define IMX_UTIM_RESV __BITS(15,12) 222 223 /* 224 * IMX_UBIR bits 225 */ 226 #define IMX_UBIR_INC __BITS(15,0) /* rw */ 227 228 /* 229 * IMX_UBMR bits 230 */ 231 #define IMX_UBMR_MOD __BITS(15,0) /* rw */ 232 233 /* 234 * IMX_UBRC bits 235 */ 236 #define IMX_UBRC_BCNT __BITS(15,0) /* ro */ 237 238 /* 239 * IMX_ONEMS bits 240 */ 241 #define IMX_ONEMS_ONEMS __BITS(15,0) /* rw */ 242 243 /* 244 * IMX_UTS bits 245 */ 246 #define IMX_UTS_SOFTRST __BIT(0) /* rw */ 247 #define IMX_UTS_RESVa __BITS(2,1) 248 #define IMX_UTS_RXFULL __BIT(3) /* rw */ 249 #define IMX_UTS_TXFUL __BIT(4) /* rw */ 250 #define IMX_UTS_RXEMPTY __BIT(5) /* rw */ 251 #define IMX_UTS_TXEMPTY __BIT(5) /* rw */ 252 #define IMX_UTS_RESVb __BITS(8,7) 253 #define IMX_UTS_RXDBG __BIT(9) /* rw */ 254 #define IMX_UTS_LOOPIR __BIT(10) /* rw */ 255 #define IMX_UTS_DBGEN __BIT(11) /* rw */ 256 #define IMX_UTS_LOOP __BIT(12) /* rw */ 257 #define IMX_UTS_FRCPERR __BIT(13) /* rw */ 258 #define IMX_UTS_RESVc __BITS(15,14) 259 #define IMX_UTS_RESV (IMX_UTS_RESVa|IMX_UTS_RESVb|IMX_UTS_RESVc) 260 261 #ifndef __ASSEMBLER__ 262 /* 263 * interrupt specs 264 * see Table 31-25. "Interrupts an DMA" 265 */ 266 267 /* 268 * abstract interrupts spec indexing 269 */ 270 typedef enum { 271 RX_RRDY=0, 272 RX_ID, 273 RX_DR, 274 RX_RXDS, 275 RX_AT, 276 TX_TXMPTY, 277 TX_TRDY, 278 TX_TC, 279 MINT_OR, 280 MINT_BR, 281 MINT_WK, 282 MINT_AD, 283 MINT_ACI, 284 MINT_ESCI, 285 MINT_IRI, 286 MINT_AIRINT, 287 MINT_AWAK, 288 MINT_FRAERR, 289 MINT_PARERR, 290 MINT_RTSD, 291 MINT_RTS, 292 MINT_DCE_DTR, 293 MINT_DTE_RI, 294 MINT_DTE_DCE, 295 MINT_DTRD, 296 RX_DMAREQ_RXDMA, 297 RX_DMAREQ_ATDMA, 298 RX_DMAREQ_IDDMA, 299 RX_DMAREQ_TXDMA, 300 } imxuart_intrix_t; 301 302 /* 303 * abstract interrupts spec 304 */ 305 typedef struct { 306 const uint32_t enb_bit; 307 const uint enb_reg; 308 const uint32_t flg_bit; 309 const uint flg_reg; 310 const char * name; /* for debug */ 311 } imxuart_intrspec_t; 312 313 #define IMXUART_INTRSPEC(cv, cr, sv, sr) \ 314 { IMX_UCR##cr##_##cv, ((cr) - 1), IMX_USR##sr##_##sv, ((sr) - 1), #sv } 315 316 static const imxuart_intrspec_t imxuart_intrspec_tab[] = { 317 /* ipi_uart_rx */ 318 IMXUART_INTRSPEC(RRDYEN, 1, RRDY, 1), 319 IMXUART_INTRSPEC(IDEN, 1, IDLE, 2), 320 IMXUART_INTRSPEC(DREN, 4, RDR, 2), 321 IMXUART_INTRSPEC(RXDSEN, 3, RXDS, 1), 322 IMXUART_INTRSPEC(ATEN, 2, AGTIM, 1), 323 /* ipi_uart_tx */ 324 IMXUART_INTRSPEC(TXMPTYEN, 1, TXFE, 2), 325 IMXUART_INTRSPEC(TRDYEN, 1, TRDY, 1), 326 IMXUART_INTRSPEC(TCEN, 4, TXDC, 2), 327 /* ipi_uart_mint */ 328 IMXUART_INTRSPEC(OREN, 4, ORE, 2), 329 IMXUART_INTRSPEC(BKEN, 4, BRCD, 2), 330 IMXUART_INTRSPEC(WKEN, 4, WAKE, 2), 331 IMXUART_INTRSPEC(ADEN, 1, ADET, 2), 332 IMXUART_INTRSPEC(ACIEN, 3, ACST, 2), 333 IMXUART_INTRSPEC(ESCI, 2, ESCF, 1), 334 IMXUART_INTRSPEC(ENIRI, 4, IRINT, 2), 335 IMXUART_INTRSPEC(AIRINTEN, 3, AIRINT, 1), 336 IMXUART_INTRSPEC(AWAKEN, 3, AWAKE, 1), 337 IMXUART_INTRSPEC(FRAERREN, 3, FRAMERR, 1), 338 IMXUART_INTRSPEC(PARERREN, 3, PARITYERR, 1), 339 IMXUART_INTRSPEC(RTSDEN, 1, RTSD, 1), 340 IMXUART_INTRSPEC(RTSEN, 2, RTSF, 2), 341 IMXUART_INTRSPEC(DTREN, 3, DTRF, 2), 342 IMXUART_INTRSPEC(RI, 3, DTRF, 2), 343 IMXUART_INTRSPEC(DCD, 3, DCDDELT, 2), 344 IMXUART_INTRSPEC(DTRDEN, 3, DTRD, 1), 345 /* ipd_uart_rx_dmareq */ 346 IMXUART_INTRSPEC(RXDMAEN, 1, RRDY, 1), 347 IMXUART_INTRSPEC(ATDMAEN, 1, AGTIM, 1), 348 IMXUART_INTRSPEC(IDDMAEN, 4, IDLE, 2), 349 /* ipd_uart_tx_dmareq */ 350 IMXUART_INTRSPEC(TXDMAEN, 1, TRDY, 1), 351 }; 352 #define IMXUART_INTRSPEC_TAB_SZ \ 353 (sizeof(imxuart_intrspec_tab) / sizeof(imxuart_intrspec_tab[0])) 354 355 #endif /* __ASSEMBLER__ */ 356 357 /* 358 * functional groupings of intr status flags by reg 359 */ 360 #define IMXUART_RXINTR_USR1 (IMX_USR1_RRDY|IMX_USR1_RXDS|IMX_USR1_AGTIM) 361 #define IMXUART_RXINTR_USR2 (IMX_USR2_IDLE|IMX_USR2_RDR) 362 #define IMXUART_TXINTR_USR1 (IMX_USR1_TRDY) 363 #define IMXUART_TXINTR_USR2 (IMX_USR2_TXFE|IMX_USR2_TXDC) 364 #define IMXUART_MINT_USR1 (IMX_USR1_ESCF|IMX_USR1_AIRINT||IMX_USR1_AWAKE \ 365 |IMX_USR1_FRAMERR|IMX_USR1_PARITYERR \ 366 |IMX_USR1_RTSD|IMX_USR1_DTRD) 367 #define IMXUART_MINT_USR2 (IMX_USR2_ORE|IMX_USR2_BRCD|IMX_USR2_WAKE \ 368 |IMX_USR2_ADET|IMX_USR2_ACST|IMX_USR2_IRINT \ 369 |IMX_USR2_RTSF|IMX_USR2_DTRF|IMX_USR2_DTRF \ 370 |IMX_USR2_DCDDELT) 371 #define IMXUART_RXDMA_USR1 (IMX_USR1_RRDY|IMX_USR1_AGTIM) 372 #define IMXUART_RXDMA_USR2 (IMX_USR2_IDLE) 373 #define IMXUART_TXDMA_USR1 (IMX_USR1_TRDY) 374 #define IMXUART_TXDMA_USR2 (0) 375 376 /* 377 * all intr status flags by reg 378 */ 379 #define IMXUART_INTRS_USR1 (IMXUART_RXINTR_USR1|IMXUART_TXINTR_USR1 \ 380 |IMXUART_MINT_USR1|IMXUART_RXDMA_USR1 \ 381 |IMXUART_TXDMA_USR1) 382 #define IMXUART_INTRS_USR2 (IMXUART_RXINTR_USR2|IMXUART_TXINTR_USR2 \ 383 |IMXUART_MINT_USR2|IMXUART_RXDMA_USR2 \ 384 |IMXUART_TXDMA_USR2) 385 386 /* 387 * all intr controls by reg 388 */ 389 #define IMXUART_INTRS_UCR1 (IMX_UCR1_RRDYEN|IMX_UCR1_IDEN \ 390 |IMX_UCR1_TXMPTYEN|IMX_UCR1_TRDYEN \ 391 |IMX_UCR1_ADEN|IMX_UCR1_RTSDEN \ 392 |IMX_UCR1_RXDMAEN|IMX_UCR1_RXDMAEN \ 393 |IMX_UCR1_ATDMAEN|IMX_UCR1_TXDMAEN) 394 #define IMXUART_INTRS_UCR2 (IMX_UCR2_ATEN|IMX_UCR2_ESCI|IMX_UCR2_RTSEN) 395 #define IMXUART_INTRS_UCR3 (IMX_UCR3_RXDSEN|IMX_UCR3_ACIEN \ 396 |IMX_UCR3_AIRINTEN|IMX_UCR3_AWAKEN \ 397 |IMX_UCR3_FRAERREN|IMX_UCR3_PARERREN \ 398 |IMX_UCR3_DTREN|IMX_UCR3_RI \ 399 |IMX_UCR3_DCD|IMX_UCR3_DTRDEN) 400 #define IMXUART_INTRS_UCR4 (IMX_UCR4_DREN|IMX_UCR4_TCEN|IMX_UCR4_OREN \ 401 |IMX_UCR4_BKEN|IMX_UCR4_WKEN \ 402 |IMX_UCR4_ENIRI|IMX_UCR4_IDDMAEN) 403 404 405 #endif /* _IMXUARTREG_H */ 406
Indexes created Thu Sep 25 16:09:42 GMT 2025