imxuartreg.h revision 1.5
1 /* $NetBSD: imxuartreg.h,v 1.5 2012/09/01 14:46:25 matt Exp $ */ 2 /* 3 * register definitions for Freescale i.MX31 and i.MX31L UARTs 4 * 5 * UART specification obtained from: 6 * MCIMX31 and MCIMX31L Application Processors 7 * Reference Manual 8 * MCIMC31RM 9 * Rev. 2.3 10 * 1/2007 11 * 12 * MCIMC51 Multimedia Application Processor 13 * Reference Manual 14 * MCMIMX51RM 15 * Rev.1 16 * 2/2010 17 */ 18 #ifndef _IMXUARTREG_H 19 #define _IMXUARTREG_H 20 21 /* 22 * Registers are 32 bits wide; the 16 MSBs are unused -- 23 * they read as zeros and are ignored on write. 24 */ 25 26 27 /* 28 * register offsets 29 */ 30 #define IMX_URXD 0x00 /* r */ /* UART Receiver Reg */ 31 #define IMX_UTXD 0x40 /* w */ /* UART Transmitter Reg */ 32 #define IMX_UCR1 0x80 /* rw */ /* UART Control Reg 1 */ 33 #define IMX_UCR2 0x84 /* rw */ /* UART Control Reg 2 */ 34 #define IMX_UCR3 0x88 /* rw */ /* UART Control Reg 3 */ 35 #define IMX_UCR4 0x8c /* rw */ /* UART Control Reg 4 */ 36 #define IMX_UCRn(n) (IMX_UCR1 + ((n) << 2)) 37 #define IMX_UFCR 0x90 /* rw */ /* UART FIFO Control Reg */ 38 #define IMX_USR1 0x94 /* rw */ /* UART Status Reg 1 */ 39 #define IMX_USR2 0x98 /* rw */ /* UART Status Reg 2 */ 40 #define IMX_USRn(n) (IMX_USR1 + ((n) << 2)) 41 #define IMX_UESC 0x9c /* rw */ /* UART Escape Character Reg */ 42 #define IMX_UTIM 0xa0 /* rw */ /* UART Escape Timer Reg */ 43 #define IMX_UBIR 0xa4 /* rw */ /* UART BRM Incremental Reg */ 44 #define IMX_UBMR 0xa8 /* rw */ /* UART BRM Modulator Reg */ 45 #define IMX_UBRC 0xac /* r */ /* UART Baud Rate Count Reg */ 46 #define IMX_ONEMS 0xb0 /* rw */ /* UART One Millisecond Reg */ 47 #define IMX_UTS 0xb4 /* rw */ /* UART Test Reg */ 48 49 #define IMX_UART_SIZE 0xb8 50 51 /* 52 * bit attributes: 53 * ro read-only 54 * wo write-only 55 * rw read/write 56 * w1c write 1 to clear 57 * 58 * attrs defined but apparently unused for the UART: 59 * rwm rw bit that can be modified by HW (other than reset) 60 * scb self-clear: write 1 has some effect, always reads as 0 61 */ 62 63 /* 64 * IMX_URXD bits 65 */ 66 #define IMX_URXD_RX_DATA __BITS(7,0) /* ro */ 67 #define IMX_URXD_RESV __BITS(9,8) /* ro */ 68 #define IMX_URXD_PRERR __BIT(10) /* ro */ 69 #define IMX_URXD_BRK __BIT(11) /* ro */ 70 #define IMX_URXD_FRMERR __BIT(12) /* ro */ 71 #define IMX_URXD_OVRRUN __BIT(13) /* ro */ 72 #define IMX_URXD_ERR __BIT(14) /* ro */ 73 #define IMX_URXD_CHARDY __BIT(15) /* ro */ 74 75 /* 76 * IMX_UTXD bits 77 */ 78 #define IMX_UTXD_TX_DATA __BITS(7,0) /* wo */ 79 #define IMX_UTXD_RESV __BITS(15,8) 80 81 /* 82 * IMX_UCR1 bits 83 */ 84 #define IMX_UCR1_UARTEN __BIT(0) /* rw */ 85 #define IMX_UCR1_DOZE __BIT(1) /* rw */ 86 #define IMX_UCR1_ATDMAEN __BIT(2) /* rw */ 87 #define IMX_UCR1_TXDMAEN __BIT(3) /* rw */ 88 #define IMX_UCR1_SNDBRK __BIT(4) /* rw */ 89 #define IMX_UCR1_RTSDEN __BIT(5) /* rw */ 90 #define IMX_UCR1_TXMPTYEN __BIT(6) /* rw */ 91 #define IMX_UCR1_IREN __BIT(7) /* rw */ 92 #define IMX_UCR1_RXDMAEN __BIT(8) /* rw */ 93 #define IMX_UCR1_RRDYEN __BIT(9) /* rw */ 94 #define IMX_UCR1_ICD __BITS(11,10) /* rw */ 95 #define IMX_UCR1_IDEN __BIT(12) /* rw */ 96 #define IMX_UCR1_TRDYEN __BIT(13) /* rw */ 97 #define IMX_UCR1_ADBR __BIT(14) /* rw */ 98 #define IMX_UCR1_ADEN __BIT(15) /* rw */ 99 100 /* 101 * IMX_UCR2 bits 102 */ 103 #define IMX_UCR2_SRST __BIT(0) /* rw */ 104 #define IMX_UCR2_RXEN __BIT(1) /* rw */ 105 #define IMX_UCR2_TXEN __BIT(2) /* rw */ 106 #define IMX_UCR2_ATEN __BIT(3) /* rw */ 107 #define IMX_UCR2_RTSEN __BIT(4) /* rw */ 108 #define IMX_UCR2_WS __BIT(5) /* rw */ 109 #define IMX_UCR2_STPB __BIT(6) /* rw */ 110 #define IMX_UCR2_PROE __BIT(7) /* rw */ 111 #define IMX_UCR2_PREN __BIT(8) /* rw */ 112 #define IMX_UCR2_RTEC __BITS(10,9) /* rw */ 113 #define IMX_UCR2_ESCEN __BIT(11) /* rw */ 114 #define IMX_UCR2_CTS __BIT(12) /* rw */ 115 #define IMX_UCR2_CTSC __BIT(13) /* rw */ 116 #define IMX_UCR2_IRTS __BIT(14) /* rw */ 117 #define IMX_UCR2_ESCI __BIT(15) /* rw */ 118 119 /* 120 * IMX_UCR3 bits 121 */ 122 #define IMX_UCR3_ACIEN __BIT(0) /* rw */ 123 #define IMX_UCR3_INVT __BIT(1) /* rw */ 124 #define IMX_UCR3_RXDMUXSEL __BIT(2) /* rw */ 125 #define IMX_UCR3_DTRDEN __BIT(3) /* rw */ 126 #define IMX_UCR3_AWAKEN __BIT(4) /* rw */ 127 #define IMX_UCR3_AIRINTEN __BIT(5) /* rw */ 128 #define IMX_UCR3_RXDSEN __BIT(6) /* rw */ 129 #define IMX_UCR3_ADNIMP __BIT(7) /* rw */ 130 #define IMX_UCR3_RI __BIT(8) /* rw */ 131 #define IMX_UCR3_DCD __BIT(9) /* rw */ 132 #define IMX_UCR3_DSR __BIT(10) /* rw */ 133 #define IMX_UCR3_FRAERREN __BIT(11) /* rw */ 134 #define IMX_UCR3_PARERREN __BIT(12) /* rw */ 135 #define IMX_UCR3_DTREN __BIT(13) /* rw */ 136 #define IMX_UCR3_DPEC __BITS(15,14) /* rw */ 137 138 /* 139 * IMX_UCR4 bits 140 */ 141 #define IMX_UCR4_DREN __BIT(0) /* rw */ 142 #define IMX_UCR4_OREN __BIT(1) /* rw */ 143 #define IMX_UCR4_BKEN __BIT(2) /* rw */ 144 #define IMX_UCR4_TCEN __BIT(3) /* rw */ 145 #define IMX_UCR4_LPBYP __BIT(4) /* rw */ 146 #define IMX_UCR4_IRSC __BIT(5) /* rw */ 147 #define IMX_UCR4_IDDMAEN __BIT(6) /* rw */ 148 #define IMX_UCR4_WKEN __BIT(7) /* rw */ 149 #define IMX_UCR4_ENIRI __BIT(8) /* rw */ 150 #define IMX_UCR4_INVR __BIT(9) /* rw */ 151 #define IMX_UCR4_CTSTL __BITS(15,10) /* rw */ 152 153 /* 154 * IMX_UFCR bits 155 */ 156 #define IMX_UFCR_RXTL_SHIFT 0 157 #define IMX_UFCR_RXTL __BITS(5,IMX_UFCR_RXTL_SHIFT) /* rw */ 158 #define IMX_UFCR_DCEDTE __BIT(6) /* rw */ 159 #define IMX_UFCR_RFDIV_SHIFT 7 160 #define IMX_UFCR_RFDIV __BITS(9,IMX_UFCR_RFDIV_SHIFT) /* rw */ 161 #define IMX_UFCR_TXTL_SHIFT 10 162 #define IMX_UFCR_TXTL __BITS(15,IMX_UFCR_TXTL_SHIFT) /* rw */ 163 164 #define IMX_UFCR_DIVIDER_TO_RFDIV(div) \ 165 (((6 - div) % 7) & 0x7) 166 167 /* 168 * IMX_USR1 bits 169 */ 170 #define IMX_USR1_RESV __BITS(3,0) 171 #define IMX_USR1_AWAKE __BIT(4) /* w1c */ 172 #define IMX_USR1_AIRINT __BIT(5) /* w1c */ 173 #define IMX_USR1_RXDS __BIT(6) /* ro */ 174 #define IMX_USR1_DTRD __BIT(7) /* w1c */ 175 #define IMX_USR1_AGTIM __BIT(8) /* w1c */ 176 #define IMX_USR1_RRDY __BIT(9) /* ro */ 177 #define IMX_USR1_FRAMERR __BIT(10) /* w1c */ 178 #define IMX_USR1_ESCF __BIT(11) /* w1c */ 179 #define IMX_USR1_RTSD __BIT(12) /* w1c */ 180 #define IMX_USR1_TRDY __BIT(13) /* ro */ 181 #define IMX_USR1_RTSS __BIT(14) /* ro */ 182 #define IMX_USR1_PARITYERR __BIT(15) /* w1c */ 183 184 /* 185 * IMX_USR2 bits 186 */ 187 #define IMX_USR2_RDR __BIT(0) 188 #define IMX_USR2_ORE __BIT(1) /* w1c */ 189 #define IMX_USR2_BRCD __BIT(2) /* w1c */ 190 #define IMX_USR2_TXDC __BIT(3) /* ro */ 191 #define IMX_USR2_RTSF __BIT(4) /* w1c */ 192 #define IMX_USR2_DCDIN __BIT(5) /* ro */ 193 #define IMX_USR2_DCDDELT __BIT(6) /* rw */ 194 #define IMX_USR2_WAKE __BIT(7) /* w1c */ 195 #define IMX_USR2_IRINT __BIT(8) /* rw */ 196 #define IMX_USR2_RIIN __BIT(9) /* ro */ 197 #define IMX_USR2_RIDELT __BIT(10) /* w1c */ 198 #define IMX_USR2_ACST __BIT(11) /* rw */ 199 #define IMX_USR2_IDLE __BIT(12) /* w1c */ 200 #define IMX_USR2_DTRF __BIT(13) /* rw */ 201 #define IMX_USR2_TXFE __BIT(14) /* ro */ 202 #define IMX_USR2_ADET __BIT(15) /* w1c */ 203 204 /* 205 * IMX_UESC bits 206 */ 207 #define IMX_UESC_ESC_CHAR __BITS(7,0) /* rw */ 208 #define IMX_UESC_RESV __BITS(15,8) 209 210 /* 211 * IMX_UTIM bits 212 */ 213 #define IMX_UTIM_TIM __BITS(11,0) /* rw */ 214 #define IMX_UTIM_RESV __BITS(15,12) 215 216 /* 217 * IMX_UBIR bits 218 */ 219 #define IMX_UBIR_INC __BITS(15,0) /* rw */ 220 221 /* 222 * IMX_UBMR bits 223 */ 224 #define IMX_UBMR_MOD __BITS(15,0) /* rw */ 225 226 /* 227 * IMX_UBRC bits 228 */ 229 #define IMX_UBRC_BCNT __BITS(15,0) /* ro */ 230 231 /* 232 * IMX_ONEMS bits 233 */ 234 #define IMX_ONEMS_ONEMS __BITS(15,0) /* rw */ 235 236 /* 237 * IMX_UTS bits 238 */ 239 #define IMX_UTS_SOFTRST __BIT(0) /* rw */ 240 #define IMX_UTS_RESVa __BITS(2,1) 241 #define IMX_UTS_RXFULL __BIT(3) /* rw */ 242 #define IMX_UTS_TXFUL __BIT(4) /* rw */ 243 #define IMX_UTS_RXEMPTY __BIT(5) /* rw */ 244 #define IMX_UTS_TXEMPTY __BIT(5) /* rw */ 245 #define IMX_UTS_RESVb __BITS(8,7) 246 #define IMX_UTS_RXDBG __BIT(9) /* rw */ 247 #define IMX_UTS_LOOPIR __BIT(10) /* rw */ 248 #define IMX_UTS_DBGEN __BIT(11) /* rw */ 249 #define IMX_UTS_LOOP __BIT(12) /* rw */ 250 #define IMX_UTS_FRCPERR __BIT(13) /* rw */ 251 #define IMX_UTS_RESVc __BITS(15,14) 252 #define IMX_UTS_RESV (IMX_UTS_RESVa|IMX_UTS_RESVb|IMX_UTS_RESVc) 253 254 #ifndef __ASSEMBLER__ 255 /* 256 * interrupt specs 257 * see Table 31-25. "Interrupts an DMA" 258 */ 259 260 /* 261 * abstract interrupts spec indexing 262 */ 263 typedef enum { 264 RX_RRDY=0, 265 RX_ID, 266 RX_DR, 267 RX_RXDS, 268 RX_AT, 269 TX_TXMPTY, 270 TX_TRDY, 271 TX_TC, 272 MINT_OR, 273 MINT_BR, 274 MINT_WK, 275 MINT_AD, 276 MINT_ACI, 277 MINT_ESCI, 278 MINT_IRI, 279 MINT_AIRINT, 280 MINT_AWAK, 281 MINT_FRAERR, 282 MINT_PARERR, 283 MINT_RTSD, 284 MINT_RTS, 285 MINT_DCE_DTR, 286 MINT_DTE_RI, 287 MINT_DTE_DCE, 288 MINT_DTRD, 289 RX_DMAREQ_RXDMA, 290 RX_DMAREQ_ATDMA, 291 RX_DMAREQ_IDDMA, 292 RX_DMAREQ_TXDMA, 293 } imxuart_intrix_t; 294 295 /* 296 * abstract interrupts spec 297 */ 298 typedef struct { 299 const uint32_t enb_bit; 300 const uint enb_reg; 301 const uint32_t flg_bit; 302 const uint flg_reg; 303 const char * name; /* for debug */ 304 } imxuart_intrspec_t; 305 306 #define IMXUART_INTRSPEC(cv, cr, sv, sr) \ 307 { IMX_UCR##cr##_##cv, ((cr) - 1), IMX_USR##sr##_##sv, ((sr) - 1), #sv } 308 309 static const imxuart_intrspec_t imxuart_intrspec_tab[] = { 310 /* ipi_uart_rx */ 311 IMXUART_INTRSPEC(RRDYEN, 1, RRDY, 1), 312 IMXUART_INTRSPEC(IDEN, 1, IDLE, 2), 313 IMXUART_INTRSPEC(DREN, 4, RDR, 2), 314 IMXUART_INTRSPEC(RXDSEN, 3, RXDS, 1), 315 IMXUART_INTRSPEC(ATEN, 2, AGTIM, 1), 316 /* ipi_uart_tx */ 317 IMXUART_INTRSPEC(TXMPTYEN, 1, TXFE, 2), 318 IMXUART_INTRSPEC(TRDYEN, 1, TRDY, 1), 319 IMXUART_INTRSPEC(TCEN, 4, TXDC, 2), 320 /* ipi_uart_mint */ 321 IMXUART_INTRSPEC(OREN, 4, ORE, 2), 322 IMXUART_INTRSPEC(BKEN, 4, BRCD, 2), 323 IMXUART_INTRSPEC(WKEN, 4, WAKE, 2), 324 IMXUART_INTRSPEC(ADEN, 1, ADET, 2), 325 IMXUART_INTRSPEC(ACIEN, 3, ACST, 2), 326 IMXUART_INTRSPEC(ESCI, 2, ESCF, 1), 327 IMXUART_INTRSPEC(ENIRI, 4, IRINT, 2), 328 IMXUART_INTRSPEC(AIRINTEN, 3, AIRINT, 1), 329 IMXUART_INTRSPEC(AWAKEN, 3, AWAKE, 1), 330 IMXUART_INTRSPEC(FRAERREN, 3, FRAMERR, 1), 331 IMXUART_INTRSPEC(PARERREN, 3, PARITYERR, 1), 332 IMXUART_INTRSPEC(RTSDEN, 1, RTSD, 1), 333 IMXUART_INTRSPEC(RTSEN, 2, RTSF, 2), 334 IMXUART_INTRSPEC(DTREN, 3, DTRF, 2), 335 IMXUART_INTRSPEC(RI, 3, DTRF, 2), 336 IMXUART_INTRSPEC(DCD, 3, DCDDELT, 2), 337 IMXUART_INTRSPEC(DTRDEN, 3, DTRD, 1), 338 /* ipd_uart_rx_dmareq */ 339 IMXUART_INTRSPEC(RXDMAEN, 1, RRDY, 1), 340 IMXUART_INTRSPEC(ATDMAEN, 1, AGTIM, 1), 341 IMXUART_INTRSPEC(IDDMAEN, 4, IDLE, 2), 342 /* ipd_uart_tx_dmareq */ 343 IMXUART_INTRSPEC(TXDMAEN, 1, TRDY, 1), 344 }; 345 #define IMXUART_INTRSPEC_TAB_SZ \ 346 (sizeof(imxuart_intrspec_tab) / sizeof(imxuart_intrspec_tab[0])) 347 348 #endif /* __ASSEMBLER__ */ 349 350 /* 351 * functional groupings of intr status flags by reg 352 */ 353 #define IMXUART_RXINTR_USR1 (IMX_USR1_RRDY|IMX_USR1_RXDS|IMX_USR1_AGTIM) 354 #define IMXUART_RXINTR_USR2 (IMX_USR2_IDLE|IMX_USR2_RDR) 355 #define IMXUART_TXINTR_USR1 (IMX_USR1_TRDY) 356 #define IMXUART_TXINTR_USR2 (IMX_USR2_TXFE|IMX_USR2_TXDC) 357 #define IMXUART_MINT_USR1 (IMX_USR1_ESCF|IMX_USR1_AIRINT||IMX_USR1_AWAKE \ 358 |IMX_USR1_FRAMERR|IMX_USR1_PARITYERR \ 359 |IMX_USR1_RTSD|IMX_USR1_DTRD) 360 #define IMXUART_MINT_USR2 (IMX_USR2_ORE|IMX_USR2_BRCD|IMX_USR2_WAKE \ 361 |IMX_USR2_ADET|IMX_USR2_ACST|IMX_USR2_IRINT \ 362 |IMX_USR2_RTSF|IMX_USR2_DTRF|IMX_USR2_DTRF \ 363 |IMX_USR2_DCDDELT) 364 #define IMXUART_RXDMA_USR1 (IMX_USR1_RRDY|IMX_USR1_AGTIM) 365 #define IMXUART_RXDMA_USR2 (IMX_USR2_IDLE) 366 #define IMXUART_TXDMA_USR1 (IMX_USR1_TRDY) 367 #define IMXUART_TXDMA_USR2 (0) 368 369 /* 370 * all intr status flags by reg 371 */ 372 #define IMXUART_INTRS_USR1 (IMXUART_RXINTR_USR1|IMXUART_TXINTR_USR1 \ 373 |IMXUART_MINT_USR1|IMXUART_RXDMA_USR1 \ 374 |IMXUART_TXDMA_USR1) 375 #define IMXUART_INTRS_USR2 (IMXUART_RXINTR_USR2|IMXUART_TXINTR_USR2 \ 376 |IMXUART_MINT_USR2|IMXUART_RXDMA_USR2 \ 377 |IMXUART_TXDMA_USR2) 378 379 /* 380 * all intr controls by reg 381 */ 382 #define IMXUART_INTRS_UCR1 (IMX_UCR1_RRDYEN|IMX_UCR1_IDEN \ 383 |IMX_UCR1_TXMPTYEN|IMX_UCR1_TRDYEN \ 384 |IMX_UCR1_ADEN|IMX_UCR1_RTSDEN \ 385 |IMX_UCR1_RXDMAEN|IMX_UCR1_RXDMAEN \ 386 |IMX_UCR1_ATDMAEN|IMX_UCR1_TXDMAEN) 387 #define IMXUART_INTRS_UCR2 (IMX_UCR2_ATEN|IMX_UCR2_ESCI|IMX_UCR2_RTSEN) 388 #define IMXUART_INTRS_UCR3 (IMX_UCR3_RXDSEN|IMX_UCR3_ACIEN \ 389 |IMX_UCR3_AIRINTEN|IMX_UCR3_AWAKEN \ 390 |IMX_UCR3_FRAERREN|IMX_UCR3_PARERREN \ 391 |IMX_UCR3_DTREN|IMX_UCR3_RI \ 392 |IMX_UCR3_DCD|IMX_UCR3_DTRDEN) 393 #define IMXUART_INTRS_UCR4 (IMX_UCR4_DREN|IMX_UCR4_TCEN|IMX_UCR4_OREN \ 394 |IMX_UCR4_BKEN|IMX_UCR4_WKEN \ 395 |IMX_UCR4_ENIRI|IMX_UCR4_IDDMAEN) 396 397 398 #endif /* _IMXUARTREG_H */ 399
Indexes created Fri Sep 26 20:09:58 GMT 2025