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imxwdogreg.h revision 1.1.26.1
      1       1.1    bsh /*-
      2       1.1    bsh  * Copyright (c) 2010  Genetec Corporation.  All rights reserved.
      3       1.1    bsh  * Written by Hiroyuki Bessho for Genetec Corporation.
      4       1.1    bsh  *
      5       1.1    bsh  * Redistribution and use in source and binary forms, with or without
      6       1.1    bsh  * modification, are permitted provided that the following conditions
      7       1.1    bsh  * are met:
      8       1.1    bsh  * 1. Redistributions of source code must retain the above copyright
      9       1.1    bsh  *    notice, this list of conditions and the following disclaimer.
     10       1.1    bsh  * 2. Redistributions in binary form must reproduce the above
     11       1.1    bsh  *    copyright notice, this list of conditions and the following
     12       1.1    bsh  *    disclaimer in the documentation and/or other materials provided
     13       1.1    bsh  *    with the distribution.
     14       1.1    bsh  *
     15       1.1    bsh  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS''
     16       1.1    bsh  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     17       1.1    bsh  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
     18       1.1    bsh  * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS
     19       1.1    bsh  * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     20       1.1    bsh  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
     21       1.1    bsh  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
     22       1.1    bsh  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
     23       1.1    bsh  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24       1.1    bsh  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
     25       1.1    bsh  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26       1.1    bsh  * SUCH DAMAGE.
     27       1.1    bsh  */
     28       1.1    bsh 
     29       1.1    bsh /*
     30       1.1    bsh  * Watchdog register definitions for Freescale i.MX31 and i.MX51
     31       1.1    bsh  *
     32       1.1    bsh  *	MCIMX31 and MCIMX31L Application Processors
     33       1.1    bsh  *	Reference Manual
     34       1.1    bsh  *	MCIMC31RM
     35       1.1    bsh  *	Rev. 2.3
     36       1.1    bsh  *	1/2007
     37       1.1    bsh  *
     38       1.1    bsh  *	MCIMX51 Multimedia Applications Processor
     39       1.1    bsh  *      Reference Manual
     40       1.1    bsh  *      MCIMX51RM
     41       1.1    bsh  *      Rev. 1
     42       1.1    bsh  *      2/2010
     43       1.1    bsh  */
     44       1.1    bsh 
     45  1.1.26.1  rmind #ifndef _ARM_IMX_IMXWDOGREG_H
     46  1.1.26.1  rmind #define _ARM_IMX_IMXWDOGREG_H
     47       1.1    bsh 
     48       1.1    bsh #define	IMX_WDOG_WCR	0x0000	/* Watchdog Control Register */
     49       1.1    bsh #define	 WCR_WDZST	__BIT(0)	/* watchdog low power */
     50       1.1    bsh #define	 WCR_WDBG	__BIT(1)	/* watchdog debug enable */
     51       1.1    bsh #define	 WCR_WDE	__BIT(2)	/* watchdog enable */
     52       1.1    bsh #define	 WCR_WDT	__BIT(3)	/* timeout assertion */
     53       1.1    bsh #define	 WCR_SRS	__BIT(4)	/* software reset signal */
     54       1.1    bsh #define	 WCR_WDA	__BIT(5)	/* ipp_wdog* assertion */
     55       1.1    bsh #define	 WCR_WDW	__BIT(7)	/* disable for wait */
     56  1.1.26.1  rmind #define	 WCR_WT		__BITS(15, 8)
     57       1.1    bsh 					/* watchdog timeout
     58       1.1    bsh 					   0=0.5sec 0xff=128sec */
     59       1.1    bsh 
     60       1.1    bsh #define	IMX_WDOG_WSR	0x0002	/* Watchdog Service Register */
     61       1.1    bsh #define	 WSR_MAGIC1	0x5555	/* 1st word of service sequence */
     62       1.1    bsh #define	 WSR_MAGIC2	0xaaaa	/* 2nd word of service sequence */
     63       1.1    bsh 
     64       1.1    bsh #define	IMX_WDOG_WRSR	0x0004	/* Watchdog Reset Status Register */
     65       1.1    bsh #define	 WRSR_SFTW	__BIT(0)	/* reset is the result of a
     66       1.1    bsh 					 * software reset */
     67       1.1    bsh #define	 WRSR_TOUT	__BIT(1)	/* reset is the result of a
     68       1.1    bsh 					 * WDOG timeout */
     69       1.1    bsh /* only for i.MX31 */
     70       1.1    bsh #define	 WRSR_CMON	__BIT(2)
     71       1.1    bsh #define	 WRSR_EXT	__BIT(3)
     72       1.1    bsh #define	 WRSR_PWR	__BIT(4)
     73       1.1    bsh #define	 WRSR_JRST	__BIT(5)
     74       1.1    bsh 
     75       1.1    bsh /* only for i.MX51 */
     76       1.1    bsh #define	IMX_WDOG_WICR	0x0006	/* Watchdog Interrupt Control Register */
     77  1.1.26.1  rmind #define	 WICR_WICT	__BITS(7,0)	/* interrupt count timeout */
     78       1.1    bsh #define	 WICR_WTIS	__BIT(14)	/* interrupt status [w1c] */
     79       1.1    bsh #define	 WICR_WIE	__BIT(15)	/* interrupt enable */
     80       1.1    bsh 
     81       1.1    bsh /* only for i.MX51 */
     82       1.1    bsh #define	IMX_WDOG_WMCR	0x0008
     83       1.1    bsh #define	 WMCR_PDE	__BIT(0)	/* power down enable */
     84       1.1    bsh 
     85  1.1.26.1  rmind #endif /* _ARM_IMX_IMXWDOGREG_H */
     86