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imxwdogreg.h revision 1.1.26.1 
      1 /*-
      2  * Copyright (c) 2010  Genetec Corporation.  All rights reserved.
      3  * Written by Hiroyuki Bessho for Genetec Corporation.
      4  *
      5  * Redistribution and use in source and binary forms, with or without
      6  * modification, are permitted provided that the following conditions
      7  * are met:
      8  * 1. Redistributions of source code must retain the above copyright
      9  *    notice, this list of conditions and the following disclaimer.
     10  * 2. Redistributions in binary form must reproduce the above
     11  *    copyright notice, this list of conditions and the following
     12  *    disclaimer in the documentation and/or other materials provided
     13  *    with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS''
     16  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     17  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
     18  * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS
     19  * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     20  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
     21  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
     22  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
     23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
     25  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 /*
     30  * Watchdog register definitions for Freescale i.MX31 and i.MX51
     31  *
     32  *	MCIMX31 and MCIMX31L Application Processors
     33  *	Reference Manual
     34  *	MCIMC31RM
     35  *	Rev. 2.3
     36  *	1/2007
     37  *
     38  *	MCIMX51 Multimedia Applications Processor
     39  *      Reference Manual
     40  *      MCIMX51RM
     41  *      Rev. 1
     42  *      2/2010
     43  */
     44 
     45 #ifndef _ARM_IMX_IMXWDOGREG_H
     46 #define _ARM_IMX_IMXWDOGREG_H
     47 
     48 #define	IMX_WDOG_WCR	0x0000	/* Watchdog Control Register */
     49 #define	 WCR_WDZST	__BIT(0)	/* watchdog low power */
     50 #define	 WCR_WDBG	__BIT(1)	/* watchdog debug enable */
     51 #define	 WCR_WDE	__BIT(2)	/* watchdog enable */
     52 #define	 WCR_WDT	__BIT(3)	/* timeout assertion */
     53 #define	 WCR_SRS	__BIT(4)	/* software reset signal */
     54 #define	 WCR_WDA	__BIT(5)	/* ipp_wdog* assertion */
     55 #define	 WCR_WDW	__BIT(7)	/* disable for wait */
     56 #define	 WCR_WT		__BITS(15, 8)
     57 					/* watchdog timeout
     58 					   0=0.5sec 0xff=128sec */
     59 
     60 #define	IMX_WDOG_WSR	0x0002	/* Watchdog Service Register */
     61 #define	 WSR_MAGIC1	0x5555	/* 1st word of service sequence */
     62 #define	 WSR_MAGIC2	0xaaaa	/* 2nd word of service sequence */
     63 
     64 #define	IMX_WDOG_WRSR	0x0004	/* Watchdog Reset Status Register */
     65 #define	 WRSR_SFTW	__BIT(0)	/* reset is the result of a
     66 					 * software reset */
     67 #define	 WRSR_TOUT	__BIT(1)	/* reset is the result of a
     68 					 * WDOG timeout */
     69 /* only for i.MX31 */
     70 #define	 WRSR_CMON	__BIT(2)
     71 #define	 WRSR_EXT	__BIT(3)
     72 #define	 WRSR_PWR	__BIT(4)
     73 #define	 WRSR_JRST	__BIT(5)
     74 
     75 /* only for i.MX51 */
     76 #define	IMX_WDOG_WICR	0x0006	/* Watchdog Interrupt Control Register */
     77 #define	 WICR_WICT	__BITS(7,0)	/* interrupt count timeout */
     78 #define	 WICR_WTIS	__BIT(14)	/* interrupt status [w1c] */
     79 #define	 WICR_WIE	__BIT(15)	/* interrupt enable */
     80 
     81 /* only for i.MX51 */
     82 #define	IMX_WDOG_WMCR	0x0008
     83 #define	 WMCR_PDE	__BIT(0)	/* power down enable */
     84 
     85 #endif /* _ARM_IMX_IMXWDOGREG_H */
     86