frame.h revision 1.11
1 /* $NetBSD: frame.h,v 1.11 2004/04/27 07:13:16 scw Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1997 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * frame.h 40 * 41 * Stack frames structures 42 * 43 * Created : 30/09/94 44 */ 45 46 #ifndef _ARM32_FRAME_H_ 47 #define _ARM32_FRAME_H_ 48 49 #include <arm/frame.h> /* Common ARM stack frames */ 50 51 #ifndef _LOCORE 52 53 /* 54 * System stack frames. 55 */ 56 57 typedef struct irqframe { 58 unsigned int if_spsr; 59 unsigned int if_r0; 60 unsigned int if_r1; 61 unsigned int if_r2; 62 unsigned int if_r3; 63 unsigned int if_r4; 64 unsigned int if_r5; 65 unsigned int if_r6; 66 unsigned int if_r7; 67 unsigned int if_r8; 68 unsigned int if_r9; 69 unsigned int if_r10; 70 unsigned int if_r11; 71 unsigned int if_r12; 72 unsigned int if_usr_sp; 73 unsigned int if_usr_lr; 74 unsigned int if_svc_sp; 75 unsigned int if_svc_lr; 76 unsigned int if_pc; 77 } irqframe_t; 78 79 #define clockframe irqframe 80 81 /* 82 * Switch frame 83 */ 84 85 struct switchframe { 86 u_int sf_r4; 87 u_int sf_r5; 88 u_int sf_r6; 89 u_int sf_r7; 90 u_int sf_pc; 91 }; 92 93 /* 94 * Stack frame. Used during stack traces (db_trace.c) 95 */ 96 struct frame { 97 u_int fr_fp; 98 u_int fr_sp; 99 u_int fr_lr; 100 u_int fr_pc; 101 }; 102 103 #ifdef _KERNEL 104 void validate_trapframe __P((trapframe_t *, int)); 105 #endif /* _KERNEL */ 106 107 #else /* _LOCORE */ 108 109 #include "opt_compat_netbsd.h" 110 #include "opt_execfmt.h" 111 #include "opt_multiprocessor.h" 112 113 /* 114 * AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS 115 * These are used in order to support dynamic enabling/disabling of 116 * alignment faults when executing old a.out ARM binaries. 117 */ 118 #if defined(COMPAT_15) && defined(EXEC_AOUT) 119 #ifndef MULTIPROCESSOR 120 121 /* 122 * Local variables needed by the AST/Alignment Fault macroes 123 */ 124 #define AST_ALIGNMENT_FAULT_LOCALS \ 125 .Laflt_astpending: ;\ 126 .word _C_LABEL(astpending) ;\ 127 .Laflt_cpufuncs: ;\ 128 .word _C_LABEL(cpufuncs) ;\ 129 .Laflt_curpcb: ;\ 130 .word _C_LABEL(curpcb) ;\ 131 .Laflt_cpu_info_store: ;\ 132 .word _C_LABEL(cpu_info_store) 133 134 #define GET_CURPCB_ENTER \ 135 ldr r1, .Laflt_curpcb ;\ 136 ldr r1, [r1] 137 138 #define GET_CPUINFO_ENTER \ 139 ldr r0, .Laflt_cpu_info_store 140 141 #define GET_CURPCB_EXIT \ 142 ldr r1, .Laflt_curpcb ;\ 143 ldr r2, .Laflt_cpu_info_store ;\ 144 ldr r1, [r1] 145 146 #else /* !MULTIPROCESSOR */ 147 148 #define AST_ALIGNMENT_FAULT_LOCALS \ 149 .Laflt_astpending: ;\ 150 .word _C_LABEL(astpending) ;\ 151 .Laflt_cpufuncs: ;\ 152 .word _C_LABEL(cpufuncs) ;\ 153 .Laflt_cpu_info: ;\ 154 .word _C_LABEL(cpu_info) 155 156 #define GET_CURPCB_ENTER \ 157 ldr r4, .Laflt_cpu_info ;\ 158 bl _C_LABEL(cpu_number) ;\ 159 ldr r0, [r4, r0, lsl #2] ;\ 160 ldr r1, [r0, #CI_CURPCB] 161 162 #define GET_CPUINFO_ENTER /* nothing to do */ 163 164 #define GET_CURPCB_EXIT \ 165 ldr r7, .Laflt_cpu_info ;\ 166 bl _C_LABEL(cpu_number) ;\ 167 ldr r2, [r7, r0, lsl #2] ;\ 168 ldr r1, [r2, #CI_CURPCB] 169 #endif /* MULTIPROCESSOR */ 170 171 /* 172 * This macro must be invoked following PUSHFRAMEINSVC or PUSHFRAME at 173 * the top of interrupt/exception handlers. 174 * 175 * When invoked, r0 *must* contain the value of SPSR on the current 176 * trap/interrupt frame. This is always the case if ENABLE_ALIGNMENT_FAULTS 177 * is invoked immediately after PUSHFRAMEINSVC or PUSHFRAME. 178 */ 179 #define ENABLE_ALIGNMENT_FAULTS \ 180 and r0, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\ 181 teq r0, #(PSR_USR32_MODE) ;\ 182 bne 1f /* Not USR mode skip AFLT */ ;\ 183 GET_CURPCB_ENTER /* r1 = curpcb */ ;\ 184 cmp r1, #0x00 /* curpcb NULL? */ ;\ 185 ldrne r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\ 186 tstne r1, #PCB_NOALIGNFLT ;\ 187 beq 1f /* AFLTs already enabled */ ;\ 188 GET_CPUINFO_ENTER /* r0 = cpuinfo */ ;\ 189 ldr r2, .Laflt_cpufuncs ;\ 190 ldr r1, [r0, #CI_CTRL] /* Fetch control register */ ;\ 191 mov r0, #-1 ;\ 192 mov lr, pc ;\ 193 ldr pc, [r2, #CF_CONTROL] /* Enable alignment faults */ ;\ 194 1: 195 196 /* 197 * This macro must be invoked just before PULLFRAMEFROMSVCANDEXIT or 198 * PULLFRAME at the end of interrupt/exception handlers. 199 */ 200 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 201 ldr r0, [sp] /* Get the SPSR from stack */ ;\ 202 mrs r4, cpsr /* save CPSR */ ;\ 203 orr r1, r4, #(I32_bit) ;\ 204 msr cpsr_c, r1 /* Disable interrupts */ ;\ 205 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ 206 teq r0, #(PSR_USR32_MODE) ;\ 207 ldreq r5, .Laflt_astpending ;\ 208 bne 3f /* Nope, get out now */ ;\ 209 bic r4, r4, #(I32_bit) ;\ 210 1: ldr r1, [r5] /* Pending AST? */ ;\ 211 teq r1, #0x00000000 ;\ 212 bne 2f /* Yup. Go deal with it */ ;\ 213 GET_CURPCB_EXIT /* r1 = curpcb, r2 = cpuinfo */ ;\ 214 cmp r1, #0x00 /* curpcb NULL? */ ;\ 215 ldrne r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\ 216 tstne r1, #PCB_NOALIGNFLT ;\ 217 beq 3f /* Keep AFLTs enabled */ ;\ 218 ldr r1, [r2, #CI_CTRL] /* Fetch control register */ ;\ 219 ldr r2, .Laflt_cpufuncs ;\ 220 mov r0, #-1 ;\ 221 bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable AFLTs */ ;\ 222 adr lr, 3f ;\ 223 ldr pc, [r2, #CF_CONTROL] /* Set new CTRL reg value */ ;\ 224 2: mov r1, #0x00000000 ;\ 225 str r1, [r5] /* Clear astpending */ ;\ 226 msr cpsr_c, r4 /* Restore interrupts */ ;\ 227 mov r0, sp ;\ 228 bl _C_LABEL(ast) /* ast(frame) */ ;\ 229 orr r0, r4, #(I32_bit) /* Disable IRQs */ ;\ 230 msr cpsr_c, r0 ;\ 231 b 1b /* Back around again */ ;\ 232 3: 233 234 #else /* !(COMPAT_15 && EXEC_AOUT) */ 235 236 #define AST_ALIGNMENT_FAULT_LOCALS ;\ 237 .Laflt_astpending: ;\ 238 .word _C_LABEL(astpending) 239 240 #define ENABLE_ALIGNMENT_FAULTS /* nothing */ 241 242 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 243 ldr r0, [sp] /* Get the SPSR from stack */ ;\ 244 mrs r4, cpsr /* save CPSR */ ;\ 245 orr r1, r4, #(I32_bit) ;\ 246 msr cpsr_c, r1 /* Disable interrupts */ ;\ 247 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ 248 teq r0, #(PSR_USR32_MODE) ;\ 249 ldreq r5, .Laflt_astpending ;\ 250 bne 2f /* Nope, get out now */ ;\ 251 bic r4, r4, #(I32_bit) ;\ 252 ldr r1, [r5] /* Pending AST? */ ;\ 253 teq r1, #0x00000000 ;\ 254 beq 2f /* Nope. Just bail */ ;\ 255 1: mov r1, #0x00000000 ;\ 256 str r1, [r5] /* Clear astpending */ ;\ 257 msr cpsr_c, r4 /* Restore interrupts */ ;\ 258 mov r0, sp ;\ 259 bl _C_LABEL(ast) /* ast(frame) */ ;\ 260 orr r0, r4, #(I32_bit) /* Disable IRQs */ ;\ 261 msr cpsr_c, r0 ;\ 262 ldr r1, [r5] /* Another pending AST? */ ;\ 263 teq r1, #0x00000000 ;\ 264 bne 1b /* Yup. Back around again */ ;\ 265 2: 266 #endif /* COMPAT_15 && EXEC_AOUT */ 267 268 /* 269 * ASM macros for pushing and pulling trapframes from the stack 270 * 271 * These macros are used to handle the irqframe and trapframe structures 272 * defined above. 273 */ 274 275 /* 276 * PUSHFRAME - macro to push a trap frame on the stack in the current mode 277 * Since the current mode is used, the SVC lr field is not defined. 278 * 279 * NOTE: r13 and r14 are stored separately as a work around for the 280 * SA110 rev 2 STM^ bug 281 */ 282 283 #define PUSHFRAME \ 284 str lr, [sp, #-4]!; /* Push the return address */ \ 285 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \ 286 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 287 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 288 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 289 mov r0, r0; /* NOP for previous instruction */ \ 290 mrs r0, spsr_all; /* Put the SPSR on the stack */ \ 291 str r0, [sp, #-4]! 292 293 /* 294 * PULLFRAME - macro to pull a trap frame from the stack in the current mode 295 * Since the current mode is used, the SVC lr field is ignored. 296 */ 297 298 #define PULLFRAME \ 299 ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \ 300 msr spsr_all, r0; \ 301 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 302 mov r0, r0; /* NOP for previous instruction */ \ 303 add sp, sp, #(4*17); /* Adjust the stack pointer */ \ 304 ldr lr, [sp], #0x0004 /* Pull the return address */ 305 306 /* 307 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode 308 * This should only be used if the processor is not currently in SVC32 309 * mode. The processor mode is switched to SVC mode and the trap frame is 310 * stored. The SVC lr field is used to store the previous value of 311 * lr in SVC mode. 312 * 313 * NOTE: r13 and r14 are stored separately as a work around for the 314 * SA110 rev 2 STM^ bug 315 */ 316 317 #define PUSHFRAMEINSVC \ 318 stmdb sp, {r0-r3}; /* Save 4 registers */ \ 319 mov r0, lr; /* Save xxx32 r14 */ \ 320 mov r1, sp; /* Save xxx32 sp */ \ 321 mrs r3, spsr; /* Save xxx32 spsr */ \ 322 mrs r2, cpsr; /* Get the CPSR */ \ 323 bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \ 324 orr r2, r2, #(PSR_SVC32_MODE); \ 325 msr cpsr_c, r2; /* Punch into SVC mode */ \ 326 mov r2, sp; /* Save SVC sp */ \ 327 str r0, [sp, #-4]!; /* Push return address */ \ 328 str lr, [sp, #-4]!; /* Push SVC lr */ \ 329 str r2, [sp, #-4]!; /* Push SVC sp */ \ 330 msr spsr_all, r3; /* Restore correct spsr */ \ 331 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ 332 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \ 333 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 334 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 335 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 336 mov r0, r0; /* NOP for previous instruction */ \ 337 mrs r0, spsr_all; /* Put the SPSR on the stack */ \ 338 str r0, [sp, #-4]! 339 340 /* 341 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack 342 * in SVC32 mode and restore the saved processor mode and PC. 343 * This should be used when the SVC lr register needs to be restored on 344 * exit. 345 */ 346 347 #define PULLFRAMEFROMSVCANDEXIT \ 348 ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \ 349 msr spsr_all, r0; /* restore SPSR */ \ 350 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 351 mov r0, r0; /* NOP for previous instruction */ \ 352 add sp, sp, #(4*15); /* Adjust the stack pointer */ \ 353 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ 354 355 #endif /* _LOCORE */ 356 357 #endif /* _ARM32_FRAME_H_ */ 358 359 /* End of frame.h */ 360
Indexes created Tue Sep 23 02:09:52 GMT 2025