frame.h revision 1.14
1 /* $NetBSD: frame.h,v 1.14 2006/09/27 21:42:05 manu Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1997 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * frame.h 40 * 41 * Stack frames structures 42 * 43 * Created : 30/09/94 44 */ 45 46 #ifndef _ARM32_FRAME_H_ 47 #define _ARM32_FRAME_H_ 48 49 #include <arm/frame.h> /* Common ARM stack frames */ 50 51 #ifndef _LOCORE 52 53 /* 54 * System stack frames. 55 */ 56 57 typedef struct irqframe { 58 unsigned int if_spsr; 59 unsigned int if_r0; 60 unsigned int if_r1; 61 unsigned int if_r2; 62 unsigned int if_r3; 63 unsigned int if_r4; 64 unsigned int if_r5; 65 unsigned int if_r6; 66 unsigned int if_r7; 67 unsigned int if_r8; 68 unsigned int if_r9; 69 unsigned int if_r10; 70 unsigned int if_r11; 71 unsigned int if_r12; 72 unsigned int if_usr_sp; 73 unsigned int if_usr_lr; 74 unsigned int if_svc_sp; 75 unsigned int if_svc_lr; 76 unsigned int if_pc; 77 } irqframe_t; 78 79 struct clockframe { 80 struct irqframe cf_if; 81 }; 82 83 /* 84 * Switch frame 85 */ 86 87 struct switchframe { 88 u_int sf_r4; 89 u_int sf_r5; 90 u_int sf_r6; 91 u_int sf_r7; 92 u_int sf_pc; 93 }; 94 95 /* 96 * Stack frame. Used during stack traces (db_trace.c) 97 */ 98 struct frame { 99 u_int fr_fp; 100 u_int fr_sp; 101 u_int fr_lr; 102 u_int fr_pc; 103 }; 104 105 #ifdef _KERNEL 106 void validate_trapframe __P((trapframe_t *, int)); 107 #endif /* _KERNEL */ 108 109 #else /* _LOCORE */ 110 111 #include "opt_compat_netbsd.h" 112 #include "opt_execfmt.h" 113 #include "opt_multiprocessor.h" 114 115 /* 116 * AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS 117 * These are used in order to support dynamic enabling/disabling of 118 * alignment faults when executing old a.out ARM binaries. 119 */ 120 #ifdef EXEC_AOUT 121 #ifndef MULTIPROCESSOR 122 123 /* 124 * Local variables needed by the AST/Alignment Fault macroes 125 */ 126 #define AST_ALIGNMENT_FAULT_LOCALS \ 127 .Laflt_astpending: ;\ 128 .word _C_LABEL(astpending) ;\ 129 .Laflt_cpufuncs: ;\ 130 .word _C_LABEL(cpufuncs) ;\ 131 .Laflt_curpcb: ;\ 132 .word _C_LABEL(curpcb) ;\ 133 .Laflt_cpu_info_store: ;\ 134 .word _C_LABEL(cpu_info_store) 135 136 #define GET_CURPCB_ENTER \ 137 ldr r1, .Laflt_curpcb ;\ 138 ldr r1, [r1] 139 140 #define GET_CPUINFO_ENTER \ 141 ldr r0, .Laflt_cpu_info_store 142 143 #define GET_CURPCB_EXIT \ 144 ldr r1, .Laflt_curpcb ;\ 145 ldr r2, .Laflt_cpu_info_store ;\ 146 ldr r1, [r1] 147 148 #else /* !MULTIPROCESSOR */ 149 150 #define AST_ALIGNMENT_FAULT_LOCALS \ 151 .Laflt_astpending: ;\ 152 .word _C_LABEL(astpending) ;\ 153 .Laflt_cpufuncs: ;\ 154 .word _C_LABEL(cpufuncs) ;\ 155 .Laflt_cpu_info: ;\ 156 .word _C_LABEL(cpu_info) 157 158 #define GET_CURPCB_ENTER \ 159 ldr r4, .Laflt_cpu_info ;\ 160 bl _C_LABEL(cpu_number) ;\ 161 ldr r0, [r4, r0, lsl #2] ;\ 162 ldr r1, [r0, #CI_CURPCB] 163 164 #define GET_CPUINFO_ENTER /* nothing to do */ 165 166 #define GET_CURPCB_EXIT \ 167 ldr r7, .Laflt_cpu_info ;\ 168 bl _C_LABEL(cpu_number) ;\ 169 ldr r2, [r7, r0, lsl #2] ;\ 170 ldr r1, [r2, #CI_CURPCB] 171 #endif /* MULTIPROCESSOR */ 172 173 /* 174 * This macro must be invoked following PUSHFRAMEINSVC or PUSHFRAME at 175 * the top of interrupt/exception handlers. 176 * 177 * When invoked, r0 *must* contain the value of SPSR on the current 178 * trap/interrupt frame. This is always the case if ENABLE_ALIGNMENT_FAULTS 179 * is invoked immediately after PUSHFRAMEINSVC or PUSHFRAME. 180 */ 181 #define ENABLE_ALIGNMENT_FAULTS \ 182 and r0, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\ 183 teq r0, #(PSR_USR32_MODE) ;\ 184 bne 1f /* Not USR mode skip AFLT */ ;\ 185 GET_CURPCB_ENTER /* r1 = curpcb */ ;\ 186 cmp r1, #0x00 /* curpcb NULL? */ ;\ 187 ldrne r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\ 188 tstne r1, #PCB_NOALIGNFLT ;\ 189 beq 1f /* AFLTs already enabled */ ;\ 190 GET_CPUINFO_ENTER /* r0 = cpuinfo */ ;\ 191 ldr r2, .Laflt_cpufuncs ;\ 192 ldr r1, [r0, #CI_CTRL] /* Fetch control register */ ;\ 193 mov r0, #-1 ;\ 194 mov lr, pc ;\ 195 ldr pc, [r2, #CF_CONTROL] /* Enable alignment faults */ ;\ 196 1: 197 198 /* 199 * This macro must be invoked just before PULLFRAMEFROMSVCANDEXIT or 200 * PULLFRAME at the end of interrupt/exception handlers. 201 */ 202 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 203 ldr r0, [sp] /* Get the SPSR from stack */ ;\ 204 mrs r4, cpsr /* save CPSR */ ;\ 205 orr r1, r4, #(I32_bit) ;\ 206 msr cpsr_c, r1 /* Disable interrupts */ ;\ 207 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ 208 teq r0, #(PSR_USR32_MODE) ;\ 209 ldreq r5, .Laflt_astpending ;\ 210 bne 3f /* Nope, get out now */ ;\ 211 bic r4, r4, #(I32_bit) ;\ 212 1: ldr r1, [r5] /* Pending AST? */ ;\ 213 teq r1, #0x00000000 ;\ 214 bne 2f /* Yup. Go deal with it */ ;\ 215 GET_CURPCB_EXIT /* r1 = curpcb, r2 = cpuinfo */ ;\ 216 cmp r1, #0x00 /* curpcb NULL? */ ;\ 217 ldrne r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\ 218 tstne r1, #PCB_NOALIGNFLT ;\ 219 beq 3f /* Keep AFLTs enabled */ ;\ 220 ldr r1, [r2, #CI_CTRL] /* Fetch control register */ ;\ 221 ldr r2, .Laflt_cpufuncs ;\ 222 mov r0, #-1 ;\ 223 bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable AFLTs */ ;\ 224 adr lr, 3f ;\ 225 ldr pc, [r2, #CF_CONTROL] /* Set new CTRL reg value */ ;\ 226 2: mov r1, #0x00000000 ;\ 227 str r1, [r5] /* Clear astpending */ ;\ 228 msr cpsr_c, r4 /* Restore interrupts */ ;\ 229 mov r0, sp ;\ 230 bl _C_LABEL(ast) /* ast(frame) */ ;\ 231 orr r0, r4, #(I32_bit) /* Disable IRQs */ ;\ 232 msr cpsr_c, r0 ;\ 233 b 1b /* Back around again */ ;\ 234 3: 235 236 #else /* !EXEC_AOUT */ 237 238 #define AST_ALIGNMENT_FAULT_LOCALS ;\ 239 .Laflt_astpending: ;\ 240 .word _C_LABEL(astpending) 241 242 #define ENABLE_ALIGNMENT_FAULTS /* nothing */ 243 244 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 245 ldr r0, [sp] /* Get the SPSR from stack */ ;\ 246 mrs r4, cpsr /* save CPSR */ ;\ 247 orr r1, r4, #(I32_bit) ;\ 248 msr cpsr_c, r1 /* Disable interrupts */ ;\ 249 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ 250 teq r0, #(PSR_USR32_MODE) ;\ 251 ldreq r5, .Laflt_astpending ;\ 252 bne 2f /* Nope, get out now */ ;\ 253 bic r4, r4, #(I32_bit) ;\ 254 ldr r1, [r5] /* Pending AST? */ ;\ 255 teq r1, #0x00000000 ;\ 256 beq 2f /* Nope. Just bail */ ;\ 257 1: mov r1, #0x00000000 ;\ 258 str r1, [r5] /* Clear astpending */ ;\ 259 msr cpsr_c, r4 /* Restore interrupts */ ;\ 260 mov r0, sp ;\ 261 bl _C_LABEL(ast) /* ast(frame) */ ;\ 262 orr r0, r4, #(I32_bit) /* Disable IRQs */ ;\ 263 msr cpsr_c, r0 ;\ 264 ldr r1, [r5] /* Another pending AST? */ ;\ 265 teq r1, #0x00000000 ;\ 266 bne 1b /* Yup. Back around again */ ;\ 267 2: 268 #endif /* EXEC_AOUT */ 269 270 /* 271 * ASM macros for pushing and pulling trapframes from the stack 272 * 273 * These macros are used to handle the irqframe and trapframe structures 274 * defined above. 275 */ 276 277 /* 278 * PUSHFRAME - macro to push a trap frame on the stack in the current mode 279 * Since the current mode is used, the SVC lr field is not defined. 280 * 281 * NOTE: r13 and r14 are stored separately as a work around for the 282 * SA110 rev 2 STM^ bug 283 */ 284 285 #define PUSHFRAME \ 286 str lr, [sp, #-4]!; /* Push the return address */ \ 287 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \ 288 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 289 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 290 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 291 mov r0, r0; /* NOP for previous instruction */ \ 292 mrs r0, spsr_all; /* Put the SPSR on the stack */ \ 293 str r0, [sp, #-4]! 294 295 /* 296 * PULLFRAME - macro to pull a trap frame from the stack in the current mode 297 * Since the current mode is used, the SVC lr field is ignored. 298 */ 299 300 #define PULLFRAME \ 301 ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \ 302 msr spsr_all, r0; \ 303 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 304 mov r0, r0; /* NOP for previous instruction */ \ 305 add sp, sp, #(4*17); /* Adjust the stack pointer */ \ 306 ldr lr, [sp], #0x0004 /* Pull the return address */ 307 308 /* 309 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode 310 * This should only be used if the processor is not currently in SVC32 311 * mode. The processor mode is switched to SVC mode and the trap frame is 312 * stored. The SVC lr field is used to store the previous value of 313 * lr in SVC mode. 314 * 315 * NOTE: r13 and r14 are stored separately as a work around for the 316 * SA110 rev 2 STM^ bug 317 */ 318 319 #define PUSHFRAMEINSVC \ 320 stmdb sp, {r0-r3}; /* Save 4 registers */ \ 321 mov r0, lr; /* Save xxx32 r14 */ \ 322 mov r1, sp; /* Save xxx32 sp */ \ 323 mrs r3, spsr; /* Save xxx32 spsr */ \ 324 mrs r2, cpsr; /* Get the CPSR */ \ 325 bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \ 326 orr r2, r2, #(PSR_SVC32_MODE); \ 327 msr cpsr_c, r2; /* Punch into SVC mode */ \ 328 mov r2, sp; /* Save SVC sp */ \ 329 str r0, [sp, #-4]!; /* Push return address */ \ 330 str lr, [sp, #-4]!; /* Push SVC lr */ \ 331 str r2, [sp, #-4]!; /* Push SVC sp */ \ 332 msr spsr_all, r3; /* Restore correct spsr */ \ 333 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ 334 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \ 335 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 336 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 337 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 338 mov r0, r0; /* NOP for previous instruction */ \ 339 mrs r0, spsr_all; /* Put the SPSR on the stack */ \ 340 str r0, [sp, #-4]! 341 342 /* 343 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack 344 * in SVC32 mode and restore the saved processor mode and PC. 345 * This should be used when the SVC lr register needs to be restored on 346 * exit. 347 */ 348 349 #define PULLFRAMEFROMSVCANDEXIT \ 350 ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \ 351 msr spsr_all, r0; /* restore SPSR */ \ 352 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 353 mov r0, r0; /* NOP for previous instruction */ \ 354 add sp, sp, #(4*15); /* Adjust the stack pointer */ \ 355 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ 356 357 #endif /* _LOCORE */ 358 359 #endif /* _ARM32_FRAME_H_ */ 360 361 /* End of frame.h */ 362
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