frame.h revision 1.15
1 /* $NetBSD: frame.h,v 1.15 2007/03/09 19:21:58 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1997 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * frame.h 40 * 41 * Stack frames structures 42 * 43 * Created : 30/09/94 44 */ 45 46 #ifndef _ARM32_FRAME_H_ 47 #define _ARM32_FRAME_H_ 48 49 #include <arm/frame.h> /* Common ARM stack frames */ 50 51 #ifndef _LOCORE 52 53 /* 54 * System stack frames. 55 */ 56 57 typedef struct irqframe { 58 unsigned int if_spsr; 59 unsigned int if_r0; 60 unsigned int if_r1; 61 unsigned int if_r2; 62 unsigned int if_r3; 63 unsigned int if_r4; 64 unsigned int if_r5; 65 unsigned int if_r6; 66 unsigned int if_r7; 67 unsigned int if_r8; 68 unsigned int if_r9; 69 unsigned int if_r10; 70 unsigned int if_r11; 71 unsigned int if_r12; 72 unsigned int if_usr_sp; 73 unsigned int if_usr_lr; 74 unsigned int if_svc_sp; 75 unsigned int if_svc_lr; 76 unsigned int if_pc; 77 } irqframe_t; 78 79 struct clockframe { 80 struct irqframe cf_if; 81 }; 82 83 /* 84 * Switch frame 85 */ 86 87 struct switchframe { 88 u_int sf_r4; 89 u_int sf_r5; 90 u_int sf_r6; 91 u_int sf_r7; 92 u_int sf_pc; 93 }; 94 95 /* 96 * Stack frame. Used during stack traces (db_trace.c) 97 */ 98 struct frame { 99 u_int fr_fp; 100 u_int fr_sp; 101 u_int fr_lr; 102 u_int fr_pc; 103 }; 104 105 #ifdef _KERNEL 106 void validate_trapframe __P((trapframe_t *, int)); 107 #endif /* _KERNEL */ 108 109 #else /* _LOCORE */ 110 111 #include "opt_compat_netbsd.h" 112 #include "opt_execfmt.h" 113 #include "opt_multiprocessor.h" 114 #include "opt_arm_debug.h" 115 116 /* 117 * AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS 118 * These are used in order to support dynamic enabling/disabling of 119 * alignment faults when executing old a.out ARM binaries. 120 */ 121 #ifdef EXEC_AOUT 122 #ifndef MULTIPROCESSOR 123 124 /* 125 * Local variables needed by the AST/Alignment Fault macroes 126 */ 127 #define AST_ALIGNMENT_FAULT_LOCALS \ 128 .Laflt_astpending: ;\ 129 .word _C_LABEL(astpending) ;\ 130 .Laflt_cpufuncs: ;\ 131 .word _C_LABEL(cpufuncs) ;\ 132 .Laflt_curpcb: ;\ 133 .word _C_LABEL(curpcb) ;\ 134 .Laflt_cpu_info_store: ;\ 135 .word _C_LABEL(cpu_info_store) 136 137 #define GET_CURPCB_ENTER \ 138 ldr r1, .Laflt_curpcb ;\ 139 ldr r1, [r1] 140 141 #define GET_CPUINFO_ENTER \ 142 ldr r0, .Laflt_cpu_info_store 143 144 #define GET_CURPCB_EXIT \ 145 ldr r1, .Laflt_curpcb ;\ 146 ldr r2, .Laflt_cpu_info_store ;\ 147 ldr r1, [r1] 148 149 #else /* !MULTIPROCESSOR */ 150 151 #define AST_ALIGNMENT_FAULT_LOCALS \ 152 .Laflt_astpending: ;\ 153 .word _C_LABEL(astpending) ;\ 154 .Laflt_cpufuncs: ;\ 155 .word _C_LABEL(cpufuncs) ;\ 156 .Laflt_cpu_info: ;\ 157 .word _C_LABEL(cpu_info) 158 159 #define GET_CURPCB_ENTER \ 160 ldr r4, .Laflt_cpu_info ;\ 161 bl _C_LABEL(cpu_number) ;\ 162 ldr r0, [r4, r0, lsl #2] ;\ 163 ldr r1, [r0, #CI_CURPCB] 164 165 #define GET_CPUINFO_ENTER /* nothing to do */ 166 167 #define GET_CURPCB_EXIT \ 168 ldr r7, .Laflt_cpu_info ;\ 169 bl _C_LABEL(cpu_number) ;\ 170 ldr r2, [r7, r0, lsl #2] ;\ 171 ldr r1, [r2, #CI_CURPCB] 172 #endif /* MULTIPROCESSOR */ 173 174 /* 175 * This macro must be invoked following PUSHFRAMEINSVC or PUSHFRAME at 176 * the top of interrupt/exception handlers. 177 * 178 * When invoked, r0 *must* contain the value of SPSR on the current 179 * trap/interrupt frame. This is always the case if ENABLE_ALIGNMENT_FAULTS 180 * is invoked immediately after PUSHFRAMEINSVC or PUSHFRAME. 181 */ 182 #define ENABLE_ALIGNMENT_FAULTS \ 183 and r0, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\ 184 teq r0, #(PSR_USR32_MODE) ;\ 185 bne 1f /* Not USR mode skip AFLT */ ;\ 186 GET_CURPCB_ENTER /* r1 = curpcb */ ;\ 187 cmp r1, #0x00 /* curpcb NULL? */ ;\ 188 ldrne r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\ 189 tstne r1, #PCB_NOALIGNFLT ;\ 190 beq 1f /* AFLTs already enabled */ ;\ 191 GET_CPUINFO_ENTER /* r0 = cpuinfo */ ;\ 192 ldr r2, .Laflt_cpufuncs ;\ 193 ldr r1, [r0, #CI_CTRL] /* Fetch control register */ ;\ 194 mov r0, #-1 ;\ 195 mov lr, pc ;\ 196 ldr pc, [r2, #CF_CONTROL] /* Enable alignment faults */ ;\ 197 1: 198 199 /* 200 * This macro must be invoked just before PULLFRAMEFROMSVCANDEXIT or 201 * PULLFRAME at the end of interrupt/exception handlers. 202 */ 203 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 204 ldr r0, [sp] /* Get the SPSR from stack */ ;\ 205 mrs r4, cpsr /* save CPSR */ ;\ 206 orr r1, r4, #(I32_bit) ;\ 207 msr cpsr_c, r1 /* Disable interrupts */ ;\ 208 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ 209 teq r0, #(PSR_USR32_MODE) ;\ 210 ldreq r5, .Laflt_astpending ;\ 211 bne 3f /* Nope, get out now */ ;\ 212 bic r4, r4, #(I32_bit) ;\ 213 1: ldr r1, [r5] /* Pending AST? */ ;\ 214 teq r1, #0x00000000 ;\ 215 bne 2f /* Yup. Go deal with it */ ;\ 216 GET_CURPCB_EXIT /* r1 = curpcb, r2 = cpuinfo */ ;\ 217 cmp r1, #0x00 /* curpcb NULL? */ ;\ 218 ldrne r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\ 219 tstne r1, #PCB_NOALIGNFLT ;\ 220 beq 3f /* Keep AFLTs enabled */ ;\ 221 ldr r1, [r2, #CI_CTRL] /* Fetch control register */ ;\ 222 ldr r2, .Laflt_cpufuncs ;\ 223 mov r0, #-1 ;\ 224 bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable AFLTs */ ;\ 225 adr lr, 3f ;\ 226 ldr pc, [r2, #CF_CONTROL] /* Set new CTRL reg value */ ;\ 227 2: mov r1, #0x00000000 ;\ 228 str r1, [r5] /* Clear astpending */ ;\ 229 msr cpsr_c, r4 /* Restore interrupts */ ;\ 230 mov r0, sp ;\ 231 bl _C_LABEL(ast) /* ast(frame) */ ;\ 232 orr r0, r4, #(I32_bit) /* Disable IRQs */ ;\ 233 msr cpsr_c, r0 ;\ 234 b 1b /* Back around again */ ;\ 235 3: 236 237 #else /* !EXEC_AOUT */ 238 239 #define AST_ALIGNMENT_FAULT_LOCALS ;\ 240 .Laflt_astpending: ;\ 241 .word _C_LABEL(astpending) 242 243 #define ENABLE_ALIGNMENT_FAULTS /* nothing */ 244 245 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 246 ldr r0, [sp] /* Get the SPSR from stack */ ;\ 247 mrs r4, cpsr /* save CPSR */ ;\ 248 orr r1, r4, #(I32_bit) ;\ 249 msr cpsr_c, r1 /* Disable interrupts */ ;\ 250 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ 251 teq r0, #(PSR_USR32_MODE) ;\ 252 ldreq r5, .Laflt_astpending ;\ 253 bne 2f /* Nope, get out now */ ;\ 254 bic r4, r4, #(I32_bit) ;\ 255 ldr r1, [r5] /* Pending AST? */ ;\ 256 teq r1, #0x00000000 ;\ 257 beq 2f /* Nope. Just bail */ ;\ 258 1: mov r1, #0x00000000 ;\ 259 str r1, [r5] /* Clear astpending */ ;\ 260 msr cpsr_c, r4 /* Restore interrupts */ ;\ 261 mov r0, sp ;\ 262 bl _C_LABEL(ast) /* ast(frame) */ ;\ 263 orr r0, r4, #(I32_bit) /* Disable IRQs */ ;\ 264 msr cpsr_c, r0 ;\ 265 ldr r1, [r5] /* Another pending AST? */ ;\ 266 teq r1, #0x00000000 ;\ 267 bne 1b /* Yup. Back around again */ ;\ 268 2: 269 #endif /* EXEC_AOUT */ 270 271 #ifdef ARM_LOCK_CAS_DEBUG 272 #define LOCK_CAS_DEBUG_LOCALS \ 273 .L_lock_cas_restart: ;\ 274 .word _C_LABEL(_lock_cas_restart) 275 276 #if defined(__ARMEB__) 277 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 278 ble 99f ;\ 279 ldr r0, .L_lock_cas_restart ;\ 280 ldmia r0, {r1-r2} /* load ev_count */ ;\ 281 adds r2, r2, #1 /* 64-bit incr (lo) */ ;\ 282 adc r1, r1, #0 /* 64-bit incr (hi) */ ;\ 283 stmia r0, {r1-r2} /* store ev_count */ 284 #else /* __ARMEB__ */ 285 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 286 ble 99f ;\ 287 ldr r0, .L_lock_cas_restart ;\ 288 ldmia r0, {r1-r2} /* load ev_count */ ;\ 289 adds r1, r1, #1 /* 64-bit incr (lo) */ ;\ 290 adc r2, r2, #0 /* 64-bit incr (hi) */ ;\ 291 stmia r0, {r1-r2} /* store ev_count */ 292 #endif /* __ARMEB__ */ 293 #else /* ARM_LOCK_CAS_DEBUG */ 294 #define LOCK_CAS_DEBUG_LOCALS /* nothing */ 295 #define LOCK_CAS_DEBUG_COUNT_RESTART /* nothing */ 296 #endif /* ARM_LOCK_CAS_DEBUG */ 297 298 #define LOCK_CAS_CHECK_LOCALS \ 299 .L_lock_cas: ;\ 300 .word _C_LABEL(_lock_cas) ;\ 301 .L_lock_cas_end: ;\ 302 .word _C_LABEL(_lock_cas_end) ;\ 303 LOCK_CAS_DEBUG_LOCALS 304 305 #define LOCK_CAS_CHECK \ 306 ldr r0, [sp] /* get saved PSR */ ;\ 307 and r0, r0, #(PSR_MODE) /* check for SVC32 mode */ ;\ 308 teq r0, #(PSR_SVC32_MODE) ;\ 309 bne 99f /* nope, get out now */ ;\ 310 ldr r0, [sp, #(IF_PC)] ;\ 311 ldr r1, .L_lock_cas_end ;\ 312 cmp r0, r1 ;\ 313 bge 99f ;\ 314 ldr r1, .L_lock_cas ;\ 315 cmp r0, r1 ;\ 316 strgt r1, [sp, #(IF_PC)] ;\ 317 LOCK_CAS_DEBUG_COUNT_RESTART ;\ 318 99: 319 320 /* 321 * ASM macros for pushing and pulling trapframes from the stack 322 * 323 * These macros are used to handle the irqframe and trapframe structures 324 * defined above. 325 */ 326 327 /* 328 * PUSHFRAME - macro to push a trap frame on the stack in the current mode 329 * Since the current mode is used, the SVC lr field is not defined. 330 * 331 * NOTE: r13 and r14 are stored separately as a work around for the 332 * SA110 rev 2 STM^ bug 333 */ 334 335 #define PUSHFRAME \ 336 str lr, [sp, #-4]!; /* Push the return address */ \ 337 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \ 338 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 339 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 340 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 341 mov r0, r0; /* NOP for previous instruction */ \ 342 mrs r0, spsr_all; /* Put the SPSR on the stack */ \ 343 str r0, [sp, #-4]! 344 345 /* 346 * PULLFRAME - macro to pull a trap frame from the stack in the current mode 347 * Since the current mode is used, the SVC lr field is ignored. 348 */ 349 350 #define PULLFRAME \ 351 ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \ 352 msr spsr_all, r0; \ 353 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 354 mov r0, r0; /* NOP for previous instruction */ \ 355 add sp, sp, #(4*17); /* Adjust the stack pointer */ \ 356 ldr lr, [sp], #0x0004 /* Pull the return address */ 357 358 /* 359 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode 360 * This should only be used if the processor is not currently in SVC32 361 * mode. The processor mode is switched to SVC mode and the trap frame is 362 * stored. The SVC lr field is used to store the previous value of 363 * lr in SVC mode. 364 * 365 * NOTE: r13 and r14 are stored separately as a work around for the 366 * SA110 rev 2 STM^ bug 367 */ 368 369 #define PUSHFRAMEINSVC \ 370 stmdb sp, {r0-r3}; /* Save 4 registers */ \ 371 mov r0, lr; /* Save xxx32 r14 */ \ 372 mov r1, sp; /* Save xxx32 sp */ \ 373 mrs r3, spsr; /* Save xxx32 spsr */ \ 374 mrs r2, cpsr; /* Get the CPSR */ \ 375 bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \ 376 orr r2, r2, #(PSR_SVC32_MODE); \ 377 msr cpsr_c, r2; /* Punch into SVC mode */ \ 378 mov r2, sp; /* Save SVC sp */ \ 379 str r0, [sp, #-4]!; /* Push return address */ \ 380 str lr, [sp, #-4]!; /* Push SVC lr */ \ 381 str r2, [sp, #-4]!; /* Push SVC sp */ \ 382 msr spsr_all, r3; /* Restore correct spsr */ \ 383 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ 384 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \ 385 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 386 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 387 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 388 mov r0, r0; /* NOP for previous instruction */ \ 389 mrs r0, spsr_all; /* Put the SPSR on the stack */ \ 390 str r0, [sp, #-4]! 391 392 /* 393 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack 394 * in SVC32 mode and restore the saved processor mode and PC. 395 * This should be used when the SVC lr register needs to be restored on 396 * exit. 397 */ 398 399 #define PULLFRAMEFROMSVCANDEXIT \ 400 ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \ 401 msr spsr_all, r0; /* restore SPSR */ \ 402 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 403 mov r0, r0; /* NOP for previous instruction */ \ 404 add sp, sp, #(4*15); /* Adjust the stack pointer */ \ 405 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ 406 407 #endif /* _LOCORE */ 408 409 #endif /* _ARM32_FRAME_H_ */ 410 411 /* End of frame.h */ 412
Indexes created Wed Sep 24 05:09:52 GMT 2025