frame.h revision 1.15.22.1
1 /* $NetBSD: frame.h,v 1.15.22.1 2007/08/28 18:49:00 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1997 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * frame.h 40 * 41 * Stack frames structures 42 * 43 * Created : 30/09/94 44 */ 45 46 #ifndef _ARM32_FRAME_H_ 47 #define _ARM32_FRAME_H_ 48 49 #include <arm/frame.h> /* Common ARM stack frames */ 50 51 #ifndef _LOCORE 52 53 /* 54 * System stack frames. 55 */ 56 57 typedef struct irqframe { 58 unsigned int if_spsr; 59 unsigned int if_r0; 60 unsigned int if_r1; 61 unsigned int if_r2; 62 unsigned int if_r3; 63 unsigned int if_r4; 64 unsigned int if_r5; 65 unsigned int if_r6; 66 unsigned int if_r7; 67 unsigned int if_r8; 68 unsigned int if_r9; 69 unsigned int if_r10; 70 unsigned int if_r11; 71 unsigned int if_r12; 72 unsigned int if_usr_sp; 73 unsigned int if_usr_lr; 74 unsigned int if_svc_sp; 75 unsigned int if_svc_lr; 76 unsigned int if_pc; 77 } irqframe_t; 78 79 struct clockframe { 80 struct irqframe cf_if; 81 }; 82 83 /* 84 * Switch frame 85 */ 86 87 struct switchframe { 88 u_int sf_r4; 89 u_int sf_r5; 90 u_int sf_r6; 91 u_int sf_r7; 92 u_int sf_pc; 93 }; 94 95 /* 96 * Stack frame. Used during stack traces (db_trace.c) 97 */ 98 struct frame { 99 u_int fr_fp; 100 u_int fr_sp; 101 u_int fr_lr; 102 u_int fr_pc; 103 }; 104 105 #ifdef _KERNEL 106 void validate_trapframe __P((trapframe_t *, int)); 107 #endif /* _KERNEL */ 108 109 #else /* _LOCORE */ 110 111 #include "opt_compat_netbsd.h" 112 #include "opt_execfmt.h" 113 #include "opt_multiprocessor.h" 114 #include "opt_cpuoptions.h" 115 #include "opt_arm_debug.h" 116 117 #include <machine/cpu.h> 118 119 /* 120 * AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS 121 * These are used in order to support dynamic enabling/disabling of 122 * alignment faults when executing old a.out ARM binaries. 123 * 124 * Note that when ENABLE_ALIGNMENTS_FAULTS finishes r4 will contain 125 * pointer to the cpu's cpu_info. DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 126 * relies on r4 being preserved. 127 */ 128 #ifdef EXEC_AOUT 129 #if defined(PROCESS_ID_IS_CURLWP) || defined(PROCESS_ID_IS_CURCPU) 130 131 #define AST_ALIGNMENT_FAULT_LOCALS \ 132 .Laflt_cpufuncs: ;\ 133 .word _C_LABEL(cpufuncs) 134 135 #elif !defined(MULTIPROCESSOR) 136 137 /* 138 * Local variables needed by the AST/Alignment Fault macroes 139 */ 140 #define AST_ALIGNMENT_FAULT_LOCALS \ 141 .Laflt_cpufuncs: ;\ 142 .word _C_LABEL(cpufuncs) ;\ 143 .Laflt_cpu_info_store: ;\ 144 .word _C_LABEL(cpu_info_store) 145 146 #define GET_CURCPU(rX) \ 147 ldr rX, .Laflt_cpu_info_store 148 149 #else /* !MULTIPROCESSOR */ 150 151 #define AST_ALIGNMENT_FAULT_LOCALS \ 152 .Laflt_cpufuncs: ;\ 153 .word _C_LABEL(cpufuncs) ;\ 154 .Laflt_cpu_info: ;\ 155 .word _C_LABEL(cpu_info) 156 157 #define GET_CURCPU(rX) \ 158 ldr rX, .Laflt_cpu_info ;\ 159 bl _C_LABEL(cpu_number) ;\ 160 ldr r0, [rX, r0, lsl #2] 161 162 #endif /* MULTIPROCESSOR */ 163 164 /* 165 * This macro must be invoked following PUSHFRAMEINSVC or PUSHFRAME at 166 * the top of interrupt/exception handlers. 167 * 168 * When invoked, r0 *must* contain the value of SPSR on the current 169 * trap/interrupt frame. This is always the case if ENABLE_ALIGNMENT_FAULTS 170 * is invoked immediately after PUSHFRAMEINSVC or PUSHFRAME. 171 */ 172 #define ENABLE_ALIGNMENT_FAULTS \ 173 and r0, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\ 174 teq r0, #(PSR_USR32_MODE) ;\ 175 bne 1f /* Not USR mode skip AFLT */ ;\ 176 GET_CURCPU(r4) /* r4 = cpuinfo */ ;\ 177 ldr r1, [r4, #CI_CURPCB] /* get curpcb from cpu_info */ ;\ 178 ldr r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\ 179 tst r1, #PCB_NOALIGNFLT ;\ 180 beq 1f /* AFLTs already enabled */ ;\ 181 ldr r2, .Laflt_cpufuncs ;\ 182 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\ 183 mov r0, #-1 ;\ 184 mov lr, pc ;\ 185 ldr pc, [r2, #CF_CONTROL] /* Enable alignment faults */ ;\ 186 1: 187 188 /* 189 * This macro must be invoked just before PULLFRAMEFROMSVCANDEXIT or 190 * PULLFRAME at the end of interrupt/exception handlers. We know that 191 * r4 points to cpu_info since that is what ENABLE_ALIGNMENT_FAULTS did 192 * for use. 193 */ 194 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 195 ldr r0, [sp] /* Get the SPSR from stack */ ;\ 196 mrs r5, cpsr /* save CPSR */ ;\ 197 orr r1, r5, #(I32_bit) ;\ 198 msr cpsr_c, r1 /* Disable interrupts */ ;\ 199 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ 200 teq r0, #(PSR_USR32_MODE) ;\ 201 bne 3f /* Nope, get out now */ ;\ 202 1: ldr r0, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\ 203 teq r0, #0x00000000 ;\ 204 bne 2f /* Yup. Go deal with it */ ;\ 205 ldr r1, [r4, #CI_CURPCB] /* Get current PCB */ ;\ 206 ldr r0, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\ 207 tst r0, #PCB_NOALIGNFLT ;\ 208 beq 3f /* Keep AFLTs enabled */ ;\ 209 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\ 210 ldr r2, .Laflt_cpufuncs ;\ 211 mov r0, #-1 ;\ 212 bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable AFLTs */ ;\ 213 adr lr, 3f ;\ 214 ldr pc, [r2, #CF_CONTROL] /* Set new CTRL reg value */ ;\ 215 /* NOTREACHED */ \ 216 2: mov r1, #0x00000000 ;\ 217 str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\ 218 bic r5, r5, #(I32_bit) ;\ 219 msr cpsr_c, r5 /* Restore interrupts */ ;\ 220 mov r0, sp ;\ 221 bl _C_LABEL(ast) /* ast(frame) */ ;\ 222 orr r0, r5, #(I32_bit) /* Disable IRQs */ ;\ 223 msr cpsr_c, r0 ;\ 224 b 1b /* Back around again */ ;\ 225 3: 226 227 #else /* !EXEC_AOUT */ 228 229 #if defined(PROCESS_ID_IS_CURLWP) || defined(PROCESS_ID_IS_CURCPU) 230 #define AST_ALIGNMENT_FAULT_LOCALS 231 232 #elif !defined(MULTIPROCESSOR) 233 #define AST_ALIGNMENT_FAULT_LOCALS \ 234 .Laflt_cpu_info_store: ;\ 235 .word _C_LABEL(cpu_info_store) 236 237 #define GET_CURCPU(rX) \ 238 ldr rX, .Laflt_cpu_info_store 239 240 #else 241 #define AST_ALIGNMENT_FAULT_LOCALS \ 242 .Laflt_cpu_info: ;\ 243 .word _C_LABEL(cpu_info) 244 245 #define GET_CURCPU(rX) \ 246 bl _C_LABEL(cpu_number) ;\ 247 ldr r1, .Laflt_cpu_info ;\ 248 ldr rX, [r1, r0, lsl #2] 249 250 #endif 251 252 #define ENABLE_ALIGNMENT_FAULTS GET_CURCPU(r4) 253 254 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 255 ldr r0, [sp] /* Get the SPSR from stack */ ;\ 256 mrs r5, cpsr /* save CPSR */ ;\ 257 orr r1, r5, #(I32_bit) ;\ 258 msr cpsr_c, r1 /* Disable interrupts */ ;\ 259 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ 260 teq r0, #(PSR_USR32_MODE) ;\ 261 bne 2f /* Nope, get out now */ ;\ 262 1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\ 263 teq r1, #0x00000000 ;\ 264 beq 2f /* Nope. Just bail */ ;\ 265 mov r1, #0x00000000 ;\ 266 str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\ 267 bic r5, r5, #(I32_bit) ;\ 268 msr cpsr_c, r5 /* Restore interrupts */ ;\ 269 mov r0, sp ;\ 270 bl _C_LABEL(ast) /* ast(frame) */ ;\ 271 orr r0, r5, #(I32_bit) /* Disable IRQs */ ;\ 272 msr cpsr_c, r0 ;\ 273 b 1b ;\ 274 2: 275 #endif /* EXEC_AOUT */ 276 277 #ifdef ARM_LOCK_CAS_DEBUG 278 #define LOCK_CAS_DEBUG_LOCALS \ 279 .L_lock_cas_restart: ;\ 280 .word _C_LABEL(_lock_cas_restart) 281 282 #if defined(__ARMEB__) 283 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 284 ble 99f ;\ 285 ldr r0, .L_lock_cas_restart ;\ 286 ldmia r0, {r1-r2} /* load ev_count */ ;\ 287 adds r2, r2, #1 /* 64-bit incr (lo) */ ;\ 288 adc r1, r1, #0 /* 64-bit incr (hi) */ ;\ 289 stmia r0, {r1-r2} /* store ev_count */ 290 #else /* __ARMEB__ */ 291 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 292 ble 99f ;\ 293 ldr r0, .L_lock_cas_restart ;\ 294 ldmia r0, {r1-r2} /* load ev_count */ ;\ 295 adds r1, r1, #1 /* 64-bit incr (lo) */ ;\ 296 adc r2, r2, #0 /* 64-bit incr (hi) */ ;\ 297 stmia r0, {r1-r2} /* store ev_count */ 298 #endif /* __ARMEB__ */ 299 #else /* ARM_LOCK_CAS_DEBUG */ 300 #define LOCK_CAS_DEBUG_LOCALS /* nothing */ 301 #define LOCK_CAS_DEBUG_COUNT_RESTART /* nothing */ 302 #endif /* ARM_LOCK_CAS_DEBUG */ 303 304 #define LOCK_CAS_CHECK_LOCALS \ 305 .L_lock_cas: ;\ 306 .word _C_LABEL(_lock_cas) ;\ 307 .L_lock_cas_end: ;\ 308 .word _C_LABEL(_lock_cas_end) ;\ 309 LOCK_CAS_DEBUG_LOCALS 310 311 #define LOCK_CAS_CHECK \ 312 ldr r0, [sp] /* get saved PSR */ ;\ 313 and r0, r0, #(PSR_MODE) /* check for SVC32 mode */ ;\ 314 teq r0, #(PSR_SVC32_MODE) ;\ 315 bne 99f /* nope, get out now */ ;\ 316 ldr r0, [sp, #(IF_PC)] ;\ 317 ldr r1, .L_lock_cas_end ;\ 318 cmp r0, r1 ;\ 319 bge 99f ;\ 320 ldr r1, .L_lock_cas ;\ 321 cmp r0, r1 ;\ 322 strgt r1, [sp, #(IF_PC)] ;\ 323 LOCK_CAS_DEBUG_COUNT_RESTART ;\ 324 99: 325 326 /* 327 * ASM macros for pushing and pulling trapframes from the stack 328 * 329 * These macros are used to handle the irqframe and trapframe structures 330 * defined above. 331 */ 332 333 /* 334 * PUSHFRAME - macro to push a trap frame on the stack in the current mode 335 * Since the current mode is used, the SVC lr field is not defined. 336 * 337 * NOTE: r13 and r14 are stored separately as a work around for the 338 * SA110 rev 2 STM^ bug 339 */ 340 341 #define PUSHFRAME \ 342 str lr, [sp, #-4]!; /* Push the return address */ \ 343 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \ 344 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 345 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 346 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 347 mov r0, r0; /* NOP for previous instruction */ \ 348 mrs r0, spsr_all; /* Put the SPSR on the stack */ \ 349 str r0, [sp, #-4]! 350 351 /* 352 * PULLFRAME - macro to pull a trap frame from the stack in the current mode 353 * Since the current mode is used, the SVC lr field is ignored. 354 */ 355 356 #define PULLFRAME \ 357 ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \ 358 msr spsr_all, r0; \ 359 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 360 mov r0, r0; /* NOP for previous instruction */ \ 361 add sp, sp, #(4*17); /* Adjust the stack pointer */ \ 362 ldr lr, [sp], #0x0004 /* Pull the return address */ 363 364 /* 365 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode 366 * This should only be used if the processor is not currently in SVC32 367 * mode. The processor mode is switched to SVC mode and the trap frame is 368 * stored. The SVC lr field is used to store the previous value of 369 * lr in SVC mode. 370 * 371 * NOTE: r13 and r14 are stored separately as a work around for the 372 * SA110 rev 2 STM^ bug 373 */ 374 375 #define PUSHFRAMEINSVC \ 376 stmdb sp, {r0-r3}; /* Save 4 registers */ \ 377 mov r0, lr; /* Save xxx32 r14 */ \ 378 mov r1, sp; /* Save xxx32 sp */ \ 379 mrs r3, spsr; /* Save xxx32 spsr */ \ 380 mrs r2, cpsr; /* Get the CPSR */ \ 381 bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \ 382 orr r2, r2, #(PSR_SVC32_MODE); \ 383 msr cpsr_c, r2; /* Punch into SVC mode */ \ 384 mov r2, sp; /* Save SVC sp */ \ 385 str r0, [sp, #-4]!; /* Push return address */ \ 386 str lr, [sp, #-4]!; /* Push SVC lr */ \ 387 str r2, [sp, #-4]!; /* Push SVC sp */ \ 388 msr spsr_all, r3; /* Restore correct spsr */ \ 389 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ 390 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \ 391 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 392 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 393 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 394 mov r0, r0; /* NOP for previous instruction */ \ 395 mrs r0, spsr_all; /* Put the SPSR on the stack */ \ 396 str r0, [sp, #-4]! 397 398 /* 399 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack 400 * in SVC32 mode and restore the saved processor mode and PC. 401 * This should be used when the SVC lr register needs to be restored on 402 * exit. 403 */ 404 405 #define PULLFRAMEFROMSVCANDEXIT \ 406 ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \ 407 msr spsr_all, r0; /* restore SPSR */ \ 408 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 409 mov r0, r0; /* NOP for previous instruction */ \ 410 add sp, sp, #(4*15); /* Adjust the stack pointer */ \ 411 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ 412 413 #endif /* _LOCORE */ 414 415 #endif /* _ARM32_FRAME_H_ */ 416
Indexes created Tue Oct 21 08:09:48 GMT 2025