frame.h revision 1.16
1 /* $NetBSD: frame.h,v 1.16 2008/01/12 20:50:24 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1997 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * frame.h 40 * 41 * Stack frames structures 42 * 43 * Created : 30/09/94 44 */ 45 46 #ifndef _ARM32_FRAME_H_ 47 #define _ARM32_FRAME_H_ 48 49 #include <arm/frame.h> /* Common ARM stack frames */ 50 51 #ifndef _LOCORE 52 53 /* 54 * System stack frames. 55 */ 56 57 typedef struct irqframe { 58 unsigned int if_spsr; 59 unsigned int if_r0; 60 unsigned int if_r1; 61 unsigned int if_r2; 62 unsigned int if_r3; 63 unsigned int if_r4; 64 unsigned int if_r5; 65 unsigned int if_r6; 66 unsigned int if_r7; 67 unsigned int if_r8; 68 unsigned int if_r9; 69 unsigned int if_r10; 70 unsigned int if_r11; 71 unsigned int if_r12; 72 unsigned int if_usr_sp; 73 unsigned int if_usr_lr; 74 unsigned int if_svc_sp; 75 unsigned int if_svc_lr; 76 unsigned int if_pc; 77 } irqframe_t; 78 79 struct clockframe { 80 struct irqframe cf_if; 81 }; 82 83 /* 84 * Switch frame. 85 * 86 * Should be a multiple of 8 bytes for dumpsys. 87 */ 88 89 struct switchframe { 90 u_int sf_r4; 91 u_int sf_r5; 92 u_int sf_r6; 93 u_int sf_r7; 94 u_int sf_sp; 95 u_int sf_pc; 96 }; 97 98 /* 99 * Stack frame. Used during stack traces (db_trace.c) 100 */ 101 struct frame { 102 u_int fr_fp; 103 u_int fr_sp; 104 u_int fr_lr; 105 u_int fr_pc; 106 }; 107 108 #ifdef _KERNEL 109 void validate_trapframe __P((trapframe_t *, int)); 110 #endif /* _KERNEL */ 111 112 #else /* _LOCORE */ 113 114 #include "opt_compat_netbsd.h" 115 #include "opt_execfmt.h" 116 #include "opt_multiprocessor.h" 117 #include "opt_arm_debug.h" 118 119 /* 120 * AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS 121 * These are used in order to support dynamic enabling/disabling of 122 * alignment faults when executing old a.out ARM binaries. 123 */ 124 #ifdef EXEC_AOUT 125 #ifndef MULTIPROCESSOR 126 127 /* 128 * Local variables needed by the AST/Alignment Fault macroes 129 */ 130 #define AST_ALIGNMENT_FAULT_LOCALS \ 131 .Laflt_astpending: ;\ 132 .word _C_LABEL(astpending) ;\ 133 .Laflt_cpufuncs: ;\ 134 .word _C_LABEL(cpufuncs) ;\ 135 .Laflt_curpcb: ;\ 136 .word _C_LABEL(curpcb) ;\ 137 .Laflt_cpu_info_store: ;\ 138 .word _C_LABEL(cpu_info_store) 139 140 #define GET_CURPCB_ENTER \ 141 ldr r1, .Laflt_curpcb ;\ 142 ldr r1, [r1] 143 144 #define GET_CPUINFO_ENTER \ 145 ldr r0, .Laflt_cpu_info_store 146 147 #define GET_CURPCB_EXIT \ 148 ldr r1, .Laflt_curpcb ;\ 149 ldr r2, .Laflt_cpu_info_store ;\ 150 ldr r1, [r1] 151 152 #else /* !MULTIPROCESSOR */ 153 154 #define AST_ALIGNMENT_FAULT_LOCALS \ 155 .Laflt_astpending: ;\ 156 .word _C_LABEL(astpending) ;\ 157 .Laflt_cpufuncs: ;\ 158 .word _C_LABEL(cpufuncs) ;\ 159 .Laflt_cpu_info: ;\ 160 .word _C_LABEL(cpu_info) 161 162 #define GET_CURPCB_ENTER \ 163 ldr r4, .Laflt_cpu_info ;\ 164 bl _C_LABEL(cpu_number) ;\ 165 ldr r0, [r4, r0, lsl #2] ;\ 166 ldr r1, [r0, #CI_CURPCB] 167 168 #define GET_CPUINFO_ENTER /* nothing to do */ 169 170 #define GET_CURPCB_EXIT \ 171 ldr r7, .Laflt_cpu_info ;\ 172 bl _C_LABEL(cpu_number) ;\ 173 ldr r2, [r7, r0, lsl #2] ;\ 174 ldr r1, [r2, #CI_CURPCB] 175 #endif /* MULTIPROCESSOR */ 176 177 /* 178 * This macro must be invoked following PUSHFRAMEINSVC or PUSHFRAME at 179 * the top of interrupt/exception handlers. 180 * 181 * When invoked, r0 *must* contain the value of SPSR on the current 182 * trap/interrupt frame. This is always the case if ENABLE_ALIGNMENT_FAULTS 183 * is invoked immediately after PUSHFRAMEINSVC or PUSHFRAME. 184 */ 185 #define ENABLE_ALIGNMENT_FAULTS \ 186 and r0, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\ 187 teq r0, #(PSR_USR32_MODE) ;\ 188 bne 1f /* Not USR mode skip AFLT */ ;\ 189 GET_CURPCB_ENTER /* r1 = curpcb */ ;\ 190 cmp r1, #0x00 /* curpcb NULL? */ ;\ 191 ldrne r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\ 192 tstne r1, #PCB_NOALIGNFLT ;\ 193 beq 1f /* AFLTs already enabled */ ;\ 194 GET_CPUINFO_ENTER /* r0 = cpuinfo */ ;\ 195 ldr r2, .Laflt_cpufuncs ;\ 196 ldr r1, [r0, #CI_CTRL] /* Fetch control register */ ;\ 197 mov r0, #-1 ;\ 198 mov lr, pc ;\ 199 ldr pc, [r2, #CF_CONTROL] /* Enable alignment faults */ ;\ 200 1: 201 202 /* 203 * This macro must be invoked just before PULLFRAMEFROMSVCANDEXIT or 204 * PULLFRAME at the end of interrupt/exception handlers. 205 */ 206 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 207 ldr r0, [sp] /* Get the SPSR from stack */ ;\ 208 mrs r4, cpsr /* save CPSR */ ;\ 209 orr r1, r4, #(I32_bit) ;\ 210 msr cpsr_c, r1 /* Disable interrupts */ ;\ 211 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ 212 teq r0, #(PSR_USR32_MODE) ;\ 213 ldreq r5, .Laflt_astpending ;\ 214 bne 3f /* Nope, get out now */ ;\ 215 bic r4, r4, #(I32_bit) ;\ 216 1: ldr r1, [r5] /* Pending AST? */ ;\ 217 teq r1, #0x00000000 ;\ 218 bne 2f /* Yup. Go deal with it */ ;\ 219 GET_CURPCB_EXIT /* r1 = curpcb, r2 = cpuinfo */ ;\ 220 cmp r1, #0x00 /* curpcb NULL? */ ;\ 221 ldrne r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\ 222 tstne r1, #PCB_NOALIGNFLT ;\ 223 beq 3f /* Keep AFLTs enabled */ ;\ 224 ldr r1, [r2, #CI_CTRL] /* Fetch control register */ ;\ 225 ldr r2, .Laflt_cpufuncs ;\ 226 mov r0, #-1 ;\ 227 bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable AFLTs */ ;\ 228 adr lr, 3f ;\ 229 ldr pc, [r2, #CF_CONTROL] /* Set new CTRL reg value */ ;\ 230 2: mov r1, #0x00000000 ;\ 231 str r1, [r5] /* Clear astpending */ ;\ 232 msr cpsr_c, r4 /* Restore interrupts */ ;\ 233 mov r0, sp ;\ 234 bl _C_LABEL(ast) /* ast(frame) */ ;\ 235 orr r0, r4, #(I32_bit) /* Disable IRQs */ ;\ 236 msr cpsr_c, r0 ;\ 237 b 1b /* Back around again */ ;\ 238 3: 239 240 #else /* !EXEC_AOUT */ 241 242 #define AST_ALIGNMENT_FAULT_LOCALS ;\ 243 .Laflt_astpending: ;\ 244 .word _C_LABEL(astpending) 245 246 #define ENABLE_ALIGNMENT_FAULTS /* nothing */ 247 248 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 249 ldr r0, [sp] /* Get the SPSR from stack */ ;\ 250 mrs r4, cpsr /* save CPSR */ ;\ 251 orr r1, r4, #(I32_bit) ;\ 252 msr cpsr_c, r1 /* Disable interrupts */ ;\ 253 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ 254 teq r0, #(PSR_USR32_MODE) ;\ 255 ldreq r5, .Laflt_astpending ;\ 256 bne 2f /* Nope, get out now */ ;\ 257 bic r4, r4, #(I32_bit) ;\ 258 ldr r1, [r5] /* Pending AST? */ ;\ 259 teq r1, #0x00000000 ;\ 260 beq 2f /* Nope. Just bail */ ;\ 261 1: mov r1, #0x00000000 ;\ 262 str r1, [r5] /* Clear astpending */ ;\ 263 msr cpsr_c, r4 /* Restore interrupts */ ;\ 264 mov r0, sp ;\ 265 bl _C_LABEL(ast) /* ast(frame) */ ;\ 266 orr r0, r4, #(I32_bit) /* Disable IRQs */ ;\ 267 msr cpsr_c, r0 ;\ 268 ldr r1, [r5] /* Another pending AST? */ ;\ 269 teq r1, #0x00000000 ;\ 270 bne 1b /* Yup. Back around again */ ;\ 271 2: 272 #endif /* EXEC_AOUT */ 273 274 #ifdef ARM_LOCK_CAS_DEBUG 275 #define LOCK_CAS_DEBUG_LOCALS \ 276 .L_lock_cas_restart: ;\ 277 .word _C_LABEL(_lock_cas_restart) 278 279 #if defined(__ARMEB__) 280 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 281 ble 99f ;\ 282 ldr r0, .L_lock_cas_restart ;\ 283 ldmia r0, {r1-r2} /* load ev_count */ ;\ 284 adds r2, r2, #1 /* 64-bit incr (lo) */ ;\ 285 adc r1, r1, #0 /* 64-bit incr (hi) */ ;\ 286 stmia r0, {r1-r2} /* store ev_count */ 287 #else /* __ARMEB__ */ 288 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 289 ble 99f ;\ 290 ldr r0, .L_lock_cas_restart ;\ 291 ldmia r0, {r1-r2} /* load ev_count */ ;\ 292 adds r1, r1, #1 /* 64-bit incr (lo) */ ;\ 293 adc r2, r2, #0 /* 64-bit incr (hi) */ ;\ 294 stmia r0, {r1-r2} /* store ev_count */ 295 #endif /* __ARMEB__ */ 296 #else /* ARM_LOCK_CAS_DEBUG */ 297 #define LOCK_CAS_DEBUG_LOCALS /* nothing */ 298 #define LOCK_CAS_DEBUG_COUNT_RESTART /* nothing */ 299 #endif /* ARM_LOCK_CAS_DEBUG */ 300 301 #define LOCK_CAS_CHECK_LOCALS \ 302 .L_lock_cas: ;\ 303 .word _C_LABEL(_lock_cas) ;\ 304 .L_lock_cas_end: ;\ 305 .word _C_LABEL(_lock_cas_end) ;\ 306 LOCK_CAS_DEBUG_LOCALS 307 308 #define LOCK_CAS_CHECK \ 309 ldr r0, [sp] /* get saved PSR */ ;\ 310 and r0, r0, #(PSR_MODE) /* check for SVC32 mode */ ;\ 311 teq r0, #(PSR_SVC32_MODE) ;\ 312 bne 99f /* nope, get out now */ ;\ 313 ldr r0, [sp, #(IF_PC)] ;\ 314 ldr r1, .L_lock_cas_end ;\ 315 cmp r0, r1 ;\ 316 bge 99f ;\ 317 ldr r1, .L_lock_cas ;\ 318 cmp r0, r1 ;\ 319 strgt r1, [sp, #(IF_PC)] ;\ 320 LOCK_CAS_DEBUG_COUNT_RESTART ;\ 321 99: 322 323 /* 324 * ASM macros for pushing and pulling trapframes from the stack 325 * 326 * These macros are used to handle the irqframe and trapframe structures 327 * defined above. 328 */ 329 330 /* 331 * PUSHFRAME - macro to push a trap frame on the stack in the current mode 332 * Since the current mode is used, the SVC lr field is not defined. 333 * 334 * NOTE: r13 and r14 are stored separately as a work around for the 335 * SA110 rev 2 STM^ bug 336 */ 337 338 #define PUSHFRAME \ 339 str lr, [sp, #-4]!; /* Push the return address */ \ 340 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \ 341 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 342 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 343 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 344 mov r0, r0; /* NOP for previous instruction */ \ 345 mrs r0, spsr_all; /* Put the SPSR on the stack */ \ 346 str r0, [sp, #-4]! 347 348 /* 349 * PULLFRAME - macro to pull a trap frame from the stack in the current mode 350 * Since the current mode is used, the SVC lr field is ignored. 351 */ 352 353 #define PULLFRAME \ 354 ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \ 355 msr spsr_all, r0; \ 356 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 357 mov r0, r0; /* NOP for previous instruction */ \ 358 add sp, sp, #(4*17); /* Adjust the stack pointer */ \ 359 ldr lr, [sp], #0x0004 /* Pull the return address */ 360 361 /* 362 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode 363 * This should only be used if the processor is not currently in SVC32 364 * mode. The processor mode is switched to SVC mode and the trap frame is 365 * stored. The SVC lr field is used to store the previous value of 366 * lr in SVC mode. 367 * 368 * NOTE: r13 and r14 are stored separately as a work around for the 369 * SA110 rev 2 STM^ bug 370 */ 371 372 #define PUSHFRAMEINSVC \ 373 stmdb sp, {r0-r3}; /* Save 4 registers */ \ 374 mov r0, lr; /* Save xxx32 r14 */ \ 375 mov r1, sp; /* Save xxx32 sp */ \ 376 mrs r3, spsr; /* Save xxx32 spsr */ \ 377 mrs r2, cpsr; /* Get the CPSR */ \ 378 bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \ 379 orr r2, r2, #(PSR_SVC32_MODE); \ 380 msr cpsr_c, r2; /* Punch into SVC mode */ \ 381 mov r2, sp; /* Save SVC sp */ \ 382 str r0, [sp, #-4]!; /* Push return address */ \ 383 str lr, [sp, #-4]!; /* Push SVC lr */ \ 384 str r2, [sp, #-4]!; /* Push SVC sp */ \ 385 msr spsr_all, r3; /* Restore correct spsr */ \ 386 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ 387 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \ 388 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 389 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 390 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 391 mov r0, r0; /* NOP for previous instruction */ \ 392 mrs r0, spsr_all; /* Put the SPSR on the stack */ \ 393 str r0, [sp, #-4]! 394 395 /* 396 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack 397 * in SVC32 mode and restore the saved processor mode and PC. 398 * This should be used when the SVC lr register needs to be restored on 399 * exit. 400 */ 401 402 #define PULLFRAMEFROMSVCANDEXIT \ 403 ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \ 404 msr spsr_all, r0; /* restore SPSR */ \ 405 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 406 mov r0, r0; /* NOP for previous instruction */ \ 407 add sp, sp, #(4*15); /* Adjust the stack pointer */ \ 408 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ 409 410 #endif /* _LOCORE */ 411 412 #endif /* _ARM32_FRAME_H_ */ 413 414 /* End of frame.h */ 415
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