frame.h revision 1.16.6.2 1 /* $NetBSD: frame.h,v 1.16.6.2 2008/09/28 10:39:50 mjf Exp $ */
2
3 /*
4 * Copyright (c) 1994-1997 Mark Brinicombe.
5 * Copyright (c) 1994 Brini.
6 * All rights reserved.
7 *
8 * This code is derived from software written for Brini by Mark Brinicombe
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Brini.
21 * 4. The name of the company nor the name of the author may be used to
22 * endorse or promote products derived from this software without specific
23 * prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * RiscBSD kernel project
38 *
39 * frame.h
40 *
41 * Stack frames structures
42 *
43 * Created : 30/09/94
44 */
45
46 #ifndef _ARM32_FRAME_H_
47 #define _ARM32_FRAME_H_
48
49 #include <arm/frame.h> /* Common ARM stack frames */
50
51 #ifndef _LOCORE
52
53 /*
54 * System stack frames.
55 */
56
57 typedef struct irqframe {
58 unsigned int if_spsr;
59 unsigned int if_r0;
60 unsigned int if_r1;
61 unsigned int if_r2;
62 unsigned int if_r3;
63 unsigned int if_r4;
64 unsigned int if_r5;
65 unsigned int if_r6;
66 unsigned int if_r7;
67 unsigned int if_r8;
68 unsigned int if_r9;
69 unsigned int if_r10;
70 unsigned int if_r11;
71 unsigned int if_r12;
72 unsigned int if_usr_sp;
73 unsigned int if_usr_lr;
74 unsigned int if_svc_sp;
75 unsigned int if_svc_lr;
76 unsigned int if_pc;
77 } irqframe_t;
78
79 struct clockframe {
80 struct irqframe cf_if;
81 };
82
83 /*
84 * Switch frame.
85 *
86 * Should be a multiple of 8 bytes for dumpsys.
87 */
88
89 struct switchframe {
90 u_int sf_r4;
91 u_int sf_r5;
92 u_int sf_r6;
93 u_int sf_r7;
94 u_int sf_sp;
95 u_int sf_pc;
96 };
97
98 /*
99 * Stack frame. Used during stack traces (db_trace.c)
100 */
101 struct frame {
102 u_int fr_fp;
103 u_int fr_sp;
104 u_int fr_lr;
105 u_int fr_pc;
106 };
107
108 #ifdef _KERNEL
109 void validate_trapframe __P((trapframe_t *, int));
110 #endif /* _KERNEL */
111
112 #else /* _LOCORE */
113
114 #include "opt_compat_netbsd.h"
115 #include "opt_execfmt.h"
116 #include "opt_multiprocessor.h"
117 #include "opt_cpuoptions.h"
118 #include "opt_arm_debug.h"
119
120 #include <machine/cpu.h>
121
122 /*
123 * This macro is used by DO_AST_AND_RESTORE_ALIGNMENT_FAULTS to process
124 * any pending softints.
125 */
126 #ifdef __HAVE_FAST_SOFTINTS
127 #define DO_PENDING_SOFTINTS \
128 ldr r0, [r4, #CI_INTR_DEPTH]/* Get current intr depth */ ;\
129 teq r0, #0 /* Test for 0. */ ;\
130 beq 10f /* skip softints if != 0 */ ;\
131 ldr r0, [r4, #CI_CPL] /* Get current priority level */;\
132 ldr r0, [r4, #CI_CPL] /* Get current priority level */;\
133 ldr r1, [r4, #CI_SOFTINTS] /* Get pending softint mask */ ;\
134 mov r0, r1, lsr r0 /* shift mask by cpl */ ;\
135 beq 10f ;\
136 bl _C_LABEL(dosoftints) /* dosoftints(void) */ ;\
137 10:
138 #else
139 #define DO_PENDING_SOFTINTS /* nothing */
140 #endif
141
142 /*
143 * AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS
144 * These are used in order to support dynamic enabling/disabling of
145 * alignment faults when executing old a.out ARM binaries.
146 *
147 * Note that when ENABLE_ALIGNMENTS_FAULTS finishes r4 will contain
148 * pointer to the cpu's cpu_info. DO_AST_AND_RESTORE_ALIGNMENT_FAULTS
149 * relies on r4 being preserved.
150 */
151 #ifdef EXEC_AOUT
152 #if defined(PROCESS_ID_IS_CURLWP) || defined(PROCESS_ID_IS_CURCPU)
153
154 #define AST_ALIGNMENT_FAULT_LOCALS \
155 .Laflt_cpufuncs: ;\
156 .word _C_LABEL(cpufuncs)
157
158 #elif !defined(MULTIPROCESSOR)
159
160 /*
161 * Local variables needed by the AST/Alignment Fault macroes
162 */
163 #define AST_ALIGNMENT_FAULT_LOCALS \
164 .Laflt_cpufuncs: ;\
165 .word _C_LABEL(cpufuncs) ;\
166 .Laflt_cpu_info_store: ;\
167 .word _C_LABEL(cpu_info_store)
168
169 #define GET_CURCPU(rX) \
170 ldr rX, .Laflt_cpu_info_store
171
172 #else /* !MULTIPROCESSOR */
173
174 #define AST_ALIGNMENT_FAULT_LOCALS \
175 .Laflt_cpufuncs: ;\
176 .word _C_LABEL(cpufuncs) ;\
177 .Laflt_cpu_info: ;\
178 .word _C_LABEL(cpu_info)
179
180 #define GET_CURCPU(rX) \
181 ldr rX, .Laflt_cpu_info ;\
182 bl _C_LABEL(cpu_number) ;\
183 ldr r0, [rX, r0, lsl #2]
184
185 #endif /* MULTIPROCESSOR */
186
187 /*
188 * This macro must be invoked following PUSHFRAMEINSVC or PUSHFRAME at
189 * the top of interrupt/exception handlers.
190 *
191 * When invoked, r0 *must* contain the value of SPSR on the current
192 * trap/interrupt frame. This is always the case if ENABLE_ALIGNMENT_FAULTS
193 * is invoked immediately after PUSHFRAMEINSVC or PUSHFRAME.
194 */
195 #define ENABLE_ALIGNMENT_FAULTS \
196 and r0, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\
197 teq r0, #(PSR_USR32_MODE) ;\
198 GET_CURCPU(r4) /* r4 = cpuinfo */ ;\
199 bne 1f /* Not USR mode skip AFLT */ ;\
200 ldr r1, [r4, #CI_CURPCB] /* get curpcb from cpu_info */ ;\
201 ldr r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\
202 tst r1, #PCB_NOALIGNFLT ;\
203 beq 1f /* AFLTs already enabled */ ;\
204 ldr r2, .Laflt_cpufuncs ;\
205 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\
206 mov r0, #-1 ;\
207 mov lr, pc ;\
208 ldr pc, [r2, #CF_CONTROL] /* Enable alignment faults */ ;\
209 1:
210
211 /*
212 * This macro must be invoked just before PULLFRAMEFROMSVCANDEXIT or
213 * PULLFRAME at the end of interrupt/exception handlers. We know that
214 * r4 points to cpu_info since that is what ENABLE_ALIGNMENT_FAULTS did
215 * for use.
216 */
217 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \
218 DO_PENDING_SOFTINTS ;\
219 ldr r0, [sp] /* Get the SPSR from stack */ ;\
220 mrs r5, cpsr /* save CPSR */ ;\
221 orr r1, r5, #(IF32_bits) ;\
222 msr cpsr_c, r1 /* Disable interrupts */ ;\
223 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\
224 teq r0, #(PSR_USR32_MODE) ;\
225 bne 3f /* Nope, get out now */ ;\
226 1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\
227 teq r1, #0x00000000 ;\
228 bne 2f /* Yup. Go deal with it */ ;\
229 ldr r1, [r4, #CI_CURPCB] /* Get current PCB */ ;\
230 ldr r0, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\
231 tst r0, #PCB_NOALIGNFLT ;\
232 beq 3f /* Keep AFLTs enabled */ ;\
233 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\
234 ldr r2, .Laflt_cpufuncs ;\
235 mov r0, #-1 ;\
236 bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable AFLTs */ ;\
237 adr lr, 3f ;\
238 ldr pc, [r2, #CF_CONTROL] /* Set new CTRL reg value */ ;\
239 /* NOTREACHED */ \
240 2: mov r1, #0x00000000 ;\
241 str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\
242 bic r5, r5, #(IF32_bits) ;\
243 msr cpsr_c, r5 /* Restore interrupts */ ;\
244 mov r0, sp ;\
245 bl _C_LABEL(ast) /* ast(frame) */ ;\
246 orr r0, r5, #(IF32_bits) /* Disable IRQs */ ;\
247 msr cpsr_c, r0 ;\
248 b 1b /* Back around again */ ;\
249 3:
250
251 #else /* !EXEC_AOUT */
252
253 #if defined(PROCESS_ID_IS_CURLWP) || defined(PROCESS_ID_IS_CURCPU)
254 #define AST_ALIGNMENT_FAULT_LOCALS
255
256 #elif !defined(MULTIPROCESSOR)
257 #define AST_ALIGNMENT_FAULT_LOCALS \
258 .Laflt_cpu_info_store: ;\
259 .word _C_LABEL(cpu_info_store)
260
261 #define GET_CURCPU(rX) \
262 ldr rX, .Laflt_cpu_info_store
263
264 #else
265 #define AST_ALIGNMENT_FAULT_LOCALS \
266 .Laflt_cpu_info: ;\
267 .word _C_LABEL(cpu_info)
268
269 #define GET_CURCPU(rX) \
270 bl _C_LABEL(cpu_number) ;\
271 ldr r1, .Laflt_cpu_info ;\
272 ldr rX, [r1, r0, lsl #2]
273
274 #endif
275
276 #define ENABLE_ALIGNMENT_FAULTS GET_CURCPU(r4)
277
278 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \
279 DO_PENDING_SOFTINTS ;\
280 ldr r0, [sp] /* Get the SPSR from stack */ ;\
281 mrs r5, cpsr /* save CPSR */ ;\
282 orr r1, r5, #(IF32_bits) ;\
283 msr cpsr_c, r1 /* Disable interrupts */ ;\
284 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\
285 teq r0, #(PSR_USR32_MODE) ;\
286 bne 2f /* Nope, get out now */ ;\
287 1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\
288 teq r1, #0x00000000 ;\
289 beq 2f /* Nope. Just bail */ ;\
290 mov r1, #0x00000000 ;\
291 str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\
292 bic r5, r5, #(IF32_bits) ;\
293 msr cpsr_c, r5 /* Restore interrupts */ ;\
294 mov r0, sp ;\
295 bl _C_LABEL(ast) /* ast(frame) */ ;\
296 orr r0, r5, #(IF32_bits) /* Disable IRQs */ ;\
297 msr cpsr_c, r0 ;\
298 b 1b ;\
299 2:
300 #endif /* EXEC_AOUT */
301
302 #ifdef ARM_LOCK_CAS_DEBUG
303 #define LOCK_CAS_DEBUG_LOCALS \
304 .L_lock_cas_restart: ;\
305 .word _C_LABEL(_lock_cas_restart)
306
307 #if defined(__ARMEB__)
308 #define LOCK_CAS_DEBUG_COUNT_RESTART \
309 ble 99f ;\
310 ldr r0, .L_lock_cas_restart ;\
311 ldmia r0, {r1-r2} /* load ev_count */ ;\
312 adds r2, r2, #1 /* 64-bit incr (lo) */ ;\
313 adc r1, r1, #0 /* 64-bit incr (hi) */ ;\
314 stmia r0, {r1-r2} /* store ev_count */
315 #else /* __ARMEB__ */
316 #define LOCK_CAS_DEBUG_COUNT_RESTART \
317 ble 99f ;\
318 ldr r0, .L_lock_cas_restart ;\
319 ldmia r0, {r1-r2} /* load ev_count */ ;\
320 adds r1, r1, #1 /* 64-bit incr (lo) */ ;\
321 adc r2, r2, #0 /* 64-bit incr (hi) */ ;\
322 stmia r0, {r1-r2} /* store ev_count */
323 #endif /* __ARMEB__ */
324 #else /* ARM_LOCK_CAS_DEBUG */
325 #define LOCK_CAS_DEBUG_LOCALS /* nothing */
326 #define LOCK_CAS_DEBUG_COUNT_RESTART /* nothing */
327 #endif /* ARM_LOCK_CAS_DEBUG */
328
329 #define LOCK_CAS_CHECK_LOCALS \
330 .L_lock_cas: ;\
331 .word _C_LABEL(_lock_cas) ;\
332 .L_lock_cas_end: ;\
333 .word _C_LABEL(_lock_cas_end) ;\
334 LOCK_CAS_DEBUG_LOCALS
335
336 #define LOCK_CAS_CHECK \
337 ldr r0, [sp] /* get saved PSR */ ;\
338 and r0, r0, #(PSR_MODE) /* check for SVC32 mode */ ;\
339 teq r0, #(PSR_SVC32_MODE) ;\
340 bne 99f /* nope, get out now */ ;\
341 ldr r0, [sp, #(IF_PC)] ;\
342 ldr r1, .L_lock_cas_end ;\
343 cmp r0, r1 ;\
344 bge 99f ;\
345 ldr r1, .L_lock_cas ;\
346 cmp r0, r1 ;\
347 strgt r1, [sp, #(IF_PC)] ;\
348 LOCK_CAS_DEBUG_COUNT_RESTART ;\
349 99:
350
351 /*
352 * ASM macros for pushing and pulling trapframes from the stack
353 *
354 * These macros are used to handle the irqframe and trapframe structures
355 * defined above.
356 */
357
358 /*
359 * PUSHFRAME - macro to push a trap frame on the stack in the current mode
360 * Since the current mode is used, the SVC lr field is not defined.
361 *
362 * NOTE: r13 and r14 are stored separately as a work around for the
363 * SA110 rev 2 STM^ bug
364 */
365
366 #define PUSHFRAME \
367 str lr, [sp, #-4]!; /* Push the return address */ \
368 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \
369 stmia sp, {r0-r12}; /* Push the user mode registers */ \
370 add r0, sp, #(4*13); /* Adjust the stack pointer */ \
371 stmia r0, {r13-r14}^; /* Push the user mode registers */ \
372 mov r0, r0; /* NOP for previous instruction */ \
373 mrs r0, spsr_all; /* Put the SPSR on the stack */ \
374 str r0, [sp, #-4]!
375
376 /*
377 * PULLFRAME - macro to pull a trap frame from the stack in the current mode
378 * Since the current mode is used, the SVC lr field is ignored.
379 */
380
381 #define PULLFRAME \
382 ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \
383 msr spsr_all, r0; \
384 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
385 mov r0, r0; /* NOP for previous instruction */ \
386 add sp, sp, #(4*17); /* Adjust the stack pointer */ \
387 ldr lr, [sp], #0x0004 /* Pull the return address */
388
389 /*
390 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode
391 * This should only be used if the processor is not currently in SVC32
392 * mode. The processor mode is switched to SVC mode and the trap frame is
393 * stored. The SVC lr field is used to store the previous value of
394 * lr in SVC mode.
395 *
396 * NOTE: r13 and r14 are stored separately as a work around for the
397 * SA110 rev 2 STM^ bug
398 */
399
400 #define PUSHFRAMEINSVC \
401 stmdb sp, {r0-r3}; /* Save 4 registers */ \
402 mov r0, lr; /* Save xxx32 r14 */ \
403 mov r1, sp; /* Save xxx32 sp */ \
404 mrs r3, spsr; /* Save xxx32 spsr */ \
405 mrs r2, cpsr; /* Get the CPSR */ \
406 bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \
407 orr r2, r2, #(PSR_SVC32_MODE); \
408 msr cpsr_c, r2; /* Punch into SVC mode */ \
409 mov r2, sp; /* Save SVC sp */ \
410 str r0, [sp, #-4]!; /* Push return address */ \
411 str lr, [sp, #-4]!; /* Push SVC lr */ \
412 str r2, [sp, #-4]!; /* Push SVC sp */ \
413 msr spsr_all, r3; /* Restore correct spsr */ \
414 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \
415 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \
416 stmia sp, {r0-r12}; /* Push the user mode registers */ \
417 add r0, sp, #(4*13); /* Adjust the stack pointer */ \
418 stmia r0, {r13-r14}^; /* Push the user mode registers */ \
419 mov r0, r0; /* NOP for previous instruction */ \
420 mrs r0, spsr_all; /* Put the SPSR on the stack */ \
421 str r0, [sp, #-4]!
422
423 /*
424 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack
425 * in SVC32 mode and restore the saved processor mode and PC.
426 * This should be used when the SVC lr register needs to be restored on
427 * exit.
428 */
429
430 #define PULLFRAMEFROMSVCANDEXIT \
431 ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \
432 msr spsr_all, r0; /* restore SPSR */ \
433 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \
434 mov r0, r0; /* NOP for previous instruction */ \
435 add sp, sp, #(4*15); /* Adjust the stack pointer */ \
436 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */
437
438 #endif /* _LOCORE */
439
440 #endif /* _ARM32_FRAME_H_ */
441