frame.h revision 1.17
1 /* $NetBSD: frame.h,v 1.17 2008/04/27 18:58:44 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1997 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * frame.h 40 * 41 * Stack frames structures 42 * 43 * Created : 30/09/94 44 */ 45 46 #ifndef _ARM32_FRAME_H_ 47 #define _ARM32_FRAME_H_ 48 49 #include <arm/frame.h> /* Common ARM stack frames */ 50 51 #ifndef _LOCORE 52 53 /* 54 * System stack frames. 55 */ 56 57 typedef struct irqframe { 58 unsigned int if_spsr; 59 unsigned int if_r0; 60 unsigned int if_r1; 61 unsigned int if_r2; 62 unsigned int if_r3; 63 unsigned int if_r4; 64 unsigned int if_r5; 65 unsigned int if_r6; 66 unsigned int if_r7; 67 unsigned int if_r8; 68 unsigned int if_r9; 69 unsigned int if_r10; 70 unsigned int if_r11; 71 unsigned int if_r12; 72 unsigned int if_usr_sp; 73 unsigned int if_usr_lr; 74 unsigned int if_svc_sp; 75 unsigned int if_svc_lr; 76 unsigned int if_pc; 77 } irqframe_t; 78 79 struct clockframe { 80 struct irqframe cf_if; 81 }; 82 83 /* 84 * Switch frame. 85 * 86 * Should be a multiple of 8 bytes for dumpsys. 87 */ 88 89 struct switchframe { 90 u_int sf_r4; 91 u_int sf_r5; 92 u_int sf_r6; 93 u_int sf_r7; 94 u_int sf_sp; 95 u_int sf_pc; 96 }; 97 98 /* 99 * Stack frame. Used during stack traces (db_trace.c) 100 */ 101 struct frame { 102 u_int fr_fp; 103 u_int fr_sp; 104 u_int fr_lr; 105 u_int fr_pc; 106 }; 107 108 #ifdef _KERNEL 109 void validate_trapframe __P((trapframe_t *, int)); 110 #endif /* _KERNEL */ 111 112 #else /* _LOCORE */ 113 114 #include "opt_compat_netbsd.h" 115 #include "opt_execfmt.h" 116 #include "opt_multiprocessor.h" 117 #include "opt_cpuoptions.h" 118 #include "opt_arm_debug.h" 119 120 #include <machine/cpu.h> 121 122 /* 123 * AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS 124 * These are used in order to support dynamic enabling/disabling of 125 * alignment faults when executing old a.out ARM binaries. 126 * 127 * Note that when ENABLE_ALIGNMENTS_FAULTS finishes r4 will contain 128 * pointer to the cpu's cpu_info. DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 129 * relies on r4 being preserved. 130 */ 131 #ifdef EXEC_AOUT 132 #if defined(PROCESS_ID_IS_CURLWP) || defined(PROCESS_ID_IS_CURCPU) 133 134 #define AST_ALIGNMENT_FAULT_LOCALS \ 135 .Laflt_cpufuncs: ;\ 136 .word _C_LABEL(cpufuncs) 137 138 #elif !defined(MULTIPROCESSOR) 139 140 /* 141 * Local variables needed by the AST/Alignment Fault macroes 142 */ 143 #define AST_ALIGNMENT_FAULT_LOCALS \ 144 .Laflt_cpufuncs: ;\ 145 .word _C_LABEL(cpufuncs) ;\ 146 .Laflt_cpu_info_store: ;\ 147 .word _C_LABEL(cpu_info_store) 148 149 #define GET_CURCPU(rX) \ 150 ldr rX, .Laflt_cpu_info_store 151 152 #else /* !MULTIPROCESSOR */ 153 154 #define AST_ALIGNMENT_FAULT_LOCALS \ 155 .Laflt_cpufuncs: ;\ 156 .word _C_LABEL(cpufuncs) ;\ 157 .Laflt_cpu_info: ;\ 158 .word _C_LABEL(cpu_info) 159 160 #define GET_CURCPU(rX) \ 161 ldr rX, .Laflt_cpu_info ;\ 162 bl _C_LABEL(cpu_number) ;\ 163 ldr r0, [rX, r0, lsl #2] 164 165 #endif /* MULTIPROCESSOR */ 166 167 /* 168 * This macro must be invoked following PUSHFRAMEINSVC or PUSHFRAME at 169 * the top of interrupt/exception handlers. 170 * 171 * When invoked, r0 *must* contain the value of SPSR on the current 172 * trap/interrupt frame. This is always the case if ENABLE_ALIGNMENT_FAULTS 173 * is invoked immediately after PUSHFRAMEINSVC or PUSHFRAME. 174 */ 175 #define ENABLE_ALIGNMENT_FAULTS \ 176 and r0, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\ 177 teq r0, #(PSR_USR32_MODE) ;\ 178 GET_CURCPU(r4) /* r4 = cpuinfo */ ;\ 179 bne 1f /* Not USR mode skip AFLT */ ;\ 180 ldr r1, [r4, #CI_CURPCB] /* get curpcb from cpu_info */ ;\ 181 ldr r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\ 182 tst r1, #PCB_NOALIGNFLT ;\ 183 beq 1f /* AFLTs already enabled */ ;\ 184 ldr r2, .Laflt_cpufuncs ;\ 185 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\ 186 mov r0, #-1 ;\ 187 mov lr, pc ;\ 188 ldr pc, [r2, #CF_CONTROL] /* Enable alignment faults */ ;\ 189 1: 190 191 /* 192 * This macro must be invoked just before PULLFRAMEFROMSVCANDEXIT or 193 * PULLFRAME at the end of interrupt/exception handlers. We know that 194 * r4 points to cpu_info since that is what ENABLE_ALIGNMENT_FAULTS did 195 * for use. 196 */ 197 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 198 ldr r0, [sp] /* Get the SPSR from stack */ ;\ 199 mrs r5, cpsr /* save CPSR */ ;\ 200 orr r1, r5, #(I32_bit) ;\ 201 msr cpsr_c, r1 /* Disable interrupts */ ;\ 202 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ 203 teq r0, #(PSR_USR32_MODE) ;\ 204 bne 3f /* Nope, get out now */ ;\ 205 1: ldr r0, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\ 206 teq r0, #0x00000000 ;\ 207 bne 2f /* Yup. Go deal with it */ ;\ 208 ldr r1, [r4, #CI_CURPCB] /* Get current PCB */ ;\ 209 ldr r0, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\ 210 tst r0, #PCB_NOALIGNFLT ;\ 211 beq 3f /* Keep AFLTs enabled */ ;\ 212 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\ 213 ldr r2, .Laflt_cpufuncs ;\ 214 mov r0, #-1 ;\ 215 bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable AFLTs */ ;\ 216 adr lr, 3f ;\ 217 ldr pc, [r2, #CF_CONTROL] /* Set new CTRL reg value */ ;\ 218 /* NOTREACHED */ \ 219 2: mov r1, #0x00000000 ;\ 220 str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\ 221 bic r5, r5, #(I32_bit) ;\ 222 msr cpsr_c, r5 /* Restore interrupts */ ;\ 223 mov r0, sp ;\ 224 bl _C_LABEL(ast) /* ast(frame) */ ;\ 225 orr r0, r5, #(I32_bit) /* Disable IRQs */ ;\ 226 msr cpsr_c, r0 ;\ 227 b 1b /* Back around again */ ;\ 228 3: 229 230 #else /* !EXEC_AOUT */ 231 232 #if defined(PROCESS_ID_IS_CURLWP) || defined(PROCESS_ID_IS_CURCPU) 233 #define AST_ALIGNMENT_FAULT_LOCALS 234 235 #elif !defined(MULTIPROCESSOR) 236 #define AST_ALIGNMENT_FAULT_LOCALS \ 237 .Laflt_cpu_info_store: ;\ 238 .word _C_LABEL(cpu_info_store) 239 240 #define GET_CURCPU(rX) \ 241 ldr rX, .Laflt_cpu_info_store 242 243 #else 244 #define AST_ALIGNMENT_FAULT_LOCALS \ 245 .Laflt_cpu_info: ;\ 246 .word _C_LABEL(cpu_info) 247 248 #define GET_CURCPU(rX) \ 249 bl _C_LABEL(cpu_number) ;\ 250 ldr r1, .Laflt_cpu_info ;\ 251 ldr rX, [r1, r0, lsl #2] 252 253 #endif 254 255 #define ENABLE_ALIGNMENT_FAULTS GET_CURCPU(r4) 256 257 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 258 ldr r0, [sp] /* Get the SPSR from stack */ ;\ 259 mrs r5, cpsr /* save CPSR */ ;\ 260 orr r1, r5, #(I32_bit) ;\ 261 msr cpsr_c, r1 /* Disable interrupts */ ;\ 262 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ 263 teq r0, #(PSR_USR32_MODE) ;\ 264 bne 2f /* Nope, get out now */ ;\ 265 1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\ 266 teq r1, #0x00000000 ;\ 267 beq 2f /* Nope. Just bail */ ;\ 268 mov r1, #0x00000000 ;\ 269 str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\ 270 bic r5, r5, #(I32_bit) ;\ 271 msr cpsr_c, r5 /* Restore interrupts */ ;\ 272 mov r0, sp ;\ 273 bl _C_LABEL(ast) /* ast(frame) */ ;\ 274 orr r0, r5, #(I32_bit) /* Disable IRQs */ ;\ 275 msr cpsr_c, r0 ;\ 276 b 1b ;\ 277 2: 278 #endif /* EXEC_AOUT */ 279 280 #ifdef ARM_LOCK_CAS_DEBUG 281 #define LOCK_CAS_DEBUG_LOCALS \ 282 .L_lock_cas_restart: ;\ 283 .word _C_LABEL(_lock_cas_restart) 284 285 #if defined(__ARMEB__) 286 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 287 ble 99f ;\ 288 ldr r0, .L_lock_cas_restart ;\ 289 ldmia r0, {r1-r2} /* load ev_count */ ;\ 290 adds r2, r2, #1 /* 64-bit incr (lo) */ ;\ 291 adc r1, r1, #0 /* 64-bit incr (hi) */ ;\ 292 stmia r0, {r1-r2} /* store ev_count */ 293 #else /* __ARMEB__ */ 294 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 295 ble 99f ;\ 296 ldr r0, .L_lock_cas_restart ;\ 297 ldmia r0, {r1-r2} /* load ev_count */ ;\ 298 adds r1, r1, #1 /* 64-bit incr (lo) */ ;\ 299 adc r2, r2, #0 /* 64-bit incr (hi) */ ;\ 300 stmia r0, {r1-r2} /* store ev_count */ 301 #endif /* __ARMEB__ */ 302 #else /* ARM_LOCK_CAS_DEBUG */ 303 #define LOCK_CAS_DEBUG_LOCALS /* nothing */ 304 #define LOCK_CAS_DEBUG_COUNT_RESTART /* nothing */ 305 #endif /* ARM_LOCK_CAS_DEBUG */ 306 307 #define LOCK_CAS_CHECK_LOCALS \ 308 .L_lock_cas: ;\ 309 .word _C_LABEL(_lock_cas) ;\ 310 .L_lock_cas_end: ;\ 311 .word _C_LABEL(_lock_cas_end) ;\ 312 LOCK_CAS_DEBUG_LOCALS 313 314 #define LOCK_CAS_CHECK \ 315 ldr r0, [sp] /* get saved PSR */ ;\ 316 and r0, r0, #(PSR_MODE) /* check for SVC32 mode */ ;\ 317 teq r0, #(PSR_SVC32_MODE) ;\ 318 bne 99f /* nope, get out now */ ;\ 319 ldr r0, [sp, #(IF_PC)] ;\ 320 ldr r1, .L_lock_cas_end ;\ 321 cmp r0, r1 ;\ 322 bge 99f ;\ 323 ldr r1, .L_lock_cas ;\ 324 cmp r0, r1 ;\ 325 strgt r1, [sp, #(IF_PC)] ;\ 326 LOCK_CAS_DEBUG_COUNT_RESTART ;\ 327 99: 328 329 /* 330 * ASM macros for pushing and pulling trapframes from the stack 331 * 332 * These macros are used to handle the irqframe and trapframe structures 333 * defined above. 334 */ 335 336 /* 337 * PUSHFRAME - macro to push a trap frame on the stack in the current mode 338 * Since the current mode is used, the SVC lr field is not defined. 339 * 340 * NOTE: r13 and r14 are stored separately as a work around for the 341 * SA110 rev 2 STM^ bug 342 */ 343 344 #define PUSHFRAME \ 345 str lr, [sp, #-4]!; /* Push the return address */ \ 346 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \ 347 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 348 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 349 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 350 mov r0, r0; /* NOP for previous instruction */ \ 351 mrs r0, spsr_all; /* Put the SPSR on the stack */ \ 352 str r0, [sp, #-4]! 353 354 /* 355 * PULLFRAME - macro to pull a trap frame from the stack in the current mode 356 * Since the current mode is used, the SVC lr field is ignored. 357 */ 358 359 #define PULLFRAME \ 360 ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \ 361 msr spsr_all, r0; \ 362 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 363 mov r0, r0; /* NOP for previous instruction */ \ 364 add sp, sp, #(4*17); /* Adjust the stack pointer */ \ 365 ldr lr, [sp], #0x0004 /* Pull the return address */ 366 367 /* 368 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode 369 * This should only be used if the processor is not currently in SVC32 370 * mode. The processor mode is switched to SVC mode and the trap frame is 371 * stored. The SVC lr field is used to store the previous value of 372 * lr in SVC mode. 373 * 374 * NOTE: r13 and r14 are stored separately as a work around for the 375 * SA110 rev 2 STM^ bug 376 */ 377 378 #define PUSHFRAMEINSVC \ 379 stmdb sp, {r0-r3}; /* Save 4 registers */ \ 380 mov r0, lr; /* Save xxx32 r14 */ \ 381 mov r1, sp; /* Save xxx32 sp */ \ 382 mrs r3, spsr; /* Save xxx32 spsr */ \ 383 mrs r2, cpsr; /* Get the CPSR */ \ 384 bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \ 385 orr r2, r2, #(PSR_SVC32_MODE); \ 386 msr cpsr_c, r2; /* Punch into SVC mode */ \ 387 mov r2, sp; /* Save SVC sp */ \ 388 str r0, [sp, #-4]!; /* Push return address */ \ 389 str lr, [sp, #-4]!; /* Push SVC lr */ \ 390 str r2, [sp, #-4]!; /* Push SVC sp */ \ 391 msr spsr_all, r3; /* Restore correct spsr */ \ 392 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ 393 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \ 394 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 395 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 396 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 397 mov r0, r0; /* NOP for previous instruction */ \ 398 mrs r0, spsr_all; /* Put the SPSR on the stack */ \ 399 str r0, [sp, #-4]! 400 401 /* 402 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack 403 * in SVC32 mode and restore the saved processor mode and PC. 404 * This should be used when the SVC lr register needs to be restored on 405 * exit. 406 */ 407 408 #define PULLFRAMEFROMSVCANDEXIT \ 409 ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \ 410 msr spsr_all, r0; /* restore SPSR */ \ 411 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 412 mov r0, r0; /* NOP for previous instruction */ \ 413 add sp, sp, #(4*15); /* Adjust the stack pointer */ \ 414 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ 415 416 #endif /* _LOCORE */ 417 418 #endif /* _ARM32_FRAME_H_ */ 419
Indexes created Thu Sep 25 16:09:42 GMT 2025