frame.h revision 1.20.8.1
1 /* $NetBSD: frame.h,v 1.20.8.1 2014/02/15 16:18:36 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1997 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * frame.h 40 * 41 * Stack frames structures 42 * 43 * Created : 30/09/94 44 */ 45 46 #ifndef _ARM32_FRAME_H_ 47 #define _ARM32_FRAME_H_ 48 49 #include <arm/frame.h> /* Common ARM stack frames */ 50 51 #ifndef _LOCORE 52 53 /* 54 * Switch frame. 55 * 56 * Should be a multiple of 8 bytes for dumpsys. 57 */ 58 59 struct switchframe { 60 u_int sf_r4; 61 u_int sf_r5; 62 u_int sf_r6; 63 u_int sf_r7; 64 u_int sf_sp; 65 u_int sf_pc; 66 }; 67 68 /* 69 * Stack frame. Used during stack traces (db_trace.c) 70 */ 71 struct frame { 72 u_int fr_fp; 73 u_int fr_sp; 74 u_int fr_lr; 75 u_int fr_pc; 76 }; 77 78 #ifdef _KERNEL 79 void validate_trapframe(trapframe_t *, int); 80 #endif /* _KERNEL */ 81 82 #else /* _LOCORE */ 83 84 #include "opt_compat_netbsd.h" 85 #include "opt_execfmt.h" 86 #include "opt_multiprocessor.h" 87 #include "opt_cpuoptions.h" 88 #include "opt_arm_debug.h" 89 #include "opt_cputypes.h" 90 91 #include <arm/locore.h> 92 93 /* 94 * This macro is used by DO_AST_AND_RESTORE_ALIGNMENT_FAULTS to process 95 * any pending softints. 96 */ 97 #ifdef _ARM_ARCH_4T 98 #define B_CF_CONTROL(rX) ;\ 99 ldr ip, [rX, #CF_CONTROL] /* get function addr */ ;\ 100 bx ip /* branch to cpu_control */ 101 #else 102 #define B_CF_CONTROL(rX) ;\ 103 ldr pc, [rX, #CF_CONTROL] /* branch to cpu_control */ 104 #endif 105 #ifdef _ARM_ARCH_5T 106 #define BL_CF_CONTROL(rX) ;\ 107 ldr ip, [rX, #CF_CONTROL] /* get function addr */ ;\ 108 blx ip /* call cpu_control */ 109 #else 110 #define BL_CF_CONTROL(rX) ;\ 111 mov lr, pc ;\ 112 ldr pc, [rX, #CF_CONTROL] /* call cpu_control */ 113 #endif 114 #if defined(__HAVE_FAST_SOFTINTS) && !defined(__HAVE_PIC_FAST_SOFTINTS) 115 #define DO_PENDING_SOFTINTS \ 116 ldr r0, [r4, #CI_INTR_DEPTH]/* Get current intr depth */ ;\ 117 cmp r0, #0 /* Test for 0. */ ;\ 118 bne 10f /* skip softints if != 0 */ ;\ 119 ldr r0, [r4, #CI_CPL] /* Get current priority level */;\ 120 ldr r1, [r4, #CI_SOFTINTS] /* Get pending softint mask */ ;\ 121 lsrs r0, r1, r0 /* shift mask by cpl */ ;\ 122 blne _C_LABEL(dosoftints) /* dosoftints(void) */ ;\ 123 10: 124 #else 125 #define DO_PENDING_SOFTINTS /* nothing */ 126 #endif 127 128 #ifdef MULTIPROCESSOR 129 #define KERNEL_LOCK \ 130 mov r0, #1 ;\ 131 mov r1, #0 ;\ 132 bl _C_LABEL(_kernel_lock) 133 134 #define KERNEL_UNLOCK \ 135 mov r0, #1 ;\ 136 mov r1, #0 ;\ 137 mov r2, #0 ;\ 138 bl _C_LABEL(_kernel_unlock) 139 #else 140 #define KERNEL_LOCK /* nothing */ 141 #define KERNEL_UNLOCK /* nothing */ 142 #endif 143 144 #ifdef _ARM_ARCH_6 145 #define GET_CPSR(rb) /* nothing */ 146 #define CPSID_I(ra,rb) cpsid i 147 #define CPSIE_I(ra,rb) cpsie i 148 #else 149 #define GET_CPSR(rb) \ 150 mrs rb, cpsr /* fetch CPSR */ 151 152 #define CPSID_I(ra,rb) \ 153 orr ra, rb, #(IF32_bits) ;\ 154 msr cpsr_c, ra /* Disable interrupts */ 155 156 #define CPSIE_I(ra,rb) \ 157 bic ra, rb, #(IF32_bits) ;\ 158 msr cpsr_c, ra /* Restore interrupts */ 159 #endif 160 161 /* 162 * AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS 163 * These are used in order to support dynamic enabling/disabling of 164 * alignment faults when executing old a.out ARM binaries. 165 * 166 * Note that when ENABLE_ALIGNMENTS_FAULTS finishes r4 will contain 167 * pointer to the cpu's cpu_info. DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 168 * relies on r4 being preserved. 169 */ 170 #ifdef EXEC_AOUT 171 #define AST_ALIGNMENT_FAULT_LOCALS \ 172 .Laflt_cpufuncs: ;\ 173 .word _C_LABEL(cpufuncs) 174 175 /* 176 * This macro must be invoked following PUSHFRAMEINSVC or PUSHFRAME at 177 * the top of interrupt/exception handlers. 178 * 179 * When invoked, r0 *must* contain the value of SPSR on the current 180 * trap/interrupt frame. This is always the case if ENABLE_ALIGNMENT_FAULTS 181 * is invoked immediately after PUSHFRAMEINSVC or PUSHFRAME. 182 */ 183 #define ENABLE_ALIGNMENT_FAULTS \ 184 and r7, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\ 185 teq r7, #(PSR_USR32_MODE) ;\ 186 GET_CURCPU(r4) /* r4 = cpuinfo */ ;\ 187 bne 1f /* Not USR mode skip AFLT */ ;\ 188 ldr r1, [r4, #CI_CURLWP] /* get curlwp from cpu_info */ ;\ 189 ldr r1, [r1, #L_MD_FLAGS] /* Fetch l_md.md_flags */ ;\ 190 tst r1, #MDLWP_NOALIGNFLT ;\ 191 beq 1f /* AFLTs already enabled */ ;\ 192 ldr r2, .Laflt_cpufuncs ;\ 193 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\ 194 mov r0, #-1 ;\ 195 BL_CF_CONTROL(r2) /* Enable alignment faults */ ;\ 196 1: KERNEL_LOCK 197 198 /* 199 * This macro must be invoked just before PULLFRAMEFROMSVCANDEXIT or 200 * PULLFRAME at the end of interrupt/exception handlers. We know that 201 * r4 points to cpu_info since that is what ENABLE_ALIGNMENT_FAULTS did 202 * for use. 203 */ 204 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 205 DO_PENDING_SOFTINTS ;\ 206 GET_CPSR(r5) /* save CPSR */ ;\ 207 CPSID_I(r1, r5) /* Disable interrupts */ ;\ 208 teq r7, #(PSR_USR32_MODE) /* Returning to USR mode? */ ;\ 209 bne 3f /* Nope, get out now */ ;\ 210 1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\ 211 teq r1, #0x00000000 ;\ 212 bne 2f /* Yup. Go deal with it */ ;\ 213 ldr r1, [r4, #CI_CURLWP] /* get curlwp from cpu_info */ ;\ 214 ldr r0, [r1, #L_MD_FLAGS] /* get md_flags from lwp */ ;\ 215 tst r0, #MDLWP_NOALIGNFLT ;\ 216 beq 3f /* Keep AFLTs enabled */ ;\ 217 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\ 218 ldr r2, .Laflt_cpufuncs ;\ 219 mov r0, #-1 ;\ 220 bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable AFLTs */ ;\ 221 adr lr, 3f ;\ 222 B_CF_CONTROL(r2) /* Set new CTRL reg value */ ;\ 223 /* NOTREACHED */ \ 224 2: mov r1, #0x00000000 ;\ 225 str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\ 226 CPSIE_I(r5, r5) /* Restore interrupts */ ;\ 227 mov r0, sp ;\ 228 bl _C_LABEL(ast) /* ast(frame) */ ;\ 229 CPSID_I(r0, r5) /* Disable interrupts */ ;\ 230 b 1b /* Back around again */ ;\ 231 3: KERNEL_UNLOCK 232 233 #else /* !EXEC_AOUT */ 234 235 #define AST_ALIGNMENT_FAULT_LOCALS 236 237 #define ENABLE_ALIGNMENT_FAULTS \ 238 and r7, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\ 239 GET_CURCPU(r4) /* r4 = cpuinfo */ ;\ 240 KERNEL_LOCK 241 242 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 243 DO_PENDING_SOFTINTS ;\ 244 GET_CPSR(r5) /* save CPSR */ ;\ 245 CPSID_I(r1, r5) /* Disable interrupts */ ;\ 246 teq r7, #(PSR_USR32_MODE) ;\ 247 bne 2f /* Nope, get out now */ ;\ 248 1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\ 249 teq r1, #0x00000000 ;\ 250 beq 2f /* Nope. Just bail */ ;\ 251 mov r1, #0x00000000 ;\ 252 str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\ 253 CPSIE_I(r5, r5) /* Restore interrupts */ ;\ 254 mov r0, sp ;\ 255 bl _C_LABEL(ast) /* ast(frame) */ ;\ 256 CPSID_I(r0, r5) /* Disable interrupts */ ;\ 257 b 1b ;\ 258 2: KERNEL_UNLOCK /* unlock the kernel */ 259 #endif /* EXEC_AOUT */ 260 261 #ifndef _ARM_ARCH_6 262 #ifdef ARM_LOCK_CAS_DEBUG 263 #define LOCK_CAS_DEBUG_LOCALS \ 264 .L_lock_cas_restart: ;\ 265 .word _C_LABEL(_lock_cas_restart) 266 267 #if defined(__ARMEB__) 268 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 269 ble 99f ;\ 270 ldr r0, .L_lock_cas_restart ;\ 271 ldmia r0, {r1-r2} /* load ev_count */ ;\ 272 adds r2, r2, #1 /* 64-bit incr (lo) */ ;\ 273 adc r1, r1, #0 /* 64-bit incr (hi) */ ;\ 274 stmia r0, {r1-r2} /* store ev_count */ 275 #else /* __ARMEB__ */ 276 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 277 ble 99f ;\ 278 ldr r0, .L_lock_cas_restart ;\ 279 ldmia r0, {r1-r2} /* load ev_count */ ;\ 280 adds r1, r1, #1 /* 64-bit incr (lo) */ ;\ 281 adc r2, r2, #0 /* 64-bit incr (hi) */ ;\ 282 stmia r0, {r1-r2} /* store ev_count */ 283 #endif /* __ARMEB__ */ 284 #else /* ARM_LOCK_CAS_DEBUG */ 285 #define LOCK_CAS_DEBUG_LOCALS /* nothing */ 286 #define LOCK_CAS_DEBUG_COUNT_RESTART /* nothing */ 287 #endif /* ARM_LOCK_CAS_DEBUG */ 288 289 #define LOCK_CAS_CHECK_LOCALS \ 290 .L_lock_cas: ;\ 291 .word _C_LABEL(_lock_cas) ;\ 292 .L_lock_cas_end: ;\ 293 .word _C_LABEL(_lock_cas_end) ;\ 294 LOCK_CAS_DEBUG_LOCALS 295 296 #define LOCK_CAS_CHECK \ 297 ldr r0, [sp] /* get saved PSR */ ;\ 298 and r0, r0, #(PSR_MODE) /* check for SVC32 mode */ ;\ 299 teq r0, #(PSR_SVC32_MODE) ;\ 300 bne 99f /* nope, get out now */ ;\ 301 ldr r0, [sp, #(TF_PC)] ;\ 302 ldr r1, .L_lock_cas_end ;\ 303 cmp r0, r1 ;\ 304 bge 99f ;\ 305 ldr r1, .L_lock_cas ;\ 306 cmp r0, r1 ;\ 307 strgt r1, [sp, #(TF_PC)] ;\ 308 LOCK_CAS_DEBUG_COUNT_RESTART ;\ 309 99: 310 311 #else 312 #define LOCK_CAS_CHECK /* nothing */ 313 #define LOCK_CAS_CHECK_LOCALS /* nothing */ 314 #endif 315 316 /* 317 * ASM macros for pushing and pulling trapframes from the stack 318 * 319 * These macros are used to handle the trapframe structure defined above. 320 */ 321 322 /* 323 * PUSHFRAME - macro to push a trap frame on the stack in the current mode 324 * Since the current mode is used, the SVC lr field is not defined. 325 */ 326 327 #ifdef CPU_SA110 328 /* 329 * NOTE: r13 and r14 are stored separately as a work around for the 330 * SA110 rev 2 STM^ bug 331 */ 332 #define PUSHUSERREGS \ 333 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 334 add r0, sp, #(TF_USR_SP-TF_R0); /* Adjust the stack pointer */ \ 335 stmia r0, {r13-r14}^ /* Push the user mode registers */ 336 #else 337 #define PUSHUSERREGS \ 338 stmia sp, {r0-r14}^ /* Push the user mode registers */ 339 #endif 340 341 #define PUSHFRAME \ 342 str lr, [sp, #-4]!; /* Push the return address */ \ 343 sub sp, sp, #(TF_PC-TF_R0); /* Adjust the stack pointer */ \ 344 PUSHUSERREGS; /* Push the user mode registers */ \ 345 mov r0, r0; /* NOP for previous instruction */ \ 346 mrs r0, spsr; /* Get the SPSR */ \ 347 str r0, [sp, #-TF_R0]! /* Push the SPSR on the stack */ 348 349 /* 350 * Push a minimal trapframe so we can dispatch an interrupt from the 351 * idle loop. The only reason the idle loop wakes up is to dispatch 352 * interrupts so why take the avoid of a full exception when we can do 353 * something minimal. 354 */ 355 #define PUSHIDLEFRAME \ 356 str lr, [sp, #-4]!; /* save SVC32 lr */ \ 357 str r6, [sp, #(TF_R6-TF_PC)]!; /* save callee-saved r6 */ \ 358 str r4, [sp, #(TF_R4-TF_R6)]!; /* save callee-saved r4 */ \ 359 mrs r0, cpsr; /* Get the CPSR */ \ 360 str r0, [sp, #(-TF_R4)]! /* Push the CPSR on the stack */ 361 362 /* 363 * Push a trapframe to be used by cpu_switchto 364 */ 365 #define PUSHSWITCHFRAME(rX) \ 366 mov ip, sp; \ 367 sub sp, sp, #(TRAPFRAMESIZE-TF_R12); /* Adjust the stack pointer */ \ 368 push {r4-r11}; /* Push the callee saved registers */ \ 369 sub sp, sp, #TF_R4; /* reserve rest of trapframe */ \ 370 str ip, [sp, #TF_SVC_SP]; \ 371 str lr, [sp, #TF_SVC_LR]; \ 372 str lr, [sp, #TF_PC]; \ 373 mrs rX, cpsr; /* Get the CPSR */ \ 374 str rX, [sp, #TF_SPSR] /* save in trapframe */ 375 376 #define PUSHSWITCHFRAME1 \ 377 mov ip, sp; \ 378 sub sp, sp, #(TRAPFRAMESIZE-TF_R8); /* Adjust the stack pointer */ \ 379 push {r4-r7}; /* Push some of the callee saved registers */ \ 380 sub sp, sp, #TF_R4; /* reserve rest of trapframe */ \ 381 str ip, [sp, #TF_SVC_SP]; \ 382 str lr, [sp, #TF_SVC_LR]; \ 383 str lr, [sp, #TF_PC] 384 385 #if defined(_ARM_ARCH_DWORD_OK) && __ARM_EABI__ 386 #define PUSHSWITCHFRAME2 \ 387 strd r10, [sp, #TF_R10]; /* save r10 & r11 */ \ 388 strd r8, [sp, #TF_R8]; /* save r8 & r9 */ \ 389 mrs r0, cpsr; /* Get the CPSR */ \ 390 str r0, [sp, #TF_SPSR] /* save in trapframe */ 391 #else 392 #define PUSHSWITCHFRAME2 \ 393 add r0, sp, #TF_R8; /* get ptr to r8 and above */ \ 394 stmia r0, {r8-r11}; /* save rest of registers */ \ 395 mrs r0, cpsr; /* Get the CPSR */ \ 396 str r0, [sp, #TF_SPSR] /* save in trapframe */ 397 #endif 398 399 /* 400 * PULLFRAME - macro to pull a trap frame from the stack in the current mode 401 * Since the current mode is used, the SVC lr field is ignored. 402 */ 403 404 #define PULLFRAME \ 405 ldr r0, [sp], #TF_R0; /* Pop the SPSR from stack */ \ 406 msr spsr_fsxc, r0; \ 407 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 408 mov r0, r0; /* NOP for previous instruction */ \ 409 add sp, sp, #(TF_PC-TF_R0); /* Adjust the stack pointer */ \ 410 ldr lr, [sp], #0x0004 /* Pop the return address */ 411 412 #define PULLIDLEFRAME \ 413 add sp, sp, #TF_R4; /* Adjust the stack pointer */ \ 414 ldr r4, [sp], #(TF_R6-TF_R4); /* restore callee-saved r4 */ \ 415 ldr r6, [sp], #(TF_PC-TF_R6); /* restore callee-saved r6 */ \ 416 ldr lr, [sp], #4 /* Pop the return address */ 417 418 /* 419 * Pop a trapframe to be used by cpu_switchto (don't touch r0 & r1). 420 */ 421 #define PULLSWITCHFRAME \ 422 add sp, sp, #TF_R4; /* Adjust the stack pointer */ \ 423 pop {r4-r11}; /* pop the callee saved registers */ \ 424 add sp, sp, #(TF_PC-TF_R12); /* Adjust the stack pointer */ \ 425 ldr lr, [sp], #4; /* pop the return address */ 426 427 /* 428 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode 429 * This should only be used if the processor is not currently in SVC32 430 * mode. The processor mode is switched to SVC mode and the trap frame is 431 * stored. The SVC lr field is used to store the previous value of 432 * lr in SVC mode. 433 * 434 * NOTE: r13 and r14 are stored separately as a work around for the 435 * SA110 rev 2 STM^ bug 436 */ 437 438 #ifdef _ARM_ARCH_6 439 #define SET_CPSR_MODE(tmp, mode) \ 440 cps #(mode) 441 #else 442 #define SET_CPSR_MODE(tmp, mode) \ 443 mrs tmp, cpsr; /* Get the CPSR */ \ 444 bic tmp, tmp, #(PSR_MODE); /* Fix for SVC mode */ \ 445 orr tmp, tmp, #(mode); \ 446 msr cpsr_c, tmp /* Punch into SVC mode */ 447 #endif 448 449 #define PUSHFRAMEINSVC \ 450 stmdb sp, {r0-r3}; /* Save 4 registers */ \ 451 mov r0, lr; /* Save xxx32 r14 */ \ 452 mov r1, sp; /* Save xxx32 sp */ \ 453 mrs r3, spsr; /* Save xxx32 spsr */ \ 454 SET_CPSR_MODE(r2, PSR_SVC32_MODE); \ 455 bic r2, sp, #7; /* Align new SVC sp */ \ 456 str r0, [r2, #-4]!; /* Push return address */ \ 457 stmdb r2!, {sp, lr}; /* Push SVC sp, lr */ \ 458 mov sp, r2; /* Keep stack aligned */ \ 459 msr spsr_fsxc, r3; /* Restore correct spsr */ \ 460 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ 461 sub sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \ 462 PUSHUSERREGS; /* Push the user mode registers */ \ 463 mov r0, r0; /* NOP for previous instruction */ \ 464 mrs r0, spsr; /* Get the SPSR */ \ 465 str r0, [sp, #-TF_R0]! /* Push the SPSR onto the stack */ 466 467 /* 468 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack 469 * in SVC32 mode and restore the saved processor mode and PC. 470 * This should be used when the SVC lr register needs to be restored on 471 * exit. 472 */ 473 474 #define PULLFRAMEFROMSVCANDEXIT \ 475 ldr r0, [sp], #0x0008; /* Pop the SPSR from stack */ \ 476 msr spsr_fsxc, r0; /* restore SPSR */ \ 477 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 478 mov r0, r0; /* NOP for previous instruction */ \ 479 add sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \ 480 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ 481 482 #endif /* _LOCORE */ 483 484 #endif /* _ARM32_FRAME_H_ */ 485
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