frame.h revision 1.23.14.1
1 /* $NetBSD: frame.h,v 1.23.14.1 2012/10/30 17:19:04 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1997 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * frame.h 40 * 41 * Stack frames structures 42 * 43 * Created : 30/09/94 44 */ 45 46 #ifndef _ARM32_FRAME_H_ 47 #define _ARM32_FRAME_H_ 48 49 #include <arm/frame.h> /* Common ARM stack frames */ 50 51 #ifndef _LOCORE 52 53 /* 54 * System stack frames. 55 */ 56 57 struct clockframe { 58 struct trapframe cf_tf; 59 }; 60 61 /* 62 * Switch frame. 63 * 64 * Should be a multiple of 8 bytes for dumpsys. 65 */ 66 67 struct switchframe { 68 u_int sf_r4; 69 u_int sf_r5; 70 u_int sf_r6; 71 u_int sf_r7; 72 u_int sf_sp; 73 u_int sf_pc; 74 }; 75 76 /* 77 * Stack frame. Used during stack traces (db_trace.c) 78 */ 79 struct frame { 80 u_int fr_fp; 81 u_int fr_sp; 82 u_int fr_lr; 83 u_int fr_pc; 84 }; 85 86 #ifdef _KERNEL 87 void validate_trapframe(trapframe_t *, int); 88 #endif /* _KERNEL */ 89 90 #else /* _LOCORE */ 91 92 #include "opt_compat_netbsd.h" 93 #include "opt_execfmt.h" 94 #include "opt_multiprocessor.h" 95 #include "opt_cpuoptions.h" 96 #include "opt_arm_debug.h" 97 #include "opt_cputypes.h" 98 99 #include <machine/cpu.h> 100 101 /* 102 * This macro is used by DO_AST_AND_RESTORE_ALIGNMENT_FAULTS to process 103 * any pending softints. 104 */ 105 #if defined(__HAVE_FAST_SOFTINTS) && !defined(__HAVE_PIC_FAST_SOFTINTS) 106 #define DO_PENDING_SOFTINTS \ 107 ldr r0, [r4, #CI_INTR_DEPTH]/* Get current intr depth */ ;\ 108 teq r0, #0 /* Test for 0. */ ;\ 109 bne 10f /* skip softints if != 0 */ ;\ 110 ldr r0, [r4, #CI_CPL] /* Get current priority level */;\ 111 ldr r1, [r4, #CI_SOFTINTS] /* Get pending softint mask */ ;\ 112 lsrs r0, r1, r0 /* shift mask by cpl */ ;\ 113 blne _C_LABEL(dosoftints) /* dosoftints(void) */ ;\ 114 10: 115 #else 116 #define DO_PENDING_SOFTINTS /* nothing */ 117 #endif 118 119 #ifdef MULTIPROCESSOR 120 #define KERNEL_LOCK \ 121 mov r0, #1 ;\ 122 mov r1, #0 ;\ 123 bl _C_LABEL(_kernel_lock) 124 125 #define KERNEL_UNLOCK \ 126 mov r0, #1 ;\ 127 mov r1, #0 ;\ 128 mov r2, #0 ;\ 129 bl _C_LABEL(_kernel_unlock) 130 #else 131 #define KERNEL_LOCK /* nothing */ 132 #define KERNEL_UNLOCK /* nothing */ 133 #endif 134 135 #ifdef _ARM_ARCH_6 136 #define GET_CPSR(rb) /* nothing */ 137 #define CPSID_I(ra,rb) cpsid i 138 #define CPSIE_I(ra,rb) cpsie i 139 #else 140 #define GET_CPSR(rb) \ 141 mrs rb, cpsr /* fetch CPSR */ 142 143 #define CPSID_I(ra,rb) \ 144 orr ra, rb, #(IF32_bits) ;\ 145 msr cpsr_c, ra /* Disable interrupts */ 146 147 #define CPSIE_I(ra,rb) \ 148 bic ra, rb, #(IF32_bits) ;\ 149 msr cpsr_c, ra /* Restore interrupts */ 150 #endif 151 152 /* 153 * AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS 154 * These are used in order to support dynamic enabling/disabling of 155 * alignment faults when executing old a.out ARM binaries. 156 * 157 * Note that when ENABLE_ALIGNMENTS_FAULTS finishes r4 will contain 158 * pointer to the cpu's cpu_info. DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 159 * relies on r4 being preserved. 160 */ 161 #ifdef EXEC_AOUT 162 #define AST_ALIGNMENT_FAULT_LOCALS \ 163 .Laflt_cpufuncs: ;\ 164 .word _C_LABEL(cpufuncs) 165 166 /* 167 * This macro must be invoked following PUSHFRAMEINSVC or PUSHFRAME at 168 * the top of interrupt/exception handlers. 169 * 170 * When invoked, r0 *must* contain the value of SPSR on the current 171 * trap/interrupt frame. This is always the case if ENABLE_ALIGNMENT_FAULTS 172 * is invoked immediately after PUSHFRAMEINSVC or PUSHFRAME. 173 */ 174 #define ENABLE_ALIGNMENT_FAULTS \ 175 and r7, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\ 176 teq r7, #(PSR_USR32_MODE) ;\ 177 GET_CURCPU(r4) /* r4 = cpuinfo */ ;\ 178 bne 1f /* Not USR mode skip AFLT */ ;\ 179 ldr r1, [r4, #CI_CURLWP] /* get curlwp from cpu_info */ ;\ 180 ldr r1, [r1, #L_MD_FLAGS] /* Fetch l_md.md_flags */ ;\ 181 tst r1, #MDLWP_NOALIGNFLT ;\ 182 beq 1f /* AFLTs already enabled */ ;\ 183 ldr r2, .Laflt_cpufuncs ;\ 184 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\ 185 mov r0, #-1 ;\ 186 mov lr, pc ;\ 187 ldr pc, [r2, #CF_CONTROL] /* Enable alignment faults */ ;\ 188 1: KERNEL_LOCK 189 190 /* 191 * This macro must be invoked just before PULLFRAMEFROMSVCANDEXIT or 192 * PULLFRAME at the end of interrupt/exception handlers. We know that 193 * r4 points to cpu_info since that is what ENABLE_ALIGNMENT_FAULTS did 194 * for use. 195 */ 196 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 197 DO_PENDING_SOFTINTS ;\ 198 GET_CPSR(r5) /* save CPSR */ ;\ 199 CPSID_I(r1, r5) /* Disable interrupts */ ;\ 200 teq r7, #(PSR_USR32_MODE) /* Returning to USR mode? */ ;\ 201 bne 3f /* Nope, get out now */ ;\ 202 1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\ 203 teq r1, #0x00000000 ;\ 204 bne 2f /* Yup. Go deal with it */ ;\ 205 ldr r1, [r4, #CI_CURLWP] /* get curlwp from cpu_info */ ;\ 206 ldr r0, [r1, #L_MD_FLAGS] /* get md_flags from lwp */ ;\ 207 tst r0, #MDLWP_NOALIGNFLT ;\ 208 beq 3f /* Keep AFLTs enabled */ ;\ 209 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\ 210 ldr r2, .Laflt_cpufuncs ;\ 211 mov r0, #-1 ;\ 212 bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable AFLTs */ ;\ 213 adr lr, 3f ;\ 214 ldr pc, [r2, #CF_CONTROL] /* Set new CTRL reg value */ ;\ 215 /* NOTREACHED */ \ 216 2: mov r1, #0x00000000 ;\ 217 str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\ 218 CPSIE_I(r5, r5) /* Restore interrupts */ ;\ 219 mov r0, sp ;\ 220 bl _C_LABEL(ast) /* ast(frame) */ ;\ 221 CPSID_I(r0, r5) /* Disable interrupts */ ;\ 222 b 1b /* Back around again */ ;\ 223 3: KERNEL_UNLOCK 224 225 #else /* !EXEC_AOUT */ 226 227 #define AST_ALIGNMENT_FAULT_LOCALS 228 229 #define ENABLE_ALIGNMENT_FAULTS \ 230 and r7, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\ 231 GET_CURCPU(r4) /* r4 = cpuinfo */ ;\ 232 KERNEL_LOCK 233 234 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 235 DO_PENDING_SOFTINTS ;\ 236 GET_CPSR(r5) /* save CPSR */ ;\ 237 CPSID_I(r1, r5) /* Disable interrupts */ ;\ 238 teq r7, #(PSR_USR32_MODE) ;\ 239 bne 2f /* Nope, get out now */ ;\ 240 1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\ 241 teq r1, #0x00000000 ;\ 242 beq 2f /* Nope. Just bail */ ;\ 243 mov r1, #0x00000000 ;\ 244 str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\ 245 CPSIE_I(r5, r5) /* Restore interrupts */ ;\ 246 mov r0, sp ;\ 247 bl _C_LABEL(ast) /* ast(frame) */ ;\ 248 CPSID_I(r0, r5) /* Disable interrupts */ ;\ 249 b 1b ;\ 250 2: KERNEL_UNLOCK /* unlock the kernel */ 251 #endif /* EXEC_AOUT */ 252 253 #ifndef _ARM_ARCH_6 254 #ifdef ARM_LOCK_CAS_DEBUG 255 #define LOCK_CAS_DEBUG_LOCALS \ 256 .L_lock_cas_restart: ;\ 257 .word _C_LABEL(_lock_cas_restart) 258 259 #if defined(__ARMEB__) 260 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 261 ble 99f ;\ 262 ldr r0, .L_lock_cas_restart ;\ 263 ldmia r0, {r1-r2} /* load ev_count */ ;\ 264 adds r2, r2, #1 /* 64-bit incr (lo) */ ;\ 265 adc r1, r1, #0 /* 64-bit incr (hi) */ ;\ 266 stmia r0, {r1-r2} /* store ev_count */ 267 #else /* __ARMEB__ */ 268 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 269 ble 99f ;\ 270 ldr r0, .L_lock_cas_restart ;\ 271 ldmia r0, {r1-r2} /* load ev_count */ ;\ 272 adds r1, r1, #1 /* 64-bit incr (lo) */ ;\ 273 adc r2, r2, #0 /* 64-bit incr (hi) */ ;\ 274 stmia r0, {r1-r2} /* store ev_count */ 275 #endif /* __ARMEB__ */ 276 #else /* ARM_LOCK_CAS_DEBUG */ 277 #define LOCK_CAS_DEBUG_LOCALS /* nothing */ 278 #define LOCK_CAS_DEBUG_COUNT_RESTART /* nothing */ 279 #endif /* ARM_LOCK_CAS_DEBUG */ 280 281 #define LOCK_CAS_CHECK_LOCALS \ 282 .L_lock_cas: ;\ 283 .word _C_LABEL(_lock_cas) ;\ 284 .L_lock_cas_end: ;\ 285 .word _C_LABEL(_lock_cas_end) ;\ 286 LOCK_CAS_DEBUG_LOCALS 287 288 #define LOCK_CAS_CHECK \ 289 ldr r0, [sp] /* get saved PSR */ ;\ 290 and r0, r0, #(PSR_MODE) /* check for SVC32 mode */ ;\ 291 teq r0, #(PSR_SVC32_MODE) ;\ 292 bne 99f /* nope, get out now */ ;\ 293 ldr r0, [sp, #(TF_PC)] ;\ 294 ldr r1, .L_lock_cas_end ;\ 295 cmp r0, r1 ;\ 296 bge 99f ;\ 297 ldr r1, .L_lock_cas ;\ 298 cmp r0, r1 ;\ 299 strgt r1, [sp, #(TF_PC)] ;\ 300 LOCK_CAS_DEBUG_COUNT_RESTART ;\ 301 99: 302 303 #else 304 #define LOCK_CAS_CHECK /* nothing */ 305 #define LOCK_CAS_CHECK_LOCALS /* nothing */ 306 #endif 307 308 /* 309 * ASM macros for pushing and pulling trapframes from the stack 310 * 311 * These macros are used to handle the trapframe structure defined above. 312 */ 313 314 /* 315 * PUSHFRAME - macro to push a trap frame on the stack in the current mode 316 * Since the current mode is used, the SVC lr field is not defined. 317 */ 318 319 #ifdef CPU_SA110 320 /* 321 * NOTE: r13 and r14 are stored separately as a work around for the 322 * SA110 rev 2 STM^ bug 323 */ 324 #define PUSHUSERREGS \ 325 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 326 add r0, sp, #(TF_USR_SP-TF_R0); /* Adjust the stack pointer */ \ 327 stmia r0, {r13-r14}^ /* Push the user mode registers */ 328 #else 329 #define PUSHUSERREGS \ 330 stmia sp, {r0-r14}^ /* Push the user mode registers */ 331 #endif 332 333 #define PUSHFRAME \ 334 str lr, [sp, #-4]!; /* Push the return address */ \ 335 sub sp, sp, #(TF_PC-TF_R0); /* Adjust the stack pointer */ \ 336 PUSHUSERREGS; /* Push the user mode registers */ \ 337 mov r0, r0; /* NOP for previous instruction */ \ 338 mrs r0, spsr_all; /* Get the SPSR */ \ 339 str r0, [sp, #-TF_R0]! /* Push the SPSR on the stack */ 340 341 /* 342 * Push a minimal trapframe so we can dispatch an interrupt from the 343 * idle loop. The only reason the idle loop wakes up is to dispatch 344 * interrupts so why take the avoid of a full exception when we can do 345 * something minimal. 346 */ 347 #define PUSHIDLEFRAME \ 348 str lr, [sp, #-4]!; /* save SVC32 lr */ \ 349 str r6, [sp, #(TF_R6-TF_PC)]!; /* save callee-saved r6 */ \ 350 str r4, [sp, #(TF_R4-TF_R6)]!; /* save callee-saved r4 */ \ 351 mrs r0, cpsr_all; /* Get the CPSR */ \ 352 str r0, [sp, #(-TF_R4)]! /* Push the CPSR on the stack */ 353 354 /* 355 * PULLFRAME - macro to pull a trap frame from the stack in the current mode 356 * Since the current mode is used, the SVC lr field is ignored. 357 */ 358 359 #define PULLFRAME \ 360 ldr r0, [sp], #TF_R0; /* Pop the SPSR from stack */ \ 361 msr spsr_all, r0; \ 362 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 363 mov r0, r0; /* NOP for previous instruction */ \ 364 add sp, sp, #(TF_PC-TF_R0); /* Adjust the stack pointer */ \ 365 ldr lr, [sp], #0x0004 /* Pop the return address */ 366 367 #define PULLIDLEFRAME \ 368 add sp, sp, #TF_R4; /* Adjust the stack pointer */ \ 369 ldr r4, [sp], #(TF_R6-TF_R4); /* restore callee-saved r4 */ \ 370 ldr r6, [sp], #(TF_PC-TF_R6); /* restore callee-saved r6 */ \ 371 ldr lr, [sp], #4 /* Pop the return address */ 372 373 /* 374 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode 375 * This should only be used if the processor is not currently in SVC32 376 * mode. The processor mode is switched to SVC mode and the trap frame is 377 * stored. The SVC lr field is used to store the previous value of 378 * lr in SVC mode. 379 * 380 * NOTE: r13 and r14 are stored separately as a work around for the 381 * SA110 rev 2 STM^ bug 382 */ 383 384 #ifdef _ARM_ARCH_6 385 #define SET_CPSR_MODE(tmp, mode) \ 386 cps #(mode) 387 #else 388 #define SET_CPSR_MODE(tmp, mode) \ 389 mrs tmp, cpsr; /* Get the CPSR */ \ 390 bic tmp, tmp, #(PSR_MODE); /* Fix for SVC mode */ \ 391 orr tmp, tmp, #(mode); \ 392 msr cpsr_c, tmp /* Punch into SVC mode */ 393 #endif 394 395 #define PUSHFRAMEINSVC \ 396 stmdb sp, {r0-r3}; /* Save 4 registers */ \ 397 mov r0, lr; /* Save xxx32 r14 */ \ 398 mov r1, sp; /* Save xxx32 sp */ \ 399 mrs r3, spsr; /* Save xxx32 spsr */ \ 400 SET_CPSR_MODE(r2, PSR_SVC32_MODE); \ 401 bic r2, sp, #7; /* Align new SVC sp */ \ 402 str r0, [r2, #-4]!; /* Push return address */ \ 403 stmdb r2!, {sp, lr}; /* Push SVC sp, lr */ \ 404 mov sp, r2; /* Keep stack aligned */ \ 405 msr spsr_all, r3; /* Restore correct spsr */ \ 406 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ 407 sub sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \ 408 PUSHUSERREGS; /* Push the user mode registers */ \ 409 mov r0, r0; /* NOP for previous instruction */ \ 410 mrs r0, spsr_all; /* Get the SPSR */ \ 411 str r0, [sp, #-TF_R0]! /* Push the SPSR onto the stack */ 412 413 /* 414 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack 415 * in SVC32 mode and restore the saved processor mode and PC. 416 * This should be used when the SVC lr register needs to be restored on 417 * exit. 418 */ 419 420 #define PULLFRAMEFROMSVCANDEXIT \ 421 ldr r0, [sp], #0x0008; /* Pop the SPSR from stack */ \ 422 msr spsr_all, r0; /* restore SPSR */ \ 423 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 424 mov r0, r0; /* NOP for previous instruction */ \ 425 add sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \ 426 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ 427 428 #endif /* _LOCORE */ 429 430 #endif /* _ARM32_FRAME_H_ */ 431
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