frame.h revision 1.23.14.2
1 /* $NetBSD: frame.h,v 1.23.14.2 2014/05/22 11:39:33 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1997 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * frame.h 40 * 41 * Stack frames structures 42 * 43 * Created : 30/09/94 44 */ 45 46 #ifndef _ARM32_FRAME_H_ 47 #define _ARM32_FRAME_H_ 48 49 #include <arm/frame.h> /* Common ARM stack frames */ 50 51 #ifndef _LOCORE 52 53 /* 54 * Switch frame. 55 * 56 * Should be a multiple of 8 bytes for dumpsys. 57 */ 58 59 struct switchframe { 60 u_int sf_r4; 61 u_int sf_r5; 62 u_int sf_r6; 63 u_int sf_r7; 64 u_int sf_sp; 65 u_int sf_pc; 66 }; 67 68 /* 69 * System stack frames. 70 */ 71 72 struct clockframe { 73 struct trapframe cf_tf; 74 }; 75 76 /* 77 * Stack frame. Used during stack traces (db_trace.c) 78 */ 79 struct frame { 80 u_int fr_fp; 81 u_int fr_sp; 82 u_int fr_lr; 83 u_int fr_pc; 84 }; 85 86 #ifdef _KERNEL 87 void validate_trapframe(trapframe_t *, int); 88 #endif /* _KERNEL */ 89 90 #else /* _LOCORE */ 91 92 #include "opt_compat_netbsd.h" 93 #include "opt_execfmt.h" 94 #include "opt_multiprocessor.h" 95 #include "opt_cpuoptions.h" 96 #include "opt_arm_debug.h" 97 #include "opt_cputypes.h" 98 99 #include <arm/locore.h> 100 101 /* 102 * This macro is used by DO_AST_AND_RESTORE_ALIGNMENT_FAULTS to process 103 * any pending softints. 104 */ 105 #ifdef _ARM_ARCH_4T 106 #define B_CF_CONTROL(rX) ;\ 107 ldr ip, [rX, #CF_CONTROL] /* get function addr */ ;\ 108 bx ip /* branch to cpu_control */ 109 #else 110 #define B_CF_CONTROL(rX) ;\ 111 ldr pc, [rX, #CF_CONTROL] /* branch to cpu_control */ 112 #endif 113 #ifdef _ARM_ARCH_5T 114 #define BL_CF_CONTROL(rX) ;\ 115 ldr ip, [rX, #CF_CONTROL] /* get function addr */ ;\ 116 blx ip /* call cpu_control */ 117 #else 118 #define BL_CF_CONTROL(rX) ;\ 119 mov lr, pc ;\ 120 ldr pc, [rX, #CF_CONTROL] /* call cpu_control */ 121 #endif 122 #if defined(__HAVE_FAST_SOFTINTS) && !defined(__HAVE_PIC_FAST_SOFTINTS) 123 #define DO_PENDING_SOFTINTS \ 124 ldr r0, [r4, #CI_INTR_DEPTH]/* Get current intr depth */ ;\ 125 cmp r0, #0 /* Test for 0. */ ;\ 126 bne 10f /* skip softints if != 0 */ ;\ 127 ldr r0, [r4, #CI_CPL] /* Get current priority level */;\ 128 ldr r1, [r4, #CI_SOFTINTS] /* Get pending softint mask */ ;\ 129 lsrs r0, r1, r0 /* shift mask by cpl */ ;\ 130 blne _C_LABEL(dosoftints) /* dosoftints(void) */ ;\ 131 10: 132 #else 133 #define DO_PENDING_SOFTINTS /* nothing */ 134 #endif 135 136 #ifdef _ARM_ARCH_6 137 #define GET_CPSR(rb) /* nothing */ 138 #define CPSID_I(ra,rb) cpsid i 139 #define CPSIE_I(ra,rb) cpsie i 140 #else 141 #define GET_CPSR(rb) \ 142 mrs rb, cpsr /* fetch CPSR */ 143 144 #define CPSID_I(ra,rb) \ 145 orr ra, rb, #(IF32_bits) ;\ 146 msr cpsr_c, ra /* Disable interrupts */ 147 148 #define CPSIE_I(ra,rb) \ 149 bic ra, rb, #(IF32_bits) ;\ 150 msr cpsr_c, ra /* Restore interrupts */ 151 #endif 152 153 /* 154 * AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS 155 * These are used in order to support dynamic enabling/disabling of 156 * alignment faults when executing old a.out ARM binaries. 157 * 158 * Note that when ENABLE_ALIGNMENTS_FAULTS finishes r4 will contain 159 * pointer to the cpu's cpu_info. DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 160 * relies on r4 being preserved. 161 */ 162 #ifdef EXEC_AOUT 163 #define AST_ALIGNMENT_FAULT_LOCALS \ 164 .Laflt_cpufuncs: ;\ 165 .word _C_LABEL(cpufuncs) 166 167 /* 168 * This macro must be invoked following PUSHFRAMEINSVC or PUSHFRAME at 169 * the top of interrupt/exception handlers. 170 * 171 * When invoked, r0 *must* contain the value of SPSR on the current 172 * trap/interrupt frame. This is always the case if ENABLE_ALIGNMENT_FAULTS 173 * is invoked immediately after PUSHFRAMEINSVC or PUSHFRAME. 174 */ 175 #define ENABLE_ALIGNMENT_FAULTS \ 176 and r7, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\ 177 teq r7, #(PSR_USR32_MODE) ;\ 178 GET_CURCPU(r4) /* r4 = cpuinfo */ ;\ 179 bne 1f /* Not USR mode skip AFLT */ ;\ 180 ldr r1, [r4, #CI_CURLWP] /* get curlwp from cpu_info */ ;\ 181 ldr r1, [r1, #L_MD_FLAGS] /* Fetch l_md.md_flags */ ;\ 182 tst r1, #MDLWP_NOALIGNFLT ;\ 183 beq 1f /* AFLTs already enabled */ ;\ 184 ldr r2, .Laflt_cpufuncs ;\ 185 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\ 186 mov r0, #-1 ;\ 187 BL_CF_CONTROL(r2) /* Enable alignment faults */ ;\ 188 1: /* done */ 189 190 /* 191 * This macro must be invoked just before PULLFRAMEFROMSVCANDEXIT or 192 * PULLFRAME at the end of interrupt/exception handlers. We know that 193 * r4 points to cpu_info since that is what ENABLE_ALIGNMENT_FAULTS did 194 * for use. 195 */ 196 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 197 DO_PENDING_SOFTINTS ;\ 198 GET_CPSR(r5) /* save CPSR */ ;\ 199 CPSID_I(r1, r5) /* Disable interrupts */ ;\ 200 teq r7, #(PSR_USR32_MODE) /* Returning to USR mode? */ ;\ 201 bne 3f /* Nope, get out now */ ;\ 202 1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\ 203 teq r1, #0x00000000 ;\ 204 bne 2f /* Yup. Go deal with it */ ;\ 205 ldr r1, [r4, #CI_CURLWP] /* get curlwp from cpu_info */ ;\ 206 ldr r0, [r1, #L_MD_FLAGS] /* get md_flags from lwp */ ;\ 207 tst r0, #MDLWP_NOALIGNFLT ;\ 208 beq 3f /* Keep AFLTs enabled */ ;\ 209 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\ 210 ldr r2, .Laflt_cpufuncs ;\ 211 mov r0, #-1 ;\ 212 bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable AFLTs */ ;\ 213 adr lr, 3f ;\ 214 B_CF_CONTROL(r2) /* Set new CTRL reg value */ ;\ 215 /* NOTREACHED */ \ 216 2: mov r1, #0x00000000 ;\ 217 str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\ 218 CPSIE_I(r5, r5) /* Restore interrupts */ ;\ 219 mov r0, sp ;\ 220 bl _C_LABEL(ast) /* ast(frame) */ ;\ 221 CPSID_I(r0, r5) /* Disable interrupts */ ;\ 222 b 1b /* Back around again */ ;\ 223 3: /* done */ 224 225 #else /* !EXEC_AOUT */ 226 227 #define AST_ALIGNMENT_FAULT_LOCALS 228 229 #define ENABLE_ALIGNMENT_FAULTS \ 230 and r7, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\ 231 GET_CURCPU(r4) /* r4 = cpuinfo */ 232 233 234 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 235 DO_PENDING_SOFTINTS ;\ 236 GET_CPSR(r5) /* save CPSR */ ;\ 237 CPSID_I(r1, r5) /* Disable interrupts */ ;\ 238 teq r7, #(PSR_USR32_MODE) ;\ 239 bne 2f /* Nope, get out now */ ;\ 240 1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\ 241 teq r1, #0x00000000 ;\ 242 beq 2f /* Nope. Just bail */ ;\ 243 mov r1, #0x00000000 ;\ 244 str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\ 245 CPSIE_I(r5, r5) /* Restore interrupts */ ;\ 246 mov r0, sp ;\ 247 bl _C_LABEL(ast) /* ast(frame) */ ;\ 248 CPSID_I(r0, r5) /* Disable interrupts */ ;\ 249 b 1b ;\ 250 2: /* done */ 251 #endif /* EXEC_AOUT */ 252 253 #ifndef _ARM_ARCH_6 254 #ifdef ARM_LOCK_CAS_DEBUG 255 #define LOCK_CAS_DEBUG_LOCALS \ 256 .L_lock_cas_restart: ;\ 257 .word _C_LABEL(_lock_cas_restart) 258 259 #if defined(__ARMEB__) 260 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 261 ble 99f ;\ 262 ldr r0, .L_lock_cas_restart ;\ 263 ldmia r0, {r1-r2} /* load ev_count */ ;\ 264 adds r2, r2, #1 /* 64-bit incr (lo) */ ;\ 265 adc r1, r1, #0 /* 64-bit incr (hi) */ ;\ 266 stmia r0, {r1-r2} /* store ev_count */ 267 #else /* __ARMEB__ */ 268 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 269 ble 99f ;\ 270 ldr r0, .L_lock_cas_restart ;\ 271 ldmia r0, {r1-r2} /* load ev_count */ ;\ 272 adds r1, r1, #1 /* 64-bit incr (lo) */ ;\ 273 adc r2, r2, #0 /* 64-bit incr (hi) */ ;\ 274 stmia r0, {r1-r2} /* store ev_count */ 275 #endif /* __ARMEB__ */ 276 #else /* ARM_LOCK_CAS_DEBUG */ 277 #define LOCK_CAS_DEBUG_LOCALS /* nothing */ 278 #define LOCK_CAS_DEBUG_COUNT_RESTART /* nothing */ 279 #endif /* ARM_LOCK_CAS_DEBUG */ 280 281 #define LOCK_CAS_CHECK_LOCALS \ 282 .L_lock_cas: ;\ 283 .word _C_LABEL(_lock_cas) ;\ 284 .L_lock_cas_end: ;\ 285 .word _C_LABEL(_lock_cas_end) ;\ 286 LOCK_CAS_DEBUG_LOCALS 287 288 #define LOCK_CAS_CHECK \ 289 ldr r0, [sp] /* get saved PSR */ ;\ 290 and r0, r0, #(PSR_MODE) /* check for SVC32 mode */ ;\ 291 teq r0, #(PSR_SVC32_MODE) ;\ 292 bne 99f /* nope, get out now */ ;\ 293 ldr r0, [sp, #(TF_PC)] ;\ 294 ldr r1, .L_lock_cas_end ;\ 295 cmp r0, r1 ;\ 296 bge 99f ;\ 297 ldr r1, .L_lock_cas ;\ 298 cmp r0, r1 ;\ 299 strgt r1, [sp, #(TF_PC)] ;\ 300 LOCK_CAS_DEBUG_COUNT_RESTART ;\ 301 99: 302 303 #else 304 #define LOCK_CAS_CHECK /* nothing */ 305 #define LOCK_CAS_CHECK_LOCALS /* nothing */ 306 #endif 307 308 /* 309 * ASM macros for pushing and pulling trapframes from the stack 310 * 311 * These macros are used to handle the trapframe structure defined above. 312 */ 313 314 /* 315 * PUSHFRAME - macro to push a trap frame on the stack in the current mode 316 * Since the current mode is used, the SVC lr field is not defined. 317 */ 318 319 #ifdef CPU_SA110 320 /* 321 * NOTE: r13 and r14 are stored separately as a work around for the 322 * SA110 rev 2 STM^ bug 323 */ 324 #define PUSHUSERREGS \ 325 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 326 add r0, sp, #(TF_USR_SP-TF_R0); /* Adjust the stack pointer */ \ 327 stmia r0, {r13-r14}^ /* Push the user mode registers */ 328 #else 329 #define PUSHUSERREGS \ 330 stmia sp, {r0-r14}^ /* Push the user mode registers */ 331 #endif 332 333 #define PUSHFRAME \ 334 str lr, [sp, #-4]!; /* Push the return address */ \ 335 sub sp, sp, #(TF_PC-TF_R0); /* Adjust the stack pointer */ \ 336 PUSHUSERREGS; /* Push the user mode registers */ \ 337 mov r0, r0; /* NOP for previous instruction */ \ 338 mrs r0, spsr; /* Get the SPSR */ \ 339 str r0, [sp, #-TF_R0]! /* Push the SPSR on the stack */ 340 341 /* 342 * Push a minimal trapframe so we can dispatch an interrupt from the 343 * idle loop. The only reason the idle loop wakes up is to dispatch 344 * interrupts so why take the avoid of a full exception when we can do 345 * something minimal. 346 */ 347 #define PUSHIDLEFRAME \ 348 str lr, [sp, #-4]!; /* save SVC32 lr */ \ 349 str r6, [sp, #(TF_R6-TF_PC)]!; /* save callee-saved r6 */ \ 350 str r4, [sp, #(TF_R4-TF_R6)]!; /* save callee-saved r4 */ \ 351 mrs r0, cpsr; /* Get the CPSR */ \ 352 str r0, [sp, #(-TF_R4)]! /* Push the CPSR on the stack */ 353 354 /* 355 * Push a trapframe to be used by cpu_switchto 356 */ 357 #define PUSHSWITCHFRAME(rX) \ 358 mov ip, sp; \ 359 sub sp, sp, #(TRAPFRAMESIZE-TF_R12); /* Adjust the stack pointer */ \ 360 push {r4-r11}; /* Push the callee saved registers */ \ 361 sub sp, sp, #TF_R4; /* reserve rest of trapframe */ \ 362 str ip, [sp, #TF_SVC_SP]; \ 363 str lr, [sp, #TF_SVC_LR]; \ 364 str lr, [sp, #TF_PC]; \ 365 mrs rX, cpsr; /* Get the CPSR */ \ 366 str rX, [sp, #TF_SPSR] /* save in trapframe */ 367 368 #define PUSHSWITCHFRAME1 \ 369 mov ip, sp; \ 370 sub sp, sp, #(TRAPFRAMESIZE-TF_R8); /* Adjust the stack pointer */ \ 371 push {r4-r7}; /* Push some of the callee saved registers */ \ 372 sub sp, sp, #TF_R4; /* reserve rest of trapframe */ \ 373 str ip, [sp, #TF_SVC_SP]; \ 374 str lr, [sp, #TF_SVC_LR]; \ 375 str lr, [sp, #TF_PC] 376 377 #if defined(_ARM_ARCH_DWORD_OK) && __ARM_EABI__ 378 #define PUSHSWITCHFRAME2 \ 379 strd r10, [sp, #TF_R10]; /* save r10 & r11 */ \ 380 strd r8, [sp, #TF_R8]; /* save r8 & r9 */ \ 381 mrs r0, cpsr; /* Get the CPSR */ \ 382 str r0, [sp, #TF_SPSR] /* save in trapframe */ 383 #else 384 #define PUSHSWITCHFRAME2 \ 385 add r0, sp, #TF_R8; /* get ptr to r8 and above */ \ 386 stmia r0, {r8-r11}; /* save rest of registers */ \ 387 mrs r0, cpsr; /* Get the CPSR */ \ 388 str r0, [sp, #TF_SPSR] /* save in trapframe */ 389 #endif 390 391 /* 392 * PULLFRAME - macro to pull a trap frame from the stack in the current mode 393 * Since the current mode is used, the SVC lr field is ignored. 394 */ 395 396 #define PULLFRAME \ 397 ldr r0, [sp], #TF_R0; /* Pop the SPSR from stack */ \ 398 msr spsr_fsxc, r0; \ 399 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 400 mov r0, r0; /* NOP for previous instruction */ \ 401 add sp, sp, #(TF_PC-TF_R0); /* Adjust the stack pointer */ \ 402 ldr lr, [sp], #0x0004 /* Pop the return address */ 403 404 #define PULLIDLEFRAME \ 405 add sp, sp, #TF_R4; /* Adjust the stack pointer */ \ 406 ldr r4, [sp], #(TF_R6-TF_R4); /* restore callee-saved r4 */ \ 407 ldr r6, [sp], #(TF_PC-TF_R6); /* restore callee-saved r6 */ \ 408 ldr lr, [sp], #4 /* Pop the return address */ 409 410 /* 411 * Pop a trapframe to be used by cpu_switchto (don't touch r0 & r1). 412 */ 413 #define PULLSWITCHFRAME \ 414 add sp, sp, #TF_R4; /* Adjust the stack pointer */ \ 415 pop {r4-r11}; /* pop the callee saved registers */ \ 416 add sp, sp, #(TF_PC-TF_R12); /* Adjust the stack pointer */ \ 417 ldr lr, [sp], #4; /* pop the return address */ 418 419 /* 420 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode 421 * This should only be used if the processor is not currently in SVC32 422 * mode. The processor mode is switched to SVC mode and the trap frame is 423 * stored. The SVC lr field is used to store the previous value of 424 * lr in SVC mode. 425 * 426 * NOTE: r13 and r14 are stored separately as a work around for the 427 * SA110 rev 2 STM^ bug 428 */ 429 430 #ifdef _ARM_ARCH_6 431 #define SET_CPSR_MODE(tmp, mode) \ 432 cps #(mode) 433 #else 434 #define SET_CPSR_MODE(tmp, mode) \ 435 mrs tmp, cpsr; /* Get the CPSR */ \ 436 bic tmp, tmp, #(PSR_MODE); /* Fix for SVC mode */ \ 437 orr tmp, tmp, #(mode); \ 438 msr cpsr_c, tmp /* Punch into SVC mode */ 439 #endif 440 441 #define PUSHFRAMEINSVC \ 442 stmdb sp, {r0-r3}; /* Save 4 registers */ \ 443 mov r0, lr; /* Save xxx32 r14 */ \ 444 mov r1, sp; /* Save xxx32 sp */ \ 445 mrs r3, spsr; /* Save xxx32 spsr */ \ 446 SET_CPSR_MODE(r2, PSR_SVC32_MODE); \ 447 bic r2, sp, #7; /* Align new SVC sp */ \ 448 str r0, [r2, #-4]!; /* Push return address */ \ 449 stmdb r2!, {sp, lr}; /* Push SVC sp, lr */ \ 450 mov sp, r2; /* Keep stack aligned */ \ 451 msr spsr_fsxc, r3; /* Restore correct spsr */ \ 452 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ 453 sub sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \ 454 PUSHUSERREGS; /* Push the user mode registers */ \ 455 mov r0, r0; /* NOP for previous instruction */ \ 456 mrs r0, spsr; /* Get the SPSR */ \ 457 str r0, [sp, #-TF_R0]! /* Push the SPSR onto the stack */ 458 459 /* 460 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack 461 * in SVC32 mode and restore the saved processor mode and PC. 462 * This should be used when the SVC lr register needs to be restored on 463 * exit. 464 */ 465 466 #define PULLFRAMEFROMSVCANDEXIT \ 467 ldr r0, [sp], #0x0008; /* Pop the SPSR from stack */ \ 468 msr spsr_fsxc, r0; /* restore SPSR */ \ 469 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 470 mov r0, r0; /* NOP for previous instruction */ \ 471 add sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \ 472 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ 473 474 #endif /* _LOCORE */ 475 476 #endif /* _ARM32_FRAME_H_ */ 477
Indexes created Wed Oct 15 16:09:53 GMT 2025