frame.h revision 1.25
1 /* $NetBSD: frame.h,v 1.25 2012/07/31 07:23:16 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1997 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * frame.h 40 * 41 * Stack frames structures 42 * 43 * Created : 30/09/94 44 */ 45 46 #ifndef _ARM32_FRAME_H_ 47 #define _ARM32_FRAME_H_ 48 49 #include <arm/frame.h> /* Common ARM stack frames */ 50 51 #ifndef _LOCORE 52 53 /* 54 * System stack frames. 55 */ 56 57 typedef struct irqframe { 58 unsigned int if_spsr; 59 unsigned int if_r0; 60 unsigned int if_r1; 61 unsigned int if_r2; 62 unsigned int if_r3; 63 unsigned int if_r4; 64 unsigned int if_r5; 65 unsigned int if_r6; 66 unsigned int if_r7; 67 unsigned int if_r8; 68 unsigned int if_r9; 69 unsigned int if_r10; 70 unsigned int if_r11; 71 unsigned int if_r12; 72 unsigned int if_usr_sp; 73 unsigned int if_usr_lr; 74 unsigned int if_fill; 75 unsigned int if_svc_sp; 76 unsigned int if_svc_lr; 77 unsigned int if_pc; 78 } irqframe_t; 79 80 struct clockframe { 81 struct irqframe cf_if; 82 }; 83 84 /* 85 * Switch frame. 86 * 87 * Should be a multiple of 8 bytes for dumpsys. 88 */ 89 90 struct switchframe { 91 u_int sf_r4; 92 u_int sf_r5; 93 u_int sf_r6; 94 u_int sf_r7; 95 u_int sf_sp; 96 u_int sf_pc; 97 }; 98 99 /* 100 * Stack frame. Used during stack traces (db_trace.c) 101 */ 102 struct frame { 103 u_int fr_fp; 104 u_int fr_sp; 105 u_int fr_lr; 106 u_int fr_pc; 107 }; 108 109 #ifdef _KERNEL 110 void validate_trapframe(trapframe_t *, int); 111 #endif /* _KERNEL */ 112 113 #else /* _LOCORE */ 114 115 #include "opt_compat_netbsd.h" 116 #include "opt_execfmt.h" 117 #include "opt_multiprocessor.h" 118 #include "opt_cpuoptions.h" 119 #include "opt_arm_debug.h" 120 121 #include <machine/cpu.h> 122 123 /* 124 * This macro is used by DO_AST_AND_RESTORE_ALIGNMENT_FAULTS to process 125 * any pending softints. 126 */ 127 #ifdef __HAVE_FAST_SOFTINTS 128 #define DO_PENDING_SOFTINTS \ 129 ldr r0, [r4, #CI_INTR_DEPTH]/* Get current intr depth */ ;\ 130 teq r0, #0 /* Test for 0. */ ;\ 131 bne 10f /* skip softints if != 0 */ ;\ 132 ldr r0, [r4, #CI_CPL] /* Get current priority level */;\ 133 ldr r1, [r4, #CI_SOFTINTS] /* Get pending softint mask */ ;\ 134 movs r0, r1, lsr r0 /* shift mask by cpl */ ;\ 135 blne _C_LABEL(dosoftints) /* dosoftints(void) */ ;\ 136 10: 137 #else 138 #define DO_PENDING_SOFTINTS /* nothing */ 139 #endif 140 141 /* 142 * AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS 143 * These are used in order to support dynamic enabling/disabling of 144 * alignment faults when executing old a.out ARM binaries. 145 * 146 * Note that when ENABLE_ALIGNMENTS_FAULTS finishes r4 will contain 147 * pointer to the cpu's cpu_info. DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 148 * relies on r4 being preserved. 149 */ 150 #ifdef EXEC_AOUT 151 #define AST_ALIGNMENT_FAULT_LOCALS \ 152 .Laflt_cpufuncs: ;\ 153 .word _C_LABEL(cpufuncs) 154 155 /* 156 * This macro must be invoked following PUSHFRAMEINSVC or PUSHFRAME at 157 * the top of interrupt/exception handlers. 158 * 159 * When invoked, r0 *must* contain the value of SPSR on the current 160 * trap/interrupt frame. This is always the case if ENABLE_ALIGNMENT_FAULTS 161 * is invoked immediately after PUSHFRAMEINSVC or PUSHFRAME. 162 */ 163 #define ENABLE_ALIGNMENT_FAULTS \ 164 and r0, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\ 165 teq r0, #(PSR_USR32_MODE) ;\ 166 GET_CURCPU(r4) /* r4 = cpuinfo */ ;\ 167 bne 1f /* Not USR mode skip AFLT */ ;\ 168 ldr r1, [r4, #CI_CURPCB] /* get curpcb from cpu_info */ ;\ 169 ldr r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\ 170 tst r1, #PCB_NOALIGNFLT ;\ 171 beq 1f /* AFLTs already enabled */ ;\ 172 ldr r2, .Laflt_cpufuncs ;\ 173 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\ 174 mov r0, #-1 ;\ 175 mov lr, pc ;\ 176 ldr pc, [r2, #CF_CONTROL] /* Enable alignment faults */ ;\ 177 1: 178 179 /* 180 * This macro must be invoked just before PULLFRAMEFROMSVCANDEXIT or 181 * PULLFRAME at the end of interrupt/exception handlers. We know that 182 * r4 points to cpu_info since that is what ENABLE_ALIGNMENT_FAULTS did 183 * for use. 184 */ 185 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 186 DO_PENDING_SOFTINTS ;\ 187 ldr r0, [sp] /* Get the SPSR from stack */ ;\ 188 mrs r5, cpsr /* save CPSR */ ;\ 189 orr r1, r5, #(IF32_bits) ;\ 190 msr cpsr_c, r1 /* Disable interrupts */ ;\ 191 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ 192 teq r0, #(PSR_USR32_MODE) ;\ 193 bne 3f /* Nope, get out now */ ;\ 194 1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\ 195 teq r1, #0x00000000 ;\ 196 bne 2f /* Yup. Go deal with it */ ;\ 197 ldr r1, [r4, #CI_CURPCB] /* Get current PCB */ ;\ 198 ldr r0, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\ 199 tst r0, #PCB_NOALIGNFLT ;\ 200 beq 3f /* Keep AFLTs enabled */ ;\ 201 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\ 202 ldr r2, .Laflt_cpufuncs ;\ 203 mov r0, #-1 ;\ 204 bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable AFLTs */ ;\ 205 adr lr, 3f ;\ 206 ldr pc, [r2, #CF_CONTROL] /* Set new CTRL reg value */ ;\ 207 /* NOTREACHED */ \ 208 2: mov r1, #0x00000000 ;\ 209 str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\ 210 bic r5, r5, #(IF32_bits) ;\ 211 msr cpsr_c, r5 /* Restore interrupts */ ;\ 212 mov r0, sp ;\ 213 bl _C_LABEL(ast) /* ast(frame) */ ;\ 214 orr r0, r5, #(IF32_bits) /* Disable IRQs */ ;\ 215 msr cpsr_c, r0 ;\ 216 b 1b /* Back around again */ ;\ 217 3: 218 219 #else /* !EXEC_AOUT */ 220 221 #define AST_ALIGNMENT_FAULT_LOCALS 222 223 #define ENABLE_ALIGNMENT_FAULTS GET_CURCPU(r4) 224 225 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 226 DO_PENDING_SOFTINTS ;\ 227 ldr r0, [sp] /* Get the SPSR from stack */ ;\ 228 mrs r5, cpsr /* save CPSR */ ;\ 229 orr r1, r5, #(IF32_bits) ;\ 230 msr cpsr_c, r1 /* Disable interrupts */ ;\ 231 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ 232 teq r0, #(PSR_USR32_MODE) ;\ 233 bne 2f /* Nope, get out now */ ;\ 234 1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\ 235 teq r1, #0x00000000 ;\ 236 beq 2f /* Nope. Just bail */ ;\ 237 mov r1, #0x00000000 ;\ 238 str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\ 239 bic r5, r5, #(IF32_bits) ;\ 240 msr cpsr_c, r5 /* Restore interrupts */ ;\ 241 mov r0, sp ;\ 242 bl _C_LABEL(ast) /* ast(frame) */ ;\ 243 orr r0, r5, #(IF32_bits) /* Disable IRQs */ ;\ 244 msr cpsr_c, r0 ;\ 245 b 1b ;\ 246 2: 247 #endif /* EXEC_AOUT */ 248 249 #ifdef ARM_LOCK_CAS_DEBUG 250 #define LOCK_CAS_DEBUG_LOCALS \ 251 .L_lock_cas_restart: ;\ 252 .word _C_LABEL(_lock_cas_restart) 253 254 #if defined(__ARMEB__) 255 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 256 ble 99f ;\ 257 ldr r0, .L_lock_cas_restart ;\ 258 ldmia r0, {r1-r2} /* load ev_count */ ;\ 259 adds r2, r2, #1 /* 64-bit incr (lo) */ ;\ 260 adc r1, r1, #0 /* 64-bit incr (hi) */ ;\ 261 stmia r0, {r1-r2} /* store ev_count */ 262 #else /* __ARMEB__ */ 263 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 264 ble 99f ;\ 265 ldr r0, .L_lock_cas_restart ;\ 266 ldmia r0, {r1-r2} /* load ev_count */ ;\ 267 adds r1, r1, #1 /* 64-bit incr (lo) */ ;\ 268 adc r2, r2, #0 /* 64-bit incr (hi) */ ;\ 269 stmia r0, {r1-r2} /* store ev_count */ 270 #endif /* __ARMEB__ */ 271 #else /* ARM_LOCK_CAS_DEBUG */ 272 #define LOCK_CAS_DEBUG_LOCALS /* nothing */ 273 #define LOCK_CAS_DEBUG_COUNT_RESTART /* nothing */ 274 #endif /* ARM_LOCK_CAS_DEBUG */ 275 276 #define LOCK_CAS_CHECK_LOCALS \ 277 .L_lock_cas: ;\ 278 .word _C_LABEL(_lock_cas) ;\ 279 .L_lock_cas_end: ;\ 280 .word _C_LABEL(_lock_cas_end) ;\ 281 LOCK_CAS_DEBUG_LOCALS 282 283 #define LOCK_CAS_CHECK \ 284 ldr r0, [sp] /* get saved PSR */ ;\ 285 and r0, r0, #(PSR_MODE) /* check for SVC32 mode */ ;\ 286 teq r0, #(PSR_SVC32_MODE) ;\ 287 bne 99f /* nope, get out now */ ;\ 288 ldr r0, [sp, #(IF_PC)] ;\ 289 ldr r1, .L_lock_cas_end ;\ 290 cmp r0, r1 ;\ 291 bge 99f ;\ 292 ldr r1, .L_lock_cas ;\ 293 cmp r0, r1 ;\ 294 strgt r1, [sp, #(IF_PC)] ;\ 295 LOCK_CAS_DEBUG_COUNT_RESTART ;\ 296 99: 297 298 /* 299 * ASM macros for pushing and pulling trapframes from the stack 300 * 301 * These macros are used to handle the irqframe and trapframe structures 302 * defined above. 303 */ 304 305 /* 306 * PUSHFRAME - macro to push a trap frame on the stack in the current mode 307 * Since the current mode is used, the SVC lr field is not defined. 308 * 309 * NOTE: r13 and r14 are stored separately as a work around for the 310 * SA110 rev 2 STM^ bug 311 */ 312 313 #define PUSHFRAME \ 314 str lr, [sp, #-4]!; /* Push the return address */ \ 315 sub sp, sp, #(4*18); /* Adjust the stack pointer */ \ 316 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 317 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 318 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 319 mov r0, r0; /* NOP for previous instruction */ \ 320 mrs r0, spsr_all; /* Get the SPSR */ \ 321 str r0, [sp, #-4]! /* Push the SPSR on the stack */ 322 323 /* 324 * PULLFRAME - macro to pull a trap frame from the stack in the current mode 325 * Since the current mode is used, the SVC lr field is ignored. 326 */ 327 328 #define PULLFRAME \ 329 ldr r0, [sp], #0x0004; /* Pop the SPSR from stack */ \ 330 msr spsr_all, r0; \ 331 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 332 mov r0, r0; /* NOP for previous instruction */ \ 333 add sp, sp, #(4*18); /* Adjust the stack pointer */ \ 334 ldr lr, [sp], #0x0004 /* Pop the return address */ 335 336 /* 337 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode 338 * This should only be used if the processor is not currently in SVC32 339 * mode. The processor mode is switched to SVC mode and the trap frame is 340 * stored. The SVC lr field is used to store the previous value of 341 * lr in SVC mode. 342 * 343 * NOTE: r13 and r14 are stored separately as a work around for the 344 * SA110 rev 2 STM^ bug 345 */ 346 347 #ifdef _ARM_ARCH_6 348 #define SET_CPSR_MODE(tmp, mode) \ 349 cps #(mode) 350 #else 351 #define SET_CPSR_MODE(tmp, mode) \ 352 mrs tmp, cpsr; /* Get the CPSR */ \ 353 bic tmp, tmp, #(PSR_MODE); /* Fix for SVC mode */ \ 354 orr tmp, tmp, #(mode); \ 355 msr cpsr_c, tmp /* Punch into SVC mode */ 356 #endif 357 358 #define PUSHFRAMEINSVC \ 359 stmdb sp, {r0-r3}; /* Save 4 registers */ \ 360 mov r0, lr; /* Save xxx32 r14 */ \ 361 mov r1, sp; /* Save xxx32 sp */ \ 362 mrs r3, spsr; /* Save xxx32 spsr */ \ 363 SET_CPSR_MODE(r2, PSR_SVC32_MODE); \ 364 mov r2, sp; /* Save SVC sp */ \ 365 str r0, [sp, #-4]!; /* Push return address */ \ 366 str lr, [sp, #-4]!; /* Push SVC lr */ \ 367 str r2, [sp, #-4]!; /* Push SVC sp */ \ 368 sub sp, sp, #4; /* Keep stack aligned */ \ 369 msr spsr_all, r3; /* Restore correct spsr */ \ 370 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ 371 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \ 372 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 373 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 374 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 375 mov r0, r0; /* NOP for previous instruction */ \ 376 mrs r0, spsr_all; /* Get the SPSR */ \ 377 str r0, [sp, #-4]! /* Push the SPSR onto the stack */ 378 379 /* 380 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack 381 * in SVC32 mode and restore the saved processor mode and PC. 382 * This should be used when the SVC lr register needs to be restored on 383 * exit. 384 */ 385 386 #define PULLFRAMEFROMSVCANDEXIT \ 387 ldr r0, [sp], #0x0004; /* Pop the SPSR from stack */ \ 388 msr spsr_all, r0; /* restore SPSR */ \ 389 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 390 mov r0, r0; /* NOP for previous instruction */ \ 391 add sp, sp, #(4*16); /* Adjust the stack pointer */ \ 392 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ 393 394 #endif /* _LOCORE */ 395 396 #endif /* _ARM32_FRAME_H_ */ 397
Indexes created Thu Sep 25 16:09:42 GMT 2025