frame.h revision 1.29
1 /* $NetBSD: frame.h,v 1.29 2012/08/01 22:46:07 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1997 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * frame.h 40 * 41 * Stack frames structures 42 * 43 * Created : 30/09/94 44 */ 45 46 #ifndef _ARM32_FRAME_H_ 47 #define _ARM32_FRAME_H_ 48 49 #include <arm/frame.h> /* Common ARM stack frames */ 50 51 #ifndef _LOCORE 52 53 /* 54 * System stack frames. 55 */ 56 57 typedef struct irqframe { 58 unsigned int if_spsr; 59 unsigned int if_fill; /* fill here so r0 will dword aligned */ 60 unsigned int if_r0; 61 unsigned int if_r1; 62 unsigned int if_r2; 63 unsigned int if_r3; 64 unsigned int if_r4; 65 unsigned int if_r5; 66 unsigned int if_r6; 67 unsigned int if_r7; 68 unsigned int if_r8; 69 unsigned int if_r9; 70 unsigned int if_r10; 71 unsigned int if_r11; 72 unsigned int if_r12; 73 unsigned int if_usr_sp; 74 unsigned int if_usr_lr; 75 unsigned int if_svc_sp; 76 unsigned int if_svc_lr; 77 unsigned int if_pc; 78 } irqframe_t; 79 80 struct clockframe { 81 struct irqframe cf_if; 82 }; 83 84 /* 85 * Switch frame. 86 * 87 * Should be a multiple of 8 bytes for dumpsys. 88 */ 89 90 struct switchframe { 91 u_int sf_r4; 92 u_int sf_r5; 93 u_int sf_r6; 94 u_int sf_r7; 95 u_int sf_sp; 96 u_int sf_pc; 97 }; 98 99 /* 100 * Stack frame. Used during stack traces (db_trace.c) 101 */ 102 struct frame { 103 u_int fr_fp; 104 u_int fr_sp; 105 u_int fr_lr; 106 u_int fr_pc; 107 }; 108 109 #ifdef _KERNEL 110 void validate_trapframe(trapframe_t *, int); 111 #endif /* _KERNEL */ 112 113 #else /* _LOCORE */ 114 115 #include "opt_compat_netbsd.h" 116 #include "opt_execfmt.h" 117 #include "opt_multiprocessor.h" 118 #include "opt_cpuoptions.h" 119 #include "opt_arm_debug.h" 120 #include "opt_cputypes.h" 121 122 #include <machine/cpu.h> 123 124 /* 125 * This macro is used by DO_AST_AND_RESTORE_ALIGNMENT_FAULTS to process 126 * any pending softints. 127 */ 128 #ifdef __HAVE_FAST_SOFTINTS 129 #define DO_PENDING_SOFTINTS \ 130 ldr r0, [r4, #CI_INTR_DEPTH]/* Get current intr depth */ ;\ 131 teq r0, #0 /* Test for 0. */ ;\ 132 bne 10f /* skip softints if != 0 */ ;\ 133 ldr r0, [r4, #CI_CPL] /* Get current priority level */;\ 134 ldr r1, [r4, #CI_SOFTINTS] /* Get pending softint mask */ ;\ 135 movs r0, r1, lsr r0 /* shift mask by cpl */ ;\ 136 blne _C_LABEL(dosoftints) /* dosoftints(void) */ ;\ 137 10: 138 #else 139 #define DO_PENDING_SOFTINTS /* nothing */ 140 #endif 141 142 /* 143 * AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS 144 * These are used in order to support dynamic enabling/disabling of 145 * alignment faults when executing old a.out ARM binaries. 146 * 147 * Note that when ENABLE_ALIGNMENTS_FAULTS finishes r4 will contain 148 * pointer to the cpu's cpu_info. DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 149 * relies on r4 being preserved. 150 */ 151 #ifdef EXEC_AOUT 152 #define AST_ALIGNMENT_FAULT_LOCALS \ 153 .Laflt_cpufuncs: ;\ 154 .word _C_LABEL(cpufuncs) 155 156 /* 157 * This macro must be invoked following PUSHFRAMEINSVC or PUSHFRAME at 158 * the top of interrupt/exception handlers. 159 * 160 * When invoked, r0 *must* contain the value of SPSR on the current 161 * trap/interrupt frame. This is always the case if ENABLE_ALIGNMENT_FAULTS 162 * is invoked immediately after PUSHFRAMEINSVC or PUSHFRAME. 163 */ 164 #define ENABLE_ALIGNMENT_FAULTS \ 165 and r0, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\ 166 teq r0, #(PSR_USR32_MODE) ;\ 167 GET_CURCPU(r4) /* r4 = cpuinfo */ ;\ 168 bne 1f /* Not USR mode skip AFLT */ ;\ 169 ldr r1, [r4, #CI_CURPCB] /* get curpcb from cpu_info */ ;\ 170 ldr r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\ 171 tst r1, #PCB_NOALIGNFLT ;\ 172 beq 1f /* AFLTs already enabled */ ;\ 173 ldr r2, .Laflt_cpufuncs ;\ 174 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\ 175 mov r0, #-1 ;\ 176 mov lr, pc ;\ 177 ldr pc, [r2, #CF_CONTROL] /* Enable alignment faults */ ;\ 178 1: 179 180 /* 181 * This macro must be invoked just before PULLFRAMEFROMSVCANDEXIT or 182 * PULLFRAME at the end of interrupt/exception handlers. We know that 183 * r4 points to cpu_info since that is what ENABLE_ALIGNMENT_FAULTS did 184 * for use. 185 */ 186 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 187 DO_PENDING_SOFTINTS ;\ 188 ldr r0, [sp] /* Get the SPSR from stack */ ;\ 189 mrs r5, cpsr /* save CPSR */ ;\ 190 orr r1, r5, #(IF32_bits) ;\ 191 msr cpsr_c, r1 /* Disable interrupts */ ;\ 192 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ 193 teq r0, #(PSR_USR32_MODE) ;\ 194 bne 3f /* Nope, get out now */ ;\ 195 1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\ 196 teq r1, #0x00000000 ;\ 197 bne 2f /* Yup. Go deal with it */ ;\ 198 ldr r1, [r4, #CI_CURPCB] /* Get current PCB */ ;\ 199 ldr r0, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\ 200 tst r0, #PCB_NOALIGNFLT ;\ 201 beq 3f /* Keep AFLTs enabled */ ;\ 202 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\ 203 ldr r2, .Laflt_cpufuncs ;\ 204 mov r0, #-1 ;\ 205 bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable AFLTs */ ;\ 206 adr lr, 3f ;\ 207 ldr pc, [r2, #CF_CONTROL] /* Set new CTRL reg value */ ;\ 208 /* NOTREACHED */ \ 209 2: mov r1, #0x00000000 ;\ 210 str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\ 211 bic r5, r5, #(IF32_bits) ;\ 212 msr cpsr_c, r5 /* Restore interrupts */ ;\ 213 mov r0, sp ;\ 214 bl _C_LABEL(ast) /* ast(frame) */ ;\ 215 orr r0, r5, #(IF32_bits) /* Disable IRQs */ ;\ 216 msr cpsr_c, r0 ;\ 217 b 1b /* Back around again */ ;\ 218 3: 219 220 #else /* !EXEC_AOUT */ 221 222 #define AST_ALIGNMENT_FAULT_LOCALS 223 224 #define ENABLE_ALIGNMENT_FAULTS GET_CURCPU(r4) 225 226 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 227 DO_PENDING_SOFTINTS ;\ 228 ldr r0, [sp] /* Get the SPSR from stack */ ;\ 229 mrs r5, cpsr /* save CPSR */ ;\ 230 orr r1, r5, #(IF32_bits) ;\ 231 msr cpsr_c, r1 /* Disable interrupts */ ;\ 232 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ 233 teq r0, #(PSR_USR32_MODE) ;\ 234 bne 2f /* Nope, get out now */ ;\ 235 1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\ 236 teq r1, #0x00000000 ;\ 237 beq 2f /* Nope. Just bail */ ;\ 238 mov r1, #0x00000000 ;\ 239 str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\ 240 bic r5, r5, #(IF32_bits) ;\ 241 msr cpsr_c, r5 /* Restore interrupts */ ;\ 242 mov r0, sp ;\ 243 bl _C_LABEL(ast) /* ast(frame) */ ;\ 244 orr r0, r5, #(IF32_bits) /* Disable IRQs */ ;\ 245 msr cpsr_c, r0 ;\ 246 b 1b ;\ 247 2: 248 #endif /* EXEC_AOUT */ 249 250 #ifdef ARM_LOCK_CAS_DEBUG 251 #define LOCK_CAS_DEBUG_LOCALS \ 252 .L_lock_cas_restart: ;\ 253 .word _C_LABEL(_lock_cas_restart) 254 255 #if defined(__ARMEB__) 256 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 257 ble 99f ;\ 258 ldr r0, .L_lock_cas_restart ;\ 259 ldmia r0, {r1-r2} /* load ev_count */ ;\ 260 adds r2, r2, #1 /* 64-bit incr (lo) */ ;\ 261 adc r1, r1, #0 /* 64-bit incr (hi) */ ;\ 262 stmia r0, {r1-r2} /* store ev_count */ 263 #else /* __ARMEB__ */ 264 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 265 ble 99f ;\ 266 ldr r0, .L_lock_cas_restart ;\ 267 ldmia r0, {r1-r2} /* load ev_count */ ;\ 268 adds r1, r1, #1 /* 64-bit incr (lo) */ ;\ 269 adc r2, r2, #0 /* 64-bit incr (hi) */ ;\ 270 stmia r0, {r1-r2} /* store ev_count */ 271 #endif /* __ARMEB__ */ 272 #else /* ARM_LOCK_CAS_DEBUG */ 273 #define LOCK_CAS_DEBUG_LOCALS /* nothing */ 274 #define LOCK_CAS_DEBUG_COUNT_RESTART /* nothing */ 275 #endif /* ARM_LOCK_CAS_DEBUG */ 276 277 #define LOCK_CAS_CHECK_LOCALS \ 278 .L_lock_cas: ;\ 279 .word _C_LABEL(_lock_cas) ;\ 280 .L_lock_cas_end: ;\ 281 .word _C_LABEL(_lock_cas_end) ;\ 282 LOCK_CAS_DEBUG_LOCALS 283 284 #define LOCK_CAS_CHECK \ 285 ldr r0, [sp] /* get saved PSR */ ;\ 286 and r0, r0, #(PSR_MODE) /* check for SVC32 mode */ ;\ 287 teq r0, #(PSR_SVC32_MODE) ;\ 288 bne 99f /* nope, get out now */ ;\ 289 ldr r0, [sp, #(IF_PC)] ;\ 290 ldr r1, .L_lock_cas_end ;\ 291 cmp r0, r1 ;\ 292 bge 99f ;\ 293 ldr r1, .L_lock_cas ;\ 294 cmp r0, r1 ;\ 295 strgt r1, [sp, #(IF_PC)] ;\ 296 LOCK_CAS_DEBUG_COUNT_RESTART ;\ 297 99: 298 299 /* 300 * ASM macros for pushing and pulling trapframes from the stack 301 * 302 * These macros are used to handle the irqframe and trapframe structures 303 * defined above. 304 */ 305 306 /* 307 * PUSHFRAME - macro to push a trap frame on the stack in the current mode 308 * Since the current mode is used, the SVC lr field is not defined. 309 */ 310 311 #ifdef CPU_SA110 312 /* 313 * NOTE: r13 and r14 are stored separately as a work around for the 314 * SA110 rev 2 STM^ bug 315 */ 316 #define PUSHUSERREGS \ 317 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 318 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 319 stmia r0, {r13-r14}^ /* Push the user mode registers */ 320 #else 321 #define PUSHUSERREGS \ 322 stmia sp, {r0-r14}^ /* Push the user mode registers */ 323 #endif 324 325 #define PUSHFRAME \ 326 str lr, [sp, #-4]!; /* Push the return address */ \ 327 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \ 328 PUSHUSERREGS; /* Push the user mode registers */ \ 329 mov r0, r0; /* NOP for previous instruction */ \ 330 mrs r0, spsr_all; /* Get the SPSR */ \ 331 str r0, [sp, #-8]! /* Push the SPSR on the stack */ 332 333 /* 334 * PULLFRAME - macro to pull a trap frame from the stack in the current mode 335 * Since the current mode is used, the SVC lr field is ignored. 336 */ 337 338 #define PULLFRAME \ 339 ldr r0, [sp], #0x0008; /* Pop the SPSR from stack */ \ 340 msr spsr_all, r0; \ 341 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 342 mov r0, r0; /* NOP for previous instruction */ \ 343 add sp, sp, #(4*17); /* Adjust the stack pointer */ \ 344 ldr lr, [sp], #0x0004 /* Pop the return address */ 345 346 /* 347 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode 348 * This should only be used if the processor is not currently in SVC32 349 * mode. The processor mode is switched to SVC mode and the trap frame is 350 * stored. The SVC lr field is used to store the previous value of 351 * lr in SVC mode. 352 * 353 * NOTE: r13 and r14 are stored separately as a work around for the 354 * SA110 rev 2 STM^ bug 355 */ 356 357 #ifdef _ARM_ARCH_6 358 #define SET_CPSR_MODE(tmp, mode) \ 359 cps #(mode) 360 #else 361 #define SET_CPSR_MODE(tmp, mode) \ 362 mrs tmp, cpsr; /* Get the CPSR */ \ 363 bic tmp, tmp, #(PSR_MODE); /* Fix for SVC mode */ \ 364 orr tmp, tmp, #(mode); \ 365 msr cpsr_c, tmp /* Punch into SVC mode */ 366 #endif 367 368 #define PUSHFRAMEINSVC \ 369 stmdb sp, {r0-r3}; /* Save 4 registers */ \ 370 mov r0, lr; /* Save xxx32 r14 */ \ 371 mov r1, sp; /* Save xxx32 sp */ \ 372 mrs r3, spsr; /* Save xxx32 spsr */ \ 373 SET_CPSR_MODE(r2, PSR_SVC32_MODE); \ 374 bic r2, sp, #7; /* Align new SVC sp */ \ 375 str r0, [r2, #-4]!; /* Push return address */ \ 376 stmdb r2!, {sp, lr}; /* Push SVC sp, lr */ \ 377 mov sp, r2; /* Keep stack aligned */ \ 378 msr spsr_all, r3; /* Restore correct spsr */ \ 379 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ 380 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \ 381 PUSHUSERREGS; /* Push the user mode registers */ \ 382 mov r0, r0; /* NOP for previous instruction */ \ 383 mrs r0, spsr_all; /* Get the SPSR */ \ 384 str r0, [sp, #-8]! /* Push the SPSR onto the stack */ 385 386 /* 387 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack 388 * in SVC32 mode and restore the saved processor mode and PC. 389 * This should be used when the SVC lr register needs to be restored on 390 * exit. 391 */ 392 393 #define PULLFRAMEFROMSVCANDEXIT \ 394 ldr r0, [sp], #0x0008; /* Pop the SPSR from stack */ \ 395 msr spsr_all, r0; /* restore SPSR */ \ 396 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 397 mov r0, r0; /* NOP for previous instruction */ \ 398 add sp, sp, #(4*15); /* Adjust the stack pointer */ \ 399 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ 400 401 #endif /* _LOCORE */ 402 403 #endif /* _ARM32_FRAME_H_ */ 404
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