frame.h revision 1.30
1 /* $NetBSD: frame.h,v 1.30 2012/08/02 15:56:07 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1997 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * frame.h 40 * 41 * Stack frames structures 42 * 43 * Created : 30/09/94 44 */ 45 46 #ifndef _ARM32_FRAME_H_ 47 #define _ARM32_FRAME_H_ 48 49 #include <arm/frame.h> /* Common ARM stack frames */ 50 51 #ifndef _LOCORE 52 53 /* 54 * System stack frames. 55 */ 56 57 struct clockframe { 58 struct trapframe cf_tf; 59 }; 60 61 /* 62 * Switch frame. 63 * 64 * Should be a multiple of 8 bytes for dumpsys. 65 */ 66 67 struct switchframe { 68 u_int sf_r4; 69 u_int sf_r5; 70 u_int sf_r6; 71 u_int sf_r7; 72 u_int sf_sp; 73 u_int sf_pc; 74 }; 75 76 /* 77 * Stack frame. Used during stack traces (db_trace.c) 78 */ 79 struct frame { 80 u_int fr_fp; 81 u_int fr_sp; 82 u_int fr_lr; 83 u_int fr_pc; 84 }; 85 86 #ifdef _KERNEL 87 void validate_trapframe(trapframe_t *, int); 88 #endif /* _KERNEL */ 89 90 #else /* _LOCORE */ 91 92 #include "opt_compat_netbsd.h" 93 #include "opt_execfmt.h" 94 #include "opt_multiprocessor.h" 95 #include "opt_cpuoptions.h" 96 #include "opt_arm_debug.h" 97 #include "opt_cputypes.h" 98 99 #include <machine/cpu.h> 100 101 /* 102 * This macro is used by DO_AST_AND_RESTORE_ALIGNMENT_FAULTS to process 103 * any pending softints. 104 */ 105 #ifdef __HAVE_FAST_SOFTINTS 106 #define DO_PENDING_SOFTINTS \ 107 ldr r0, [r4, #CI_INTR_DEPTH]/* Get current intr depth */ ;\ 108 teq r0, #0 /* Test for 0. */ ;\ 109 bne 10f /* skip softints if != 0 */ ;\ 110 ldr r0, [r4, #CI_CPL] /* Get current priority level */;\ 111 ldr r1, [r4, #CI_SOFTINTS] /* Get pending softint mask */ ;\ 112 movs r0, r1, lsr r0 /* shift mask by cpl */ ;\ 113 blne _C_LABEL(dosoftints) /* dosoftints(void) */ ;\ 114 10: 115 #else 116 #define DO_PENDING_SOFTINTS /* nothing */ 117 #endif 118 119 /* 120 * AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS 121 * These are used in order to support dynamic enabling/disabling of 122 * alignment faults when executing old a.out ARM binaries. 123 * 124 * Note that when ENABLE_ALIGNMENTS_FAULTS finishes r4 will contain 125 * pointer to the cpu's cpu_info. DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 126 * relies on r4 being preserved. 127 */ 128 #ifdef EXEC_AOUT 129 #define AST_ALIGNMENT_FAULT_LOCALS \ 130 .Laflt_cpufuncs: ;\ 131 .word _C_LABEL(cpufuncs) 132 133 /* 134 * This macro must be invoked following PUSHFRAMEINSVC or PUSHFRAME at 135 * the top of interrupt/exception handlers. 136 * 137 * When invoked, r0 *must* contain the value of SPSR on the current 138 * trap/interrupt frame. This is always the case if ENABLE_ALIGNMENT_FAULTS 139 * is invoked immediately after PUSHFRAMEINSVC or PUSHFRAME. 140 */ 141 #define ENABLE_ALIGNMENT_FAULTS \ 142 and r0, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\ 143 teq r0, #(PSR_USR32_MODE) ;\ 144 GET_CURCPU(r4) /* r4 = cpuinfo */ ;\ 145 bne 1f /* Not USR mode skip AFLT */ ;\ 146 ldr r1, [r4, #CI_CURPCB] /* get curpcb from cpu_info */ ;\ 147 ldr r1, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\ 148 tst r1, #PCB_NOALIGNFLT ;\ 149 beq 1f /* AFLTs already enabled */ ;\ 150 ldr r2, .Laflt_cpufuncs ;\ 151 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\ 152 mov r0, #-1 ;\ 153 mov lr, pc ;\ 154 ldr pc, [r2, #CF_CONTROL] /* Enable alignment faults */ ;\ 155 1: 156 157 /* 158 * This macro must be invoked just before PULLFRAMEFROMSVCANDEXIT or 159 * PULLFRAME at the end of interrupt/exception handlers. We know that 160 * r4 points to cpu_info since that is what ENABLE_ALIGNMENT_FAULTS did 161 * for use. 162 */ 163 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 164 DO_PENDING_SOFTINTS ;\ 165 ldr r0, [sp] /* Get the SPSR from stack */ ;\ 166 mrs r5, cpsr /* save CPSR */ ;\ 167 orr r1, r5, #(IF32_bits) ;\ 168 msr cpsr_c, r1 /* Disable interrupts */ ;\ 169 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ 170 teq r0, #(PSR_USR32_MODE) ;\ 171 bne 3f /* Nope, get out now */ ;\ 172 1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\ 173 teq r1, #0x00000000 ;\ 174 bne 2f /* Yup. Go deal with it */ ;\ 175 ldr r1, [r4, #CI_CURPCB] /* Get current PCB */ ;\ 176 ldr r0, [r1, #PCB_FLAGS] /* Fetch curpcb->pcb_flags */ ;\ 177 tst r0, #PCB_NOALIGNFLT ;\ 178 beq 3f /* Keep AFLTs enabled */ ;\ 179 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\ 180 ldr r2, .Laflt_cpufuncs ;\ 181 mov r0, #-1 ;\ 182 bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable AFLTs */ ;\ 183 adr lr, 3f ;\ 184 ldr pc, [r2, #CF_CONTROL] /* Set new CTRL reg value */ ;\ 185 /* NOTREACHED */ \ 186 2: mov r1, #0x00000000 ;\ 187 str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\ 188 bic r5, r5, #(IF32_bits) ;\ 189 msr cpsr_c, r5 /* Restore interrupts */ ;\ 190 mov r0, sp ;\ 191 bl _C_LABEL(ast) /* ast(frame) */ ;\ 192 orr r0, r5, #(IF32_bits) /* Disable IRQs */ ;\ 193 msr cpsr_c, r0 ;\ 194 b 1b /* Back around again */ ;\ 195 3: 196 197 #else /* !EXEC_AOUT */ 198 199 #define AST_ALIGNMENT_FAULT_LOCALS 200 201 #define ENABLE_ALIGNMENT_FAULTS GET_CURCPU(r4) 202 203 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 204 DO_PENDING_SOFTINTS ;\ 205 ldr r0, [sp] /* Get the SPSR from stack */ ;\ 206 mrs r5, cpsr /* save CPSR */ ;\ 207 orr r1, r5, #(IF32_bits) ;\ 208 msr cpsr_c, r1 /* Disable interrupts */ ;\ 209 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ 210 teq r0, #(PSR_USR32_MODE) ;\ 211 bne 2f /* Nope, get out now */ ;\ 212 1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\ 213 teq r1, #0x00000000 ;\ 214 beq 2f /* Nope. Just bail */ ;\ 215 mov r1, #0x00000000 ;\ 216 str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\ 217 bic r5, r5, #(IF32_bits) ;\ 218 msr cpsr_c, r5 /* Restore interrupts */ ;\ 219 mov r0, sp ;\ 220 bl _C_LABEL(ast) /* ast(frame) */ ;\ 221 orr r0, r5, #(IF32_bits) /* Disable IRQs */ ;\ 222 msr cpsr_c, r0 ;\ 223 b 1b ;\ 224 2: 225 #endif /* EXEC_AOUT */ 226 227 #ifdef ARM_LOCK_CAS_DEBUG 228 #define LOCK_CAS_DEBUG_LOCALS \ 229 .L_lock_cas_restart: ;\ 230 .word _C_LABEL(_lock_cas_restart) 231 232 #if defined(__ARMEB__) 233 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 234 ble 99f ;\ 235 ldr r0, .L_lock_cas_restart ;\ 236 ldmia r0, {r1-r2} /* load ev_count */ ;\ 237 adds r2, r2, #1 /* 64-bit incr (lo) */ ;\ 238 adc r1, r1, #0 /* 64-bit incr (hi) */ ;\ 239 stmia r0, {r1-r2} /* store ev_count */ 240 #else /* __ARMEB__ */ 241 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 242 ble 99f ;\ 243 ldr r0, .L_lock_cas_restart ;\ 244 ldmia r0, {r1-r2} /* load ev_count */ ;\ 245 adds r1, r1, #1 /* 64-bit incr (lo) */ ;\ 246 adc r2, r2, #0 /* 64-bit incr (hi) */ ;\ 247 stmia r0, {r1-r2} /* store ev_count */ 248 #endif /* __ARMEB__ */ 249 #else /* ARM_LOCK_CAS_DEBUG */ 250 #define LOCK_CAS_DEBUG_LOCALS /* nothing */ 251 #define LOCK_CAS_DEBUG_COUNT_RESTART /* nothing */ 252 #endif /* ARM_LOCK_CAS_DEBUG */ 253 254 #define LOCK_CAS_CHECK_LOCALS \ 255 .L_lock_cas: ;\ 256 .word _C_LABEL(_lock_cas) ;\ 257 .L_lock_cas_end: ;\ 258 .word _C_LABEL(_lock_cas_end) ;\ 259 LOCK_CAS_DEBUG_LOCALS 260 261 #define LOCK_CAS_CHECK \ 262 ldr r0, [sp] /* get saved PSR */ ;\ 263 and r0, r0, #(PSR_MODE) /* check for SVC32 mode */ ;\ 264 teq r0, #(PSR_SVC32_MODE) ;\ 265 bne 99f /* nope, get out now */ ;\ 266 ldr r0, [sp, #(TF_PC)] ;\ 267 ldr r1, .L_lock_cas_end ;\ 268 cmp r0, r1 ;\ 269 bge 99f ;\ 270 ldr r1, .L_lock_cas ;\ 271 cmp r0, r1 ;\ 272 strgt r1, [sp, #(TF_PC)] ;\ 273 LOCK_CAS_DEBUG_COUNT_RESTART ;\ 274 99: 275 276 /* 277 * ASM macros for pushing and pulling trapframes from the stack 278 * 279 * These macros are used to handle the trapframe structure defined above. 280 */ 281 282 /* 283 * PUSHFRAME - macro to push a trap frame on the stack in the current mode 284 * Since the current mode is used, the SVC lr field is not defined. 285 */ 286 287 #ifdef CPU_SA110 288 /* 289 * NOTE: r13 and r14 are stored separately as a work around for the 290 * SA110 rev 2 STM^ bug 291 */ 292 #define PUSHUSERREGS \ 293 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 294 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 295 stmia r0, {r13-r14}^ /* Push the user mode registers */ 296 #else 297 #define PUSHUSERREGS \ 298 stmia sp, {r0-r14}^ /* Push the user mode registers */ 299 #endif 300 301 #define PUSHFRAME \ 302 str lr, [sp, #-4]!; /* Push the return address */ \ 303 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \ 304 PUSHUSERREGS; /* Push the user mode registers */ \ 305 mov r0, r0; /* NOP for previous instruction */ \ 306 mrs r0, spsr_all; /* Get the SPSR */ \ 307 str r0, [sp, #-8]! /* Push the SPSR on the stack */ 308 309 /* 310 * PULLFRAME - macro to pull a trap frame from the stack in the current mode 311 * Since the current mode is used, the SVC lr field is ignored. 312 */ 313 314 #define PULLFRAME \ 315 ldr r0, [sp], #0x0008; /* Pop the SPSR from stack */ \ 316 msr spsr_all, r0; \ 317 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 318 mov r0, r0; /* NOP for previous instruction */ \ 319 add sp, sp, #(4*17); /* Adjust the stack pointer */ \ 320 ldr lr, [sp], #0x0004 /* Pop the return address */ 321 322 /* 323 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode 324 * This should only be used if the processor is not currently in SVC32 325 * mode. The processor mode is switched to SVC mode and the trap frame is 326 * stored. The SVC lr field is used to store the previous value of 327 * lr in SVC mode. 328 * 329 * NOTE: r13 and r14 are stored separately as a work around for the 330 * SA110 rev 2 STM^ bug 331 */ 332 333 #ifdef _ARM_ARCH_6 334 #define SET_CPSR_MODE(tmp, mode) \ 335 cps #(mode) 336 #else 337 #define SET_CPSR_MODE(tmp, mode) \ 338 mrs tmp, cpsr; /* Get the CPSR */ \ 339 bic tmp, tmp, #(PSR_MODE); /* Fix for SVC mode */ \ 340 orr tmp, tmp, #(mode); \ 341 msr cpsr_c, tmp /* Punch into SVC mode */ 342 #endif 343 344 #define PUSHFRAMEINSVC \ 345 stmdb sp, {r0-r3}; /* Save 4 registers */ \ 346 mov r0, lr; /* Save xxx32 r14 */ \ 347 mov r1, sp; /* Save xxx32 sp */ \ 348 mrs r3, spsr; /* Save xxx32 spsr */ \ 349 SET_CPSR_MODE(r2, PSR_SVC32_MODE); \ 350 bic r2, sp, #7; /* Align new SVC sp */ \ 351 str r0, [r2, #-4]!; /* Push return address */ \ 352 stmdb r2!, {sp, lr}; /* Push SVC sp, lr */ \ 353 mov sp, r2; /* Keep stack aligned */ \ 354 msr spsr_all, r3; /* Restore correct spsr */ \ 355 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ 356 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \ 357 PUSHUSERREGS; /* Push the user mode registers */ \ 358 mov r0, r0; /* NOP for previous instruction */ \ 359 mrs r0, spsr_all; /* Get the SPSR */ \ 360 str r0, [sp, #-8]! /* Push the SPSR onto the stack */ 361 362 /* 363 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack 364 * in SVC32 mode and restore the saved processor mode and PC. 365 * This should be used when the SVC lr register needs to be restored on 366 * exit. 367 */ 368 369 #define PULLFRAMEFROMSVCANDEXIT \ 370 ldr r0, [sp], #0x0008; /* Pop the SPSR from stack */ \ 371 msr spsr_all, r0; /* restore SPSR */ \ 372 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 373 mov r0, r0; /* NOP for previous instruction */ \ 374 add sp, sp, #(4*15); /* Adjust the stack pointer */ \ 375 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ 376 377 #endif /* _LOCORE */ 378 379 #endif /* _ARM32_FRAME_H_ */ 380
Indexes created Thu Sep 25 16:09:42 GMT 2025