frame.h revision 1.37
1 /* $NetBSD: frame.h,v 1.37 2013/12/02 18:36:10 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1997 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * frame.h 40 * 41 * Stack frames structures 42 * 43 * Created : 30/09/94 44 */ 45 46 #ifndef _ARM32_FRAME_H_ 47 #define _ARM32_FRAME_H_ 48 49 #include <arm/frame.h> /* Common ARM stack frames */ 50 51 #ifndef _LOCORE 52 53 /* 54 * Switch frame. 55 * 56 * Should be a multiple of 8 bytes for dumpsys. 57 */ 58 59 struct switchframe { 60 u_int sf_r4; 61 u_int sf_r5; 62 u_int sf_r6; 63 u_int sf_r7; 64 u_int sf_sp; 65 u_int sf_pc; 66 }; 67 68 /* 69 * System stack frames. 70 */ 71 72 struct clockframe { 73 struct trapframe cf_tf; 74 }; 75 76 /* 77 * Stack frame. Used during stack traces (db_trace.c) 78 */ 79 struct frame { 80 u_int fr_fp; 81 u_int fr_sp; 82 u_int fr_lr; 83 u_int fr_pc; 84 }; 85 86 #ifdef _KERNEL 87 void validate_trapframe(trapframe_t *, int); 88 #endif /* _KERNEL */ 89 90 #else /* _LOCORE */ 91 92 #include "opt_compat_netbsd.h" 93 #include "opt_execfmt.h" 94 #include "opt_multiprocessor.h" 95 #include "opt_cpuoptions.h" 96 #include "opt_arm_debug.h" 97 #include "opt_cputypes.h" 98 99 #include <arm/locore.h> 100 101 /* 102 * This macro is used by DO_AST_AND_RESTORE_ALIGNMENT_FAULTS to process 103 * any pending softints. 104 */ 105 #ifdef _ARM_ARCH_4T 106 #define B_CF_CONTROL(rX) ;\ 107 ldr ip, [rX, #CF_CONTROL] /* get function addr */ ;\ 108 bx ip /* branch to cpu_control */ 109 #else 110 #define B_CF_CONTROL(rX) ;\ 111 ldr pc, [rX, #CF_CONTROL] /* branch to cpu_control */ 112 #endif 113 #ifdef _ARM_ARCH_5T 114 #define BL_CF_CONTROL(rX) ;\ 115 ldr ip, [rX, #CF_CONTROL] /* get function addr */ ;\ 116 blx ip /* call cpu_control */ 117 #else 118 #define BL_CF_CONTROL(rX) ;\ 119 mov lr, pc ;\ 120 ldr pc, [rX, #CF_CONTROL] /* call cpu_control */ 121 #endif 122 #if defined(__HAVE_FAST_SOFTINTS) && !defined(__HAVE_PIC_FAST_SOFTINTS) 123 #define DO_PENDING_SOFTINTS \ 124 ldr r0, [r4, #CI_INTR_DEPTH]/* Get current intr depth */ ;\ 125 cmp r0, #0 /* Test for 0. */ ;\ 126 bne 10f /* skip softints if != 0 */ ;\ 127 ldr r0, [r4, #CI_CPL] /* Get current priority level */;\ 128 ldr r1, [r4, #CI_SOFTINTS] /* Get pending softint mask */ ;\ 129 lsrs r0, r1, r0 /* shift mask by cpl */ ;\ 130 blne _C_LABEL(dosoftints) /* dosoftints(void) */ ;\ 131 10: 132 #else 133 #define DO_PENDING_SOFTINTS /* nothing */ 134 #endif 135 136 #ifdef MULTIPROCESSOR 137 #define KERNEL_LOCK \ 138 mov r0, #1 ;\ 139 mov r1, #0 ;\ 140 bl _C_LABEL(_kernel_lock) 141 142 #define KERNEL_UNLOCK \ 143 mov r0, #1 ;\ 144 mov r1, #0 ;\ 145 mov r2, #0 ;\ 146 bl _C_LABEL(_kernel_unlock) 147 #else 148 #define KERNEL_LOCK /* nothing */ 149 #define KERNEL_UNLOCK /* nothing */ 150 #endif 151 152 #ifdef _ARM_ARCH_6 153 #define GET_CPSR(rb) /* nothing */ 154 #define CPSID_I(ra,rb) cpsid i 155 #define CPSIE_I(ra,rb) cpsie i 156 #else 157 #define GET_CPSR(rb) \ 158 mrs rb, cpsr /* fetch CPSR */ 159 160 #define CPSID_I(ra,rb) \ 161 orr ra, rb, #(IF32_bits) ;\ 162 msr cpsr_c, ra /* Disable interrupts */ 163 164 #define CPSIE_I(ra,rb) \ 165 bic ra, rb, #(IF32_bits) ;\ 166 msr cpsr_c, ra /* Restore interrupts */ 167 #endif 168 169 /* 170 * AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS 171 * These are used in order to support dynamic enabling/disabling of 172 * alignment faults when executing old a.out ARM binaries. 173 * 174 * Note that when ENABLE_ALIGNMENTS_FAULTS finishes r4 will contain 175 * pointer to the cpu's cpu_info. DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 176 * relies on r4 being preserved. 177 */ 178 #ifdef EXEC_AOUT 179 #define AST_ALIGNMENT_FAULT_LOCALS \ 180 .Laflt_cpufuncs: ;\ 181 .word _C_LABEL(cpufuncs) 182 183 /* 184 * This macro must be invoked following PUSHFRAMEINSVC or PUSHFRAME at 185 * the top of interrupt/exception handlers. 186 * 187 * When invoked, r0 *must* contain the value of SPSR on the current 188 * trap/interrupt frame. This is always the case if ENABLE_ALIGNMENT_FAULTS 189 * is invoked immediately after PUSHFRAMEINSVC or PUSHFRAME. 190 */ 191 #define ENABLE_ALIGNMENT_FAULTS \ 192 and r7, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\ 193 teq r7, #(PSR_USR32_MODE) ;\ 194 GET_CURCPU(r4) /* r4 = cpuinfo */ ;\ 195 bne 1f /* Not USR mode skip AFLT */ ;\ 196 ldr r1, [r4, #CI_CURLWP] /* get curlwp from cpu_info */ ;\ 197 ldr r1, [r1, #L_MD_FLAGS] /* Fetch l_md.md_flags */ ;\ 198 tst r1, #MDLWP_NOALIGNFLT ;\ 199 beq 1f /* AFLTs already enabled */ ;\ 200 ldr r2, .Laflt_cpufuncs ;\ 201 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\ 202 mov r0, #-1 ;\ 203 BL_CF_CONTROL(r2) /* Enable alignment faults */ ;\ 204 1: KERNEL_LOCK 205 206 /* 207 * This macro must be invoked just before PULLFRAMEFROMSVCANDEXIT or 208 * PULLFRAME at the end of interrupt/exception handlers. We know that 209 * r4 points to cpu_info since that is what ENABLE_ALIGNMENT_FAULTS did 210 * for use. 211 */ 212 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 213 DO_PENDING_SOFTINTS ;\ 214 GET_CPSR(r5) /* save CPSR */ ;\ 215 CPSID_I(r1, r5) /* Disable interrupts */ ;\ 216 teq r7, #(PSR_USR32_MODE) /* Returning to USR mode? */ ;\ 217 bne 3f /* Nope, get out now */ ;\ 218 1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\ 219 teq r1, #0x00000000 ;\ 220 bne 2f /* Yup. Go deal with it */ ;\ 221 ldr r1, [r4, #CI_CURLWP] /* get curlwp from cpu_info */ ;\ 222 ldr r0, [r1, #L_MD_FLAGS] /* get md_flags from lwp */ ;\ 223 tst r0, #MDLWP_NOALIGNFLT ;\ 224 beq 3f /* Keep AFLTs enabled */ ;\ 225 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\ 226 ldr r2, .Laflt_cpufuncs ;\ 227 mov r0, #-1 ;\ 228 bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable AFLTs */ ;\ 229 adr lr, 3f ;\ 230 B_CF_CONTROL(r2) /* Set new CTRL reg value */ ;\ 231 /* NOTREACHED */ \ 232 2: mov r1, #0x00000000 ;\ 233 str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\ 234 CPSIE_I(r5, r5) /* Restore interrupts */ ;\ 235 mov r0, sp ;\ 236 bl _C_LABEL(ast) /* ast(frame) */ ;\ 237 CPSID_I(r0, r5) /* Disable interrupts */ ;\ 238 b 1b /* Back around again */ ;\ 239 3: KERNEL_UNLOCK 240 241 #else /* !EXEC_AOUT */ 242 243 #define AST_ALIGNMENT_FAULT_LOCALS 244 245 #define ENABLE_ALIGNMENT_FAULTS \ 246 and r7, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\ 247 GET_CURCPU(r4) /* r4 = cpuinfo */ ;\ 248 KERNEL_LOCK 249 250 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 251 DO_PENDING_SOFTINTS ;\ 252 GET_CPSR(r5) /* save CPSR */ ;\ 253 CPSID_I(r1, r5) /* Disable interrupts */ ;\ 254 teq r7, #(PSR_USR32_MODE) ;\ 255 bne 2f /* Nope, get out now */ ;\ 256 1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\ 257 teq r1, #0x00000000 ;\ 258 beq 2f /* Nope. Just bail */ ;\ 259 mov r1, #0x00000000 ;\ 260 str r1, [r4, #CI_ASTPENDING] /* Clear astpending */ ;\ 261 CPSIE_I(r5, r5) /* Restore interrupts */ ;\ 262 mov r0, sp ;\ 263 bl _C_LABEL(ast) /* ast(frame) */ ;\ 264 CPSID_I(r0, r5) /* Disable interrupts */ ;\ 265 b 1b ;\ 266 2: KERNEL_UNLOCK /* unlock the kernel */ 267 #endif /* EXEC_AOUT */ 268 269 #ifndef _ARM_ARCH_6 270 #ifdef ARM_LOCK_CAS_DEBUG 271 #define LOCK_CAS_DEBUG_LOCALS \ 272 .L_lock_cas_restart: ;\ 273 .word _C_LABEL(_lock_cas_restart) 274 275 #if defined(__ARMEB__) 276 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 277 ble 99f ;\ 278 ldr r0, .L_lock_cas_restart ;\ 279 ldmia r0, {r1-r2} /* load ev_count */ ;\ 280 adds r2, r2, #1 /* 64-bit incr (lo) */ ;\ 281 adc r1, r1, #0 /* 64-bit incr (hi) */ ;\ 282 stmia r0, {r1-r2} /* store ev_count */ 283 #else /* __ARMEB__ */ 284 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 285 ble 99f ;\ 286 ldr r0, .L_lock_cas_restart ;\ 287 ldmia r0, {r1-r2} /* load ev_count */ ;\ 288 adds r1, r1, #1 /* 64-bit incr (lo) */ ;\ 289 adc r2, r2, #0 /* 64-bit incr (hi) */ ;\ 290 stmia r0, {r1-r2} /* store ev_count */ 291 #endif /* __ARMEB__ */ 292 #else /* ARM_LOCK_CAS_DEBUG */ 293 #define LOCK_CAS_DEBUG_LOCALS /* nothing */ 294 #define LOCK_CAS_DEBUG_COUNT_RESTART /* nothing */ 295 #endif /* ARM_LOCK_CAS_DEBUG */ 296 297 #define LOCK_CAS_CHECK_LOCALS \ 298 .L_lock_cas: ;\ 299 .word _C_LABEL(_lock_cas) ;\ 300 .L_lock_cas_end: ;\ 301 .word _C_LABEL(_lock_cas_end) ;\ 302 LOCK_CAS_DEBUG_LOCALS 303 304 #define LOCK_CAS_CHECK \ 305 ldr r0, [sp] /* get saved PSR */ ;\ 306 and r0, r0, #(PSR_MODE) /* check for SVC32 mode */ ;\ 307 teq r0, #(PSR_SVC32_MODE) ;\ 308 bne 99f /* nope, get out now */ ;\ 309 ldr r0, [sp, #(TF_PC)] ;\ 310 ldr r1, .L_lock_cas_end ;\ 311 cmp r0, r1 ;\ 312 bge 99f ;\ 313 ldr r1, .L_lock_cas ;\ 314 cmp r0, r1 ;\ 315 strgt r1, [sp, #(TF_PC)] ;\ 316 LOCK_CAS_DEBUG_COUNT_RESTART ;\ 317 99: 318 319 #else 320 #define LOCK_CAS_CHECK /* nothing */ 321 #define LOCK_CAS_CHECK_LOCALS /* nothing */ 322 #endif 323 324 /* 325 * ASM macros for pushing and pulling trapframes from the stack 326 * 327 * These macros are used to handle the trapframe structure defined above. 328 */ 329 330 /* 331 * PUSHFRAME - macro to push a trap frame on the stack in the current mode 332 * Since the current mode is used, the SVC lr field is not defined. 333 */ 334 335 #ifdef CPU_SA110 336 /* 337 * NOTE: r13 and r14 are stored separately as a work around for the 338 * SA110 rev 2 STM^ bug 339 */ 340 #define PUSHUSERREGS \ 341 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 342 add r0, sp, #(TF_USR_SP-TF_R0); /* Adjust the stack pointer */ \ 343 stmia r0, {r13-r14}^ /* Push the user mode registers */ 344 #else 345 #define PUSHUSERREGS \ 346 stmia sp, {r0-r14}^ /* Push the user mode registers */ 347 #endif 348 349 #define PUSHFRAME \ 350 str lr, [sp, #-4]!; /* Push the return address */ \ 351 sub sp, sp, #(TF_PC-TF_R0); /* Adjust the stack pointer */ \ 352 PUSHUSERREGS; /* Push the user mode registers */ \ 353 mov r0, r0; /* NOP for previous instruction */ \ 354 mrs r0, spsr; /* Get the SPSR */ \ 355 str r0, [sp, #-TF_R0]! /* Push the SPSR on the stack */ 356 357 /* 358 * Push a minimal trapframe so we can dispatch an interrupt from the 359 * idle loop. The only reason the idle loop wakes up is to dispatch 360 * interrupts so why take the avoid of a full exception when we can do 361 * something minimal. 362 */ 363 #define PUSHIDLEFRAME \ 364 str lr, [sp, #-4]!; /* save SVC32 lr */ \ 365 str r6, [sp, #(TF_R6-TF_PC)]!; /* save callee-saved r6 */ \ 366 str r4, [sp, #(TF_R4-TF_R6)]!; /* save callee-saved r4 */ \ 367 mrs r0, cpsr; /* Get the CPSR */ \ 368 str r0, [sp, #(-TF_R4)]! /* Push the CPSR on the stack */ 369 370 /* 371 * Push a trapframe to be used by cpu_switchto 372 */ 373 #define PUSHSWITCHFRAME(rX) \ 374 mov ip, sp; \ 375 sub sp, sp, #(TRAPFRAMESIZE-TF_R12); /* Adjust the stack pointer */ \ 376 push {r4-r11}; /* Push the callee saved registers */ \ 377 sub sp, sp, #TF_R4; /* reserve rest of trapframe */ \ 378 str ip, [sp, #TF_SVC_SP]; \ 379 str lr, [sp, #TF_SVC_LR]; \ 380 str lr, [sp, #TF_PC]; \ 381 mrs rX, cpsr; /* Get the CPSR */ \ 382 str rX, [sp, #TF_SPSR] /* save in trapframe */ 383 384 #define PUSHSWITCHFRAME1 \ 385 mov ip, sp; \ 386 sub sp, sp, #(TRAPFRAMESIZE-TF_R8); /* Adjust the stack pointer */ \ 387 push {r4-r7}; /* Push some of the callee saved registers */ \ 388 sub sp, sp, #TF_R4; /* reserve rest of trapframe */ \ 389 str ip, [sp, #TF_SVC_SP]; \ 390 str lr, [sp, #TF_SVC_LR]; \ 391 str lr, [sp, #TF_PC] 392 393 #if defined(_ARM_ARCH_DWORD_OK) && __ARM_EABI__ 394 #define PUSHSWITCHFRAME2 \ 395 strd r10, [sp, #TF_R10]; /* save r10 & r11 */ \ 396 strd r8, [sp, #TF_R8]; /* save r8 & r9 */ \ 397 mrs r0, cpsr; /* Get the CPSR */ \ 398 str r0, [sp, #TF_SPSR] /* save in trapframe */ 399 #else 400 #define PUSHSWITCHFRAME2 \ 401 add r0, sp, #TF_R8; /* get ptr to r8 and above */ \ 402 stmia r0, {r8-r11}; /* save rest of registers */ \ 403 mrs r0, cpsr; /* Get the CPSR */ \ 404 str r0, [sp, #TF_SPSR] /* save in trapframe */ 405 #endif 406 407 /* 408 * PULLFRAME - macro to pull a trap frame from the stack in the current mode 409 * Since the current mode is used, the SVC lr field is ignored. 410 */ 411 412 #define PULLFRAME \ 413 ldr r0, [sp], #TF_R0; /* Pop the SPSR from stack */ \ 414 msr spsr_all, r0; \ 415 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 416 mov r0, r0; /* NOP for previous instruction */ \ 417 add sp, sp, #(TF_PC-TF_R0); /* Adjust the stack pointer */ \ 418 ldr lr, [sp], #0x0004 /* Pop the return address */ 419 420 #define PULLIDLEFRAME \ 421 add sp, sp, #TF_R4; /* Adjust the stack pointer */ \ 422 ldr r4, [sp], #(TF_R6-TF_R4); /* restore callee-saved r4 */ \ 423 ldr r6, [sp], #(TF_PC-TF_R6); /* restore callee-saved r6 */ \ 424 ldr lr, [sp], #4 /* Pop the return address */ 425 426 /* 427 * Pop a trapframe to be used by cpu_switchto (don't touch r0 & r1). 428 */ 429 #define PULLSWITCHFRAME \ 430 add sp, sp, #TF_R4; /* Adjust the stack pointer */ \ 431 pop {r4-r11}; /* pop the callee saved registers */ \ 432 add sp, sp, #(TF_PC-TF_R12); /* Adjust the stack pointer */ \ 433 ldr lr, [sp], #4; /* pop the return address */ 434 435 /* 436 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode 437 * This should only be used if the processor is not currently in SVC32 438 * mode. The processor mode is switched to SVC mode and the trap frame is 439 * stored. The SVC lr field is used to store the previous value of 440 * lr in SVC mode. 441 * 442 * NOTE: r13 and r14 are stored separately as a work around for the 443 * SA110 rev 2 STM^ bug 444 */ 445 446 #ifdef _ARM_ARCH_6 447 #define SET_CPSR_MODE(tmp, mode) \ 448 cps #(mode) 449 #else 450 #define SET_CPSR_MODE(tmp, mode) \ 451 mrs tmp, cpsr; /* Get the CPSR */ \ 452 bic tmp, tmp, #(PSR_MODE); /* Fix for SVC mode */ \ 453 orr tmp, tmp, #(mode); \ 454 msr cpsr_c, tmp /* Punch into SVC mode */ 455 #endif 456 457 #define PUSHFRAMEINSVC \ 458 stmdb sp, {r0-r3}; /* Save 4 registers */ \ 459 mov r0, lr; /* Save xxx32 r14 */ \ 460 mov r1, sp; /* Save xxx32 sp */ \ 461 mrs r3, spsr; /* Save xxx32 spsr */ \ 462 SET_CPSR_MODE(r2, PSR_SVC32_MODE); \ 463 bic r2, sp, #7; /* Align new SVC sp */ \ 464 str r0, [r2, #-4]!; /* Push return address */ \ 465 stmdb r2!, {sp, lr}; /* Push SVC sp, lr */ \ 466 mov sp, r2; /* Keep stack aligned */ \ 467 msr spsr_all, r3; /* Restore correct spsr */ \ 468 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ 469 sub sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \ 470 PUSHUSERREGS; /* Push the user mode registers */ \ 471 mov r0, r0; /* NOP for previous instruction */ \ 472 mrs r0, spsr; /* Get the SPSR */ \ 473 str r0, [sp, #-TF_R0]! /* Push the SPSR onto the stack */ 474 475 /* 476 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack 477 * in SVC32 mode and restore the saved processor mode and PC. 478 * This should be used when the SVC lr register needs to be restored on 479 * exit. 480 */ 481 482 #define PULLFRAMEFROMSVCANDEXIT \ 483 ldr r0, [sp], #0x0008; /* Pop the SPSR from stack */ \ 484 msr spsr_all, r0; /* restore SPSR */ \ 485 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 486 mov r0, r0; /* NOP for previous instruction */ \ 487 add sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \ 488 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ 489 490 #endif /* _LOCORE */ 491 492 #endif /* _ARM32_FRAME_H_ */ 493
Indexes created Thu Sep 25 16:09:42 GMT 2025