frame.h revision 1.46
1 /* $NetBSD: frame.h,v 1.46 2018/10/28 14:45:02 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1997 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * frame.h 40 * 41 * Stack frames structures 42 * 43 * Created : 30/09/94 44 */ 45 46 #ifndef _ARM32_FRAME_H_ 47 #define _ARM32_FRAME_H_ 48 49 #include <arm/frame.h> /* Common ARM stack frames */ 50 51 #ifndef _LOCORE 52 53 /* 54 * Switch frame. 55 * 56 * Should be a multiple of 8 bytes for dumpsys. 57 */ 58 59 struct switchframe { 60 u_int sf_r4; 61 u_int sf_r5; 62 u_int sf_r6; 63 u_int sf_r7; 64 u_int sf_sp; 65 u_int sf_pc; 66 }; 67 68 /* 69 * System stack frames. 70 */ 71 72 struct clockframe { 73 struct trapframe cf_tf; 74 }; 75 76 /* 77 * Stack frame. Used during stack traces (db_trace.c) 78 */ 79 struct frame { 80 u_int fr_fp; 81 u_int fr_sp; 82 u_int fr_lr; 83 u_int fr_pc; 84 }; 85 86 #ifdef _KERNEL 87 void validate_trapframe(trapframe_t *, int); 88 #endif /* _KERNEL */ 89 90 #else /* _LOCORE */ 91 92 #include "opt_compat_netbsd.h" 93 #include "opt_execfmt.h" 94 #include "opt_multiprocessor.h" 95 #include "opt_cpuoptions.h" 96 #include "opt_arm_debug.h" 97 #include "opt_cputypes.h" 98 #include "opt_dtrace.h" 99 100 #include <arm/locore.h> 101 102 /* 103 * This macro is used by DO_AST_AND_RESTORE_ALIGNMENT_FAULTS to process 104 * any pending softints. 105 */ 106 #ifdef _ARM_ARCH_4T 107 #define B_CF_CONTROL(rX) ;\ 108 ldr ip, [rX, #CF_CONTROL] /* get function addr */ ;\ 109 bx ip /* branch to cpu_control */ 110 #else 111 #define B_CF_CONTROL(rX) ;\ 112 ldr pc, [rX, #CF_CONTROL] /* branch to cpu_control */ 113 #endif 114 #ifdef _ARM_ARCH_5T 115 #define BL_CF_CONTROL(rX) ;\ 116 ldr ip, [rX, #CF_CONTROL] /* get function addr */ ;\ 117 blx ip /* call cpu_control */ 118 #else 119 #define BL_CF_CONTROL(rX) ;\ 120 mov lr, pc ;\ 121 ldr pc, [rX, #CF_CONTROL] /* call cpu_control */ 122 #endif 123 #if defined(__HAVE_FAST_SOFTINTS) && !defined(__HAVE_PIC_FAST_SOFTINTS) 124 #define DO_PENDING_SOFTINTS \ 125 ldr r0, [r4, #CI_INTR_DEPTH]/* Get current intr depth */ ;\ 126 cmp r0, #0 /* Test for 0. */ ;\ 127 bne 10f /* skip softints if != 0 */ ;\ 128 ldr r0, [r4, #CI_CPL] /* Get current priority level */;\ 129 ldr r1, [r4, #CI_SOFTINTS] /* Get pending softint mask */ ;\ 130 lsrs r0, r1, r0 /* shift mask by cpl */ ;\ 131 blne _C_LABEL(dosoftints) /* dosoftints(void) */ ;\ 132 10: 133 #else 134 #define DO_PENDING_SOFTINTS /* nothing */ 135 #endif 136 137 #ifdef _ARM_ARCH_6 138 #define GET_CPSR(rb) /* nothing */ 139 #define CPSID_I(ra,rb) cpsid i 140 #define CPSIE_I(ra,rb) cpsie i 141 #else 142 #define GET_CPSR(rb) \ 143 mrs rb, cpsr /* fetch CPSR */ 144 145 #define CPSID_I(ra,rb) \ 146 orr ra, rb, #(IF32_bits) ;\ 147 msr cpsr_c, ra /* Disable interrupts */ 148 149 #define CPSIE_I(ra,rb) \ 150 bic ra, rb, #(IF32_bits) ;\ 151 msr cpsr_c, ra /* Restore interrupts */ 152 #endif 153 154 #ifdef __HAVE_PREEMPTION 155 #define DO_CLEAR_ASTPENDING \ 156 mvn r1, #1 /* complement of 1 */ ;\ 157 add r0, r4, #CI_ASTPENDING /* address of astpending */ ;\ 158 bl _C_LABEL(atomic_and_uint) /* clear AST */ 159 #else 160 #define DO_CLEAR_ASTPENDING \ 161 mov r0, #0 ;\ 162 str r0, [r4, #CI_ASTPENDING] /* clear AST */ 163 #endif 164 165 #define DO_PENDING_AST(lbl) ;\ 166 1: ldr r1, [r4, #CI_ASTPENDING] /* Pending AST? */ ;\ 167 tst r1, #0x00000001 ;\ 168 beq lbl /* Nope. Just bail */ ;\ 169 DO_CLEAR_ASTPENDING ;\ 170 CPSIE_I(r5, r5) /* Restore interrupts */ ;\ 171 mov r0, sp ;\ 172 bl _C_LABEL(ast) /* ast(frame) */ ;\ 173 CPSID_I(r0, r5) /* Disable interrupts */ ;\ 174 b 1b /* test again */ 175 176 /* 177 * AST_ALIGNMENT_FAULT_LOCALS and ENABLE_ALIGNMENT_FAULTS 178 * These are used in order to support dynamic enabling/disabling of 179 * alignment faults when executing old a.out ARM binaries. 180 * 181 * Note that when ENABLE_ALIGNMENTS_FAULTS finishes r4 will contain 182 * pointer to the cpu's cpu_info. DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 183 * relies on r4 being preserved. 184 */ 185 #ifdef EXEC_AOUT 186 #define AST_ALIGNMENT_FAULT_LOCALS \ 187 .Laflt_cpufuncs: ;\ 188 .word _C_LABEL(cpufuncs) 189 190 /* 191 * This macro must be invoked following PUSHFRAMEINSVC or PUSHFRAME at 192 * the top of interrupt/exception handlers. 193 * 194 * When invoked, r0 *must* contain the value of SPSR on the current 195 * trap/interrupt frame. This is always the case if ENABLE_ALIGNMENT_FAULTS 196 * is invoked immediately after PUSHFRAMEINSVC or PUSHFRAME. 197 */ 198 #define ENABLE_ALIGNMENT_FAULTS \ 199 and r7, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\ 200 cmp r7, #(PSR_USR32_MODE) ;\ 201 GET_CURCPU(r4) /* r4 = cpuinfo */ ;\ 202 bne 1f /* Not USR mode skip AFLT */ ;\ 203 ldr r1, [r4, #CI_CURLWP] /* get curlwp from cpu_info */ ;\ 204 ldr r1, [r1, #L_MD_FLAGS] /* Fetch l_md.md_flags */ ;\ 205 tst r1, #MDLWP_NOALIGNFLT ;\ 206 beq 1f /* AFLTs already enabled */ ;\ 207 ldr r2, .Laflt_cpufuncs ;\ 208 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\ 209 mov r0, #-1 ;\ 210 BL_CF_CONTROL(r2) /* Enable alignment faults */ ;\ 211 1: /* done */ 212 213 /* 214 * This macro must be invoked just before PULLFRAMEFROMSVCANDEXIT or 215 * PULLFRAME at the end of interrupt/exception handlers. We know that 216 * r4 points to cpu_info since that is what ENABLE_ALIGNMENT_FAULTS did 217 * for use. 218 */ 219 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 220 DO_PENDING_SOFTINTS ;\ 221 GET_CPSR(r5) /* save CPSR */ ;\ 222 CPSID_I(r1, r5) /* Disable interrupts */ ;\ 223 cmp r7, #(PSR_USR32_MODE) /* Returning to USR mode? */ ;\ 224 bne 3f /* Nope, get out now */ ;\ 225 DO_PENDING_AST(2f) /* Pending AST? */ ;\ 226 2: ldr r1, [r4, #CI_CURLWP] /* get curlwp from cpu_info */ ;\ 227 ldr r0, [r1, #L_MD_FLAGS] /* get md_flags from lwp */ ;\ 228 tst r0, #MDLWP_NOALIGNFLT ;\ 229 beq 3f /* Keep AFLTs enabled */ ;\ 230 ldr r1, [r4, #CI_CTRL] /* Fetch control register */ ;\ 231 ldr r2, .Laflt_cpufuncs ;\ 232 mov r0, #-1 ;\ 233 bic r1, r1, #CPU_CONTROL_AFLT_ENABLE /* Disable AFLTs */ ;\ 234 BL_CF_CONTROL(r2) /* Set new CTRL reg value */ ;\ 235 3: /* done */ 236 237 #else /* !EXEC_AOUT */ 238 239 #define AST_ALIGNMENT_FAULT_LOCALS 240 241 #define ENABLE_ALIGNMENT_FAULTS \ 242 and r7, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\ 243 GET_CURCPU(r4) /* r4 = cpuinfo */ 244 245 246 #define DO_AST_AND_RESTORE_ALIGNMENT_FAULTS \ 247 DO_PENDING_SOFTINTS ;\ 248 GET_CPSR(r5) /* save CPSR */ ;\ 249 CPSID_I(r1, r5) /* Disable interrupts */ ;\ 250 cmp r7, #(PSR_USR32_MODE) ;\ 251 bne 2f /* Nope, get out now */ ;\ 252 DO_PENDING_AST(2f) /* Pending AST? */ ;\ 253 2: /* done */ 254 #endif /* EXEC_AOUT */ 255 256 #ifndef _ARM_ARCH_6 257 #ifdef ARM_LOCK_CAS_DEBUG 258 #define LOCK_CAS_DEBUG_LOCALS \ 259 .L_lock_cas_restart: ;\ 260 .word _C_LABEL(_lock_cas_restart) 261 262 #if defined(__ARMEB__) 263 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 264 ble 99f ;\ 265 ldr r0, .L_lock_cas_restart ;\ 266 ldmia r0, {r1-r2} /* load ev_count */ ;\ 267 adds r2, r2, #1 /* 64-bit incr (lo) */ ;\ 268 adc r1, r1, #0 /* 64-bit incr (hi) */ ;\ 269 stmia r0, {r1-r2} /* store ev_count */ 270 #else /* __ARMEB__ */ 271 #define LOCK_CAS_DEBUG_COUNT_RESTART \ 272 ble 99f ;\ 273 ldr r0, .L_lock_cas_restart ;\ 274 ldmia r0, {r1-r2} /* load ev_count */ ;\ 275 adds r1, r1, #1 /* 64-bit incr (lo) */ ;\ 276 adc r2, r2, #0 /* 64-bit incr (hi) */ ;\ 277 stmia r0, {r1-r2} /* store ev_count */ 278 #endif /* __ARMEB__ */ 279 #else /* ARM_LOCK_CAS_DEBUG */ 280 #define LOCK_CAS_DEBUG_LOCALS /* nothing */ 281 #define LOCK_CAS_DEBUG_COUNT_RESTART /* nothing */ 282 #endif /* ARM_LOCK_CAS_DEBUG */ 283 284 #define LOCK_CAS_CHECK_LOCALS \ 285 .L_lock_cas: ;\ 286 .word _C_LABEL(_lock_cas) ;\ 287 .L_lock_cas_end: ;\ 288 .word _C_LABEL(_lock_cas_end) ;\ 289 LOCK_CAS_DEBUG_LOCALS 290 291 #define LOCK_CAS_CHECK \ 292 ldr r0, [sp] /* get saved PSR */ ;\ 293 and r0, r0, #(PSR_MODE) /* check for SVC32 mode */ ;\ 294 cmp r0, #(PSR_SVC32_MODE) ;\ 295 bne 99f /* nope, get out now */ ;\ 296 ldr r0, [sp, #(TF_PC)] ;\ 297 ldr r1, .L_lock_cas_end ;\ 298 cmp r0, r1 ;\ 299 bge 99f ;\ 300 ldr r1, .L_lock_cas ;\ 301 cmp r0, r1 ;\ 302 strgt r1, [sp, #(TF_PC)] ;\ 303 LOCK_CAS_DEBUG_COUNT_RESTART ;\ 304 99: 305 306 #else 307 #define LOCK_CAS_CHECK /* nothing */ 308 #define LOCK_CAS_CHECK_LOCALS /* nothing */ 309 #endif 310 311 /* 312 * ASM macros for pushing and pulling trapframes from the stack 313 * 314 * These macros are used to handle the trapframe structure defined above. 315 */ 316 317 /* 318 * PUSHFRAME - macro to push a trap frame on the stack in the current mode 319 * Since the current mode is used, the SVC lr field is not defined. 320 */ 321 322 #ifdef CPU_SA110 323 /* 324 * NOTE: r13 and r14 are stored separately as a work around for the 325 * SA110 rev 2 STM^ bug 326 */ 327 #define PUSHUSERREGS \ 328 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 329 add r0, sp, #(TF_USR_SP-TF_R0); /* Adjust the stack pointer */ \ 330 stmia r0, {r13-r14}^ /* Push the user mode registers */ 331 #else 332 #define PUSHUSERREGS \ 333 stmia sp, {r0-r14}^ /* Push the user mode registers */ 334 #endif 335 336 #define PUSHFRAME \ 337 str lr, [sp, #-4]!; /* Push the return address */ \ 338 sub sp, sp, #(TF_PC-TF_R0); /* Adjust the stack pointer */ \ 339 PUSHUSERREGS; /* Push the user mode registers */ \ 340 mov r0, r0; /* NOP for previous instruction */ \ 341 mrs r0, spsr; /* Get the SPSR */ \ 342 str r0, [sp, #-TF_R0]! /* Push the SPSR on the stack */ 343 344 /* 345 * Push a minimal trapframe so we can dispatch an interrupt from the 346 * idle loop. The only reason the idle loop wakes up is to dispatch 347 * interrupts so why take the avoid of a full exception when we can do 348 * something minimal. 349 */ 350 #define PUSHIDLEFRAME \ 351 str lr, [sp, #-4]!; /* save SVC32 lr */ \ 352 str r6, [sp, #(TF_R6-TF_PC)]!; /* save callee-saved r6 */ \ 353 str r4, [sp, #(TF_R4-TF_R6)]!; /* save callee-saved r4 */ \ 354 mrs r0, cpsr; /* Get the CPSR */ \ 355 str r0, [sp, #(-TF_R4)]! /* Push the CPSR on the stack */ 356 357 /* 358 * Push a trapframe to be used by cpu_switchto 359 */ 360 #define PUSHSWITCHFRAME(rX) \ 361 mov ip, sp; \ 362 sub sp, sp, #(TRAPFRAMESIZE-TF_R12); /* Adjust the stack pointer */ \ 363 push {r4-r11}; /* Push the callee saved registers */ \ 364 sub sp, sp, #TF_R4; /* reserve rest of trapframe */ \ 365 str ip, [sp, #TF_SVC_SP]; \ 366 str lr, [sp, #TF_SVC_LR]; \ 367 str lr, [sp, #TF_PC]; \ 368 mrs rX, cpsr; /* Get the CPSR */ \ 369 str rX, [sp, #TF_SPSR] /* save in trapframe */ 370 371 #define PUSHSWITCHFRAME1 \ 372 mov ip, sp; \ 373 sub sp, sp, #(TRAPFRAMESIZE-TF_R8); /* Adjust the stack pointer */ \ 374 push {r4-r7}; /* Push some of the callee saved registers */ \ 375 sub sp, sp, #TF_R4; /* reserve rest of trapframe */ \ 376 str ip, [sp, #TF_SVC_SP]; \ 377 str lr, [sp, #TF_SVC_LR]; \ 378 str lr, [sp, #TF_PC] 379 380 #if defined(_ARM_ARCH_DWORD_OK) && __ARM_EABI__ 381 #define PUSHSWITCHFRAME2 \ 382 strd r10, [sp, #TF_R10]; /* save r10 & r11 */ \ 383 strd r8, [sp, #TF_R8]; /* save r8 & r9 */ \ 384 mrs r0, cpsr; /* Get the CPSR */ \ 385 str r0, [sp, #TF_SPSR] /* save in trapframe */ 386 #else 387 #define PUSHSWITCHFRAME2 \ 388 add r0, sp, #TF_R8; /* get ptr to r8 and above */ \ 389 stmia r0, {r8-r11}; /* save rest of registers */ \ 390 mrs r0, cpsr; /* Get the CPSR */ \ 391 str r0, [sp, #TF_SPSR] /* save in trapframe */ 392 #endif 393 394 /* 395 * PULLFRAME - macro to pull a trap frame from the stack in the current mode 396 * Since the current mode is used, the SVC lr field is ignored. 397 */ 398 399 #define PULLFRAME \ 400 ldr r0, [sp], #TF_R0; /* Pop the SPSR from stack */ \ 401 msr spsr_fsxc, r0; \ 402 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 403 mov r0, r0; /* NOP for previous instruction */ \ 404 add sp, sp, #(TF_PC-TF_R0); /* Adjust the stack pointer */ \ 405 ldr lr, [sp], #0x0004 /* Pop the return address */ 406 407 #define PULLIDLEFRAME \ 408 add sp, sp, #TF_R4; /* Adjust the stack pointer */ \ 409 ldr r4, [sp], #(TF_R6-TF_R4); /* restore callee-saved r4 */ \ 410 ldr r6, [sp], #(TF_PC-TF_R6); /* restore callee-saved r6 */ \ 411 ldr lr, [sp], #4 /* Pop the return address */ 412 413 /* 414 * Pop a trapframe to be used by cpu_switchto (don't touch r0 & r1). 415 */ 416 #define PULLSWITCHFRAME \ 417 add sp, sp, #TF_R4; /* Adjust the stack pointer */ \ 418 pop {r4-r11}; /* pop the callee saved registers */ \ 419 add sp, sp, #(TF_PC-TF_R12); /* Adjust the stack pointer */ \ 420 ldr lr, [sp], #4; /* pop the return address */ 421 422 /* 423 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode 424 * This should only be used if the processor is not currently in SVC32 425 * mode. The processor mode is switched to SVC mode and the trap frame is 426 * stored. The SVC lr field is used to store the previous value of 427 * lr in SVC mode. 428 * 429 * NOTE: r13 and r14 are stored separately as a work around for the 430 * SA110 rev 2 STM^ bug 431 */ 432 433 #ifdef _ARM_ARCH_6 434 #define SET_CPSR_MODE(tmp, mode) \ 435 cps #(mode) 436 #else 437 #define SET_CPSR_MODE(tmp, mode) \ 438 mrs tmp, cpsr; /* Get the CPSR */ \ 439 bic tmp, tmp, #(PSR_MODE); /* Fix for SVC mode */ \ 440 orr tmp, tmp, #(mode); \ 441 msr cpsr_c, tmp /* Punch into SVC mode */ 442 #endif 443 444 #define PUSHXXXREGSANDSWITCH \ 445 stmdb sp, {r0-r3}; /* Save 4 registers */ \ 446 mov r0, lr; /* Save xxx32 r14 */ \ 447 mov r1, sp; /* Save xxx32 sp */ \ 448 mrs r3, spsr; /* Save xxx32 spsr */ \ 449 SET_CPSR_MODE(r2, PSR_SVC32_MODE) 450 451 #ifdef KDTRACE_HOOKS 452 #define PUSHDTRACEGAP \ 453 and r2, r3, #(PSR_MODE); \ 454 cmp r2, #(PSR_SVC32_MODE); /* were we in SVC mode? */ \ 455 mov r2, sp; \ 456 subeq r2, r2, #(4 * 16); /* if so, leave a gap for dtrace */ 457 #else 458 #define PUSHDTRACEGAP \ 459 mov r2, sp 460 #endif 461 462 #define PUSHTRAPFRAME(rX) \ 463 bic r2, rX, #7; /* Align new SVC sp */ \ 464 str r0, [r2, #-4]!; /* Push return address */ \ 465 stmdb r2!, {sp, lr}; /* Push SVC sp, lr */ \ 466 mov sp, r2; /* Keep stack aligned */ \ 467 msr spsr_fsxc, r3; /* Restore correct spsr */ \ 468 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ 469 sub sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \ 470 PUSHUSERREGS; /* Push the user mode registers */ \ 471 mov r0, r0; /* NOP for previous instruction */ \ 472 mrs r0, spsr; /* Get the SPSR */ \ 473 str r0, [sp, #-TF_R0]! /* Push the SPSR onto the stack */ 474 475 #define PUSHFRAMEINSVC \ 476 PUSHXXXREGSANDSWITCH; \ 477 PUSHTRAPFRAME(sp) 478 479 /* 480 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack 481 * in SVC32 mode and restore the saved processor mode and PC. 482 * This should be used when the SVC lr register needs to be restored on 483 * exit. 484 */ 485 486 #define PULLFRAMEFROMSVCANDEXIT \ 487 ldr r0, [sp], #TF_R0; /* Pop the SPSR from stack */ \ 488 msr spsr_fsxc, r0; /* restore SPSR */ \ 489 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 490 mov r0, r0; /* NOP for previous instruction */ \ 491 add sp, sp, #(TF_SVC_SP-TF_R0); /* Adjust the stack pointer */ \ 492 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ 493 494 #endif /* _LOCORE */ 495 496 #endif /* _ARM32_FRAME_H_ */ 497
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